Multitasking, Time Sharing Patents (Class 718/107)
  • Patent number: 9131489
    Abstract: Embodiments of the present invention relate to the communication field, and disclose a resource allocation method, apparatus, and system, which solve a problem that the size of resource allocation indication information increases with the increase of the transmission bandwidth, and redundancy of physical layer signaling increases with the increase of the transmission bandwidth. The method includes: allocating time-frequency resources in specific bandwidth to a terminal, where the specific bandwidth is a band less than or equal to system bandwidth; determining the size of resource allocation information according to the specific bandwidth; and sending the resource allocation information to the terminal to indicate the allocated time-frequency resources. The embodiments of the present invention are mainly applied to the process in which the base station allocates time-frequency resources to the terminal.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: September 8, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shulan Feng, Jinnan Liu, Yajuan Li
  • Patent number: 9092262
    Abstract: The invention includes a computerized method responding to a navigation cue from a user by saving the writable state of the application and directing the computer through the window operating system to perform the navigation task 36 indicated by the navigation cue. The invention includes the following, which will each be discussed in turn. An alteration mechanism including means for altering window operating system by altering the hook triggered by each navigation cue to integrate saving the writable state. The window operating system integrating response to each navigation cue and saving the writable state. Source code artifacts which can be installed to implement navigation cues triggering saving the writable state. A business method generating revenue for a business entity.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: July 28, 2015
    Assignee: i-Rescue Technologies LLC
    Inventor: Jan Rippingale
  • Patent number: 9081609
    Abstract: A system and method are disclosed for an image processing system including a threaded scheduler providing compact and efficient dataflow as a pipeline management and data flow layer.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: July 14, 2015
    Assignee: Xerox Corporation
    Inventors: Phillip J. Emmett, Terry C. Wells, Dennis L. Venable, James E. Bollman, Thomas C. Rich, David E. Rumph
  • Patent number: 9076017
    Abstract: In one embodiment, a method comprises providing an apparatus having exclusive access to each of one or more central processing units (CPUs) of a computing system and exclusive access to host resources of the computing system; and controlling, by the apparatus, execution of a virtual machine in the computing system based on the apparatus controlling access to any one of the CPUs or any one of the host resources according to prescribed policies for the virtual machine, the prescribed policies maintained exclusively by the apparatus.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: July 7, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Sateesh K Addepalli, Raghuram S Sudhaakar
  • Patent number: 9069609
    Abstract: One embodiment of the present invention sets forth a technique for assigning a compute task to a first processor included in a plurality of processors. The technique involves analyzing each compute task in a plurality of compute tasks to identify one or more compute tasks that are eligible for assignment to the first processor, where each compute task is listed in a first table and is associated with a priority value and an allocation order that indicates relative time at which the compute task was added to the first table. The technique further involves selecting a first task compute from the identified one or more compute tasks based on at least one of the priority value and the allocation order, and assigning the first compute task to the first processor for execution.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: June 30, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Karim M. Abdalla, Lacky V. Shah, Jerome F. Duluk, Jr., Timothy John Purcell, Tanmoy Mandal, Gentaro Hirota
  • Patent number: 9054962
    Abstract: A container that manages access to protected resources using rules to intelligently manage them includes an environment having a set of software and configurations that are to be managed. A rule engine, which executes the rules, may be called reactively when software accesses protected resources. The engine uses a combination of embedded and configurable rules. It may be desirable to assign and manage rules per process, per resource (e.g. file, registry, etc.), and per user. Access rules may be altitude-specific access rules.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: June 9, 2015
    Assignee: Numecent Holdings, Inc.
    Inventors: Arthur S. Hitomi, Robert Tran, Peter Kammer, Doug Pfiffner, Huy Nguyen
  • Patent number: 9047682
    Abstract: The disclosure provides a method for image processing, including: loading and decrypting an image file to obtain an original image, and saving the original image; shrinking the original image to obtain a pending image with a preset resolution, and saving the pending image; editing the pending image and previewing the pending image in real time; and editing the original image after the real-time previewing. The disclosure also provides a system for image processing. the disclosure can increase efficiency of real-time preview at the time of image editing.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: June 2, 2015
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Feng Gao, Yuan Huang, Jia Wang
  • Patent number: 9047138
    Abstract: Provided is a method and apparatus for ensuring a deterministic execution characteristic of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A lock controlling apparatus based on a deterministic progress index (DPI) may include a loading unit to load a DPI of a first core and a DPI of a second core among DPIs of a plurality of cores at a lock acquisition point in time of each thread, a comparison unit to compare the DPI of the first core and the DPI of the second core, and a controller to assign a lock to a thread of the first core when the DPI of the first core is less than the DPI of the second core and when the second core corresponds to a last core to be compared among the plurality of cores.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: June 2, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Sam Shin, Seung Won Lee, Min Young Son, Shi Hwa Lee
  • Publication number: 20150150024
    Abstract: A method of detecting stack overflows includes the following steps: storing in at least one dedicated register at least one data item chosen from: a data item (SPHaut) indicating a maximum permitted value for a stack pointer, and a data item (SPBas) indicating a minimum permitted value for said stack pointer; effecting a comparison between a current value (SP) or past value (SPMin, SPMax) of said stack pointer and said data item or each of said data items; and generating a stack overflow exception if said comparison indicates that said current or past value of said stack pointer is greater than said maximum permitted value or less than said minimum permitted value. A processor for implementing such a method is also provided.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Philippe GROSSI, Dominique DAVID, Francois BRUN
  • Publication number: 20150150023
    Abstract: A system for conducting parallelization of tasks is disclosed. The system includes an interface for receiving messages comprising a representation of logic describing two tasks to be executed in parallel, the message further comprising a content payload for use in the tasks. The system further includes a parallel processing grid comprising devices running on independent machines, each device comprising a processing manager unit and at least two processing units. The processing manager is configured to parse the received messages and to distribute the at least two tasks to the at least two processing units for independent and parallel processing relative to the content payload.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Applicant: Decooda International, Inc.
    Inventors: David Johnson, Charles Wardell
  • Publication number: 20150150022
    Abstract: There is provided an information processing apparatus including a determination unit configured to determine, for each application, shift time length for each state shift while an application changes from a non-usable state to a usable state, and a control unit configured to shift a state of an application to the non-usable state, the application being specified on the basis of a result of the determination by the determination unit.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 28, 2015
    Inventors: Masatoshi UENO, Kenichi SETA, Masato NOGUCHI
  • Publication number: 20150143384
    Abstract: Network system being configured to execute I/O commands and application commands in parallel and comprising a network and at least one network node, wherein the at least one network node is connected to the network via a network adapter and is configured to run several processes and/or threads in parallel, wherein the at least one network node comprises or is configured to establish a common communication channel (C-channel) to be used by the several processes and/or threads for data communication with the network via the network adapter, wherein the C-channel comprises or is established to comprise a work queue (WQ) for execution of I/O commands and a completion queue (CQ) for indication of a status of I/O commands, and wherein the at least one network node, especially its comprised or to be established C-channel, is configured for an exclusive access of precisely one single process or thread out of the several processes and/or threads to the CQ of the C-channel at a particular time.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventor: Carsten Lojewski
  • Patent number: 9038075
    Abstract: A system and a method are disclosed for batch execution of system calls in an operating system. In one implementation, a processing device configures a system call batching buffer table in a user space of an operating system, the system call batching buffer table including a plurality of system call units, associates a system call number with the system call batching buffer table, and issues a trap instruction to a kernel of the operating system to execute at least one of the plurality of system call units, the trap instruction including the system call number.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: May 19, 2015
    Assignee: Red Hat, Inc.
    Inventor: Neil R. T. Horman
  • Publication number: 20150135194
    Abstract: Techniques for estimating time remaining for an operation are described. Examples operations include file operations, such as file move operations, file copy operations, and so on. A wide variety of different operations may be considered in accordance with the claimed embodiments, further examples of which are discussed below. In at least some embodiments, estimating a time remaining for an operation can be based on a state of the operation. A state of an operation, for example, can be based on events related to the operation itself, such as the operation being initiated, paused, resumed, and so on. A state of an operation can also be based on events related to other operations.
    Type: Application
    Filed: January 21, 2015
    Publication date: May 14, 2015
    Inventors: Francisco Alvarez Cavazos, Jordi Mola
  • Publication number: 20150134841
    Abstract: Network system being configured to execute I/O commands and application commands in parallel and comprising a network and at least one network node, wherein the at least one network node is connected to the network via a network adapter and is configured to run several processes and/or threads in parallel, wherein the at least one network node comprises or is configured to establish a common communication channel (C-channel) to be used by the several processes and/or threads for data communication with the network via the network adapter, wherein the C-channel comprises or is established to comprise a work queue (WQ) for execution of I/O commands and a completion queue (CQ) for indication of a status of I/O commands, and wherein the at least one network node, especially its comprised or to be established C-channel, is configured for an exclusive access of precisely one single process or thread out of the several processes and/or threads to the CQ of the C-channel at a particular time.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Inventor: Carsten Lojewski
  • Publication number: 20150128151
    Abstract: A method is disclosed for mapping an integral into a thread of a parallel architecture, in the course of which the integral is mapped into a summation expressed by coefficient values and summation values, and a directed graph is generated corresponding to the computation of the summation. Furthermore, in the course of the method a level of a traversal sequence to each of the nodes is assigned, respectively, and at each level off the traversal sequence, a storage location of the intermediate value corresponding to the edge connected with its input to the node corresponding to the given level is specified in a memory corresponding to the thread and including a register storage, a local storage, and a global storage. A system is also disclosed for mapping an integral into a thread of a parallel architecture.
    Type: Application
    Filed: May 31, 2013
    Publication date: May 7, 2015
    Applicant: StreamNovation Kft.
    Inventors: Adam Rak, Gergely Feldhoffer, Gergely Balazs Soos, Tibor Holtzl, Balazs Oroszi, Gyorgy Gabor Cserey
  • Patent number: 9027028
    Abstract: A method and apparatus controls use of a computing resource by multiple tenants in DBaaS service. The method includes intercepting a task that is to access a computer resource, the task being an operating system process or thread; identifying a tenant that is in association with the task from the multiple tenants; determining other tasks of the tenant that access the computing resource; and controlling the use of the computing resource by the task, so that the total amount of usage of the computing resource by the task and the other tasks does not exceed the limit of usage of the computing resource for the tenant.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wen Hao An, Li Ya Fan, Bo Gao, Chang Jie Guo, Berthold Reinwald, Wei Sun, Ning Wang, Zhi Hu Wang
  • Patent number: 9021493
    Abstract: Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky, Chung-Lung K. Shum
  • Patent number: 9021495
    Abstract: Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).
    Type: Grant
    Filed: March 3, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky, Chung-Lung K. Shum
  • Publication number: 20150113542
    Abstract: A method is provided for controlling a compute cluster having a plurality of nodes. Each of the plurality of nodes has a respective computing device with a main server and one or more coprocessor-based hardware accelerators. The method includes receiving a plurality of jobs for scheduling. The method further includes scheduling the plurality of jobs across the plurality of nodes responsive to a knapsack-based sharing-aware schedule generated by a knapsack-based sharing-aware scheduler. The knapsack-based sharing-aware schedule is generated to co-locate together on a same computing device certain ones of the plurality of jobs that are mutually compatible based on a set of requirements whose fulfillment is determined using a knapsack-based sharing-aware technique that uses memory as a knapsack capacity and minimizes makespan while adhering to coprocessor memory and thread resource constraints.
    Type: Application
    Filed: October 3, 2014
    Publication date: April 23, 2015
    Inventors: Srihari Cadambi, Giuseppe Coviello, Srimat Chakradhar
  • Publication number: 20150113543
    Abstract: Systems and methods of managing break events may provide for detecting a first break event from a first event source and detecting a second break event from a second event source. In one example, the event sources can include devices coupled to a platform as well as active applications on the platform. Issuance of the first and second break events to the platform can be coordinated based on at least in part runtime information associated with the platform.
    Type: Application
    Filed: December 26, 2014
    Publication date: April 23, 2015
    Inventors: Ren Wang, Jr-Shian Tsai, Tsung-Yuan C. Tai, Mesut A. Ergin, Prakash N. Iyer, Bruce L. Fleming
  • Patent number: 9015504
    Abstract: A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions; (2) a storage for a thread power management configuration; and (3) a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads, wherein said power control circuit is operable to establish different power voltages in different parts of the at least one processor pipeline depending on the threads.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Thang Tran
  • Patent number: 9009726
    Abstract: A “Concurrent Sharing Model” provides a programming model based on revisions and isolation types for concurrent revisions of states, data, or variables shared between two or more concurrent tasks or programs. This model enables revisions of shared states, data, or variables to maintain determinacy despite nondeterministic scheduling between concurrent tasks or programs. More specifically, the Concurrent Sharing Model provides various techniques wherein shared states, data, or variables are conceptually replicated on forks, and only copied or written if necessary, then deterministically merged on joins such that concurrent tasks or programs can work with independent local copies of the shared states, data, or variables while ensuring automated conflict resolution.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: April 14, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sebastian Burckhardt, Daniel Johannes Pieter Leijen, Alexandro Baldassin
  • Patent number: 9009718
    Abstract: Large scale internet services may be implemented using multiple discrete server instances. Some tasks of the large scale internet services may be singleton tasks, which may be advantageously processed by a sub-set of the server instances (e.g., merely one instance). Accordingly, as provided herein, a singleton task may be processed in a reliable manner based upon one or more instances of a protocol executed across a set of arbitrary autonomous server instances. In one example, the protocol may determine whether a lease for a singleton task is valid or expired. If the lease is expired, then an attempt to claim the lease may be performed by updating a current lease expiration with a new lease expiration. If the attempt is successful, then the singleton task may be processed until the new lease expiration expires.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: April 14, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Eric M. Patey, Jason Schleifer
  • Patent number: 9003420
    Abstract: A technique for resolving deadlocks between an RCU subsystem and an operating system scheduler. An RCU reader manipulates a counter when entering and exiting an RCU read-side critical section. At the entry, the counter is incremented. At the exit, the counter is manipulated differently depending on the counter value. A first counter manipulation path is taken when the counter indicates a task-context RCU reader is exiting an outermost RCU read-side critical section. This path includes condition-based processing that may result in invocation of the operating system scheduler. The first path further includes a deadlock protection operation that manipulates the counter to prevent an intervening RCU reader from taking the same path. The second manipulation path is taken when the counter value indicates a task-context RCU reader is exiting a non-outermost RCU read-side critical section, or an RCU reader is nested within the first path. This path bypasses the condition-based processing.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventor: Paul E. McKenney
  • Patent number: 8997111
    Abstract: A system and method deterministically switches context in a real-time scheduler to guarantee schedule periodicity. The method includes determining a time slice for each of the plurality of processes. The method includes determining a time slice switch duration between consecutive ones of the time slices. The method includes determining a starting point for each time slice. The method includes generating a schedule as a function of the time slices, the time slice switch durations, and the starting points of the time slices. The schedule includes an order for each of the time slices for a respective one of the plurality of processes. Each of the time slices and each of the time slice switch durations are required to run for their entire duration to guarantee a periodicity of the schedule.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 31, 2015
    Assignee: Wind River Systems, Inc.
    Inventors: Keith Backensto, Thierry Preyssler
  • Patent number: 8997109
    Abstract: Disclosed herein are an apparatus and method for managing a data stream distributed parallel processing service. The apparatus includes a service management unit, a Quality of Service (QoS) monitoring unit, and a scheduling unit. The service management unit registers a plurality of tasks constituting the data stream distributed parallel processing service. The QoS monitoring unit gathers information about the load of the plurality of tasks and information about the load of a plurality of nodes constituting a cluster which provides the data stream distributed parallel processing service. The scheduling unit arranges the plurality of tasks by distributing the plurality of tasks among the plurality of nodes based on the information about the load of the plurality of tasks and the information about the load of the plurality of nodes.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Myung-Cheol Lee, Hyun-Hwa Choi, Hun-Soon Lee, Byoung-Seob Kim, Mi-Young Lee
  • Patent number: 8997110
    Abstract: A technique for resolving deadlocks between an RCU subsystem and an operating system scheduler. An RCU reader manipulates a counter when entering and exiting an RCU read-side critical section. At the entry, the counter is incremented. At the exit, the counter is manipulated differently depending on the counter value. A first counter manipulation path is taken when the counter indicates a task-context RCU reader is exiting an outermost RCU read-side critical section. This path includes condition-based processing that may result in invocation of the operating system scheduler. The first path further includes a deadlock protection operation that manipulates the counter to prevent an intervening RCU reader from taking the same path. The second manipulation path is taken when the counter value indicates a task-context RCU reader is exiting a non-outermost RCU read-side critical section, or an RCU reader is nested within the first path. This path bypasses the condition-based processing.
    Type: Grant
    Filed: November 30, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventor: Paul E. McKenney
  • Patent number: 8990783
    Abstract: Embodiments can include computer-implemented methods or non-transitory computer readable media storing executable instructions. The method or instructions can perform execution scheduling for code generated from an executable graphical model, where the generated code is executed on a target. The method/instructions can perform execution scheduling for a first code portion having a first execution rate, and a second code portion having a second execution rate that is temporally related to the first execution rate. The execution scheduling can account for target environment characteristics obtained from a target, can use an execution schedule, and can account for optimizations related to the first code portion or the second code portion. The method/instructions can further schedule execution of the first code portion and the second code portion in generated executable code based on the performing.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: March 24, 2015
    Assignee: The MathWorks, Inc.
    Inventors: Biao Yu, Jim Carrick, Pieter J. Mosterman
  • Publication number: 20150082320
    Abstract: A data processing apparatus includes a first storage that stores information pertaining to an order in which multiple process flows are executed, the execution of the multiple process flows being started by input of data and terminated by output of the data in a format usable for a user, a reception part that receives input data with respect to one of the multiple process flows, an execution part that executes the one of the multiple process flows on the input data, and a second storage that stores information indicating the one of the multiple process flows executed by the execution part. The execution part identifies a predetermined process flow to be executed with respect to the input data by referring to the first and second storages. The predetermined process flow is a process flow to be performed earliest among the multiple process flows that are not yet executed.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 19, 2015
    Applicant: RICOH COMPANY, LTD.
    Inventors: Seijiro HORI, Atsuko YAGI, Ayumi MIHARA, Takayori NISHIDA, Mitsuhiko HIROSE
  • Publication number: 20150082319
    Abstract: A method of traffic management implemented in a multi-core device comprising a first core and a second core, the method comprising receiving a first plurality of data flows for the first core and a second plurality of data flows for the second core, assigning a first thread running on the first core to the first plurality of data flows, assigning a second thread running on the second core to the second plurality of data flows, processing the first plurality of data flows using the first thread, and processing the second plurality of data flows using the second thread, wherein at least one of the first plurality of data flows and at least one of the second plurality of data flows are processed in parallel.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicant: Futurewei Technologies, Inc.
    Inventors: Deming Liu, Xiaoyong Yi
  • Patent number: 8984527
    Abstract: A system and method donates time from a first process to a second process. The method includes determining a time slice for each of a plurality of processes to generate a schedule therefrom. The method includes determining a time donation scheme for the first process, the time donation scheme indicative of a donation policy in which the execution time of the first process is donated to the second process. During execution of the processes, the method includes receiving a request from the first process for a time donation to the second process and executing the second process during the time slice of the first process.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 17, 2015
    Assignee: Wind River Systems, Inc.
    Inventors: Keith Backensto, Thierry Preyssler
  • Patent number: 8984494
    Abstract: An embodiment can include one or more computer readable media storing executable instructions for performing execution scheduling for code generated from an executable graphical model. The media can store instructions for accessing a first code portion having a first priority, and a second code portion having a second priority, where the second priority has a relationship with the first priority. The media can store instructions for accessing target environment characteristics that indicate a performance of the target environment, and for performing execution scheduling for the first code portion and the second code portion, the execution scheduling taking into account the target environment characteristics, the execution scheduling using an execution schedule.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: March 17, 2015
    Assignee: The MathWorks, Inc.
    Inventors: James E. Carrick, Biao Yu
  • Publication number: 20150074682
    Abstract: A core executing processes in plural threads specifies one gate to read out a state of the gate from a thread progress control unit holding information of plural gates disposed in a loop state, setting a state of a gate disposed subsequently relative to a gate when a state of the gate is set to a first state to a second state, and setting the state of the gate to the first state when a certain period of time elapses from a first request of reading the state for the gate which is set to the second state, by every certain process in each thread. The core executes a next process when the state of the specified gate is the first state, and makes the execution of the next process wait until the state becomes the first state when it is not the first state.
    Type: Application
    Filed: September 2, 2014
    Publication date: March 12, 2015
    Inventor: Akira NARUSE
  • Patent number: 8978038
    Abstract: A thread group generator generates from a received workload a plurality of thread groups. Each thread group consists of a plurality of threads, and at least one thread group has an interthread dependency existing between the plurality of threads. Each thread may be either an active thread whose output is required to form the result data, or a dummy thread required to resolve the inter-thread dependency for one of the active threads but whose output is not required to form the result data. A thread execution unit then executes each thread within a thread group received from the generator by executing a predetermined program. Execution flow modification circuitry is responsive to the received thread group having at least one dummy thread, to cause the unit to selectively omit at least part of the execution of at least one of the plurality of instructions when executing each dummy thread.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: March 10, 2015
    Assignee: ARM Limited
    Inventors: Andreas Due Engh-Halstvedt, Jorn Nystad
  • Publication number: 20150067699
    Abstract: In response to determining that an activity has been postponed (e.g., interrupted or deferred), a computer system stores a record indicating that the activity is postponed. In response to determining that another activity has become active, the computer system stores a record indicating that the other activity is active. The computer system reminds a user to return to the postponed in response to determining that a reminder condition associated with the postponed activity has been satisfied. For example, the computer system may remind the user to return to the postponed activity in response to determining that the other activity has been completed.
    Type: Application
    Filed: March 4, 2014
    Publication date: March 5, 2015
    Inventor: Robert Plotkin
  • Publication number: 20150067700
    Abstract: A method and an apparatus for performing task scheduling in a terminal are provided. The terminal includes at least two different types of cores and determines if a change in a task state has occurred in response to at least one of the two cores, If a change in a task state has occurred, the terminal determines, for said at least one core, the variation in the duration of each of a plurality of tasks being executed, predicts the duration of each of the plurality of tasks on the basis of the change in the task state using the determined variation, and performs task scheduling for said at least one core in accordance with the predicted duration.
    Type: Application
    Filed: April 11, 2013
    Publication date: March 5, 2015
    Applicant: Sansung Electronics Co., Ltd.
    Inventors: Rakie Kim, Myung-Sun Kim
  • Patent number: 8972994
    Abstract: Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass code to execute in a managed runtime in response to receiving the object lock request. The example method also includes identifying a type of instruction set architecture (ISA) associated with the processor, invoking a checkpoint instruction for the processor based on the identified ISA, suspending the object lock code from executing and executing target code when the object is uncontended, and allowing the object lock code to execute when the object is contended.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Suresh Srinivas, Stephen H. Dohrmann, Mingqiu Sun, Uma Srinivasan, Ravi Rajwar, Konrad K. Lai
  • Publication number: 20150058866
    Abstract: A processor-implemented method for implementing a shared counter architecture is provided. The method may include receiving, by a worker thread, an application request; recording, by a common timer thread, a shared timer value and acquiring, by the worker thread, the shared timer value. The method may further include recording, by the common timer thread, a shared calibration factor; acquiring, by the worker thread, a configuration value corresponding to the application request and generating, by the worker thread, a calibrated timeout interval for the application request based on the shared calibration factor, the shared timer value, and the configuration value. The method may further include registering, by the worker thread, the calibrated timeout interval for the application request on a current timeout list; determining, by the common timer thread, a timeout occurrence for the application request based on the registered calibrated timeout interval; and releasing resources based on the timeout occurrence.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: James V. Farmer, Daniel S. Gritter, Glenn I. Katzen
  • Publication number: 20150058857
    Abstract: An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.
    Type: Application
    Filed: June 27, 2014
    Publication date: February 26, 2015
    Inventor: Mark Henrik Sandstrom
  • Patent number: 8966147
    Abstract: A method for resolving deadlock in a multi-threaded computing system using a novel lock lease is disclosed. A first thread leases a lock held by the first thread to a second thread different from the first thread. The leasing transfers control of the lock to the second thread while the first thread retains ownership of the lock. To lease the lock: (1) the second thread applies for the lease from the first thread; (2) the first thread grants the lease; (3) the first thread waits for the second thread to complete a task; (4) the second thread terminates the lease; (5) the first thread confirms termination of the lease. The first thread receives control of the lock back from the second thread after the second thread has finished using resources controlled by the lock. The second thread also can sublease the lock to a third thread.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 24, 2015
    Inventors: Wenguang Wang, Richard Paul Spillane
  • Patent number: 8966484
    Abstract: An information processing apparatus makes a plurality of threads concurrently execute tasks stored in a task queue associated with the thread a prescribed number of times of execution. The information processing apparatus includes a processor that executes the plurality of threads that executes a procedure. The procedure includes generating a task from among a plurality of tasks into which a serial program processing corresponding to a processing request is divided, selecting the task queue associated with one of the plurality of threads, enqueuing the generated task to the selected task queue, dequeuing the enqueued task to the task queue associated with the thread, and executing the dequeued task.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Kei Hamada, Kouichirou Amemiya, Yasushi Kurokawa, Yumiko Ogata, Eitatsu Yoshida
  • Publication number: 20150052538
    Abstract: Software development tools and techniques for configuring parallel processing systems to execute software modules implementing processes for solving complex problems, including over-the-counter trading processes and foreign exchange trading processes, to execute quickly and efficiently. The parallel processing system may include low-cost, consumer-grade multicore processing units. A process for solving a complex problem may be divided into software modules, including by evaluating the process to determine discrete processing steps that produce an intermediate result on which later steps of the process depend. The software modules created for a process may form a template processing chain describing multiple processing chains of the process that are to be executed.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 19, 2015
    Applicant: oneZero Financial Systems, LLC
    Inventors: Christopher John Kline, Jesse Johnson, Andrew Ralich
  • Patent number: 8959517
    Abstract: A scheduler in a process of a computer system schedules tasks of a task group for concurrent execution by multiple execution contexts. The scheduler provides a mechanism that allows the task group to be cancelled by an arbitrary execution context or an asynchronous error state. When a task group is cancelled, the scheduler sets a cancel indicator in each execution context that is executing tasks corresponding to the cancelled task group and performs a cancellation process on each of the execution contexts where a cancel indicator is set. The scheduler also creates local aliases to allow task groups to be used without synchronization by execution contexts that are not directly bound to the task groups.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: February 17, 2015
    Assignee: Microsoft Corporation
    Inventors: William R. Messmer, David Callahan, Paul F. Ringseth, Niklas Gustafsson
  • Patent number: 8954986
    Abstract: Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Mohan Rajagopalan, Ali-Reza Adl-Tabatabai, Yang Ni, Adam Welc, Richard L. Hudson
  • Patent number: 8949641
    Abstract: An information processing apparatus that shortens the waiting time that a user feels when restoration from a hibernation state is performed, a method for controlling the same, and a recording medium are provided. To accomplish this, when restoration from a power saving state (hibernation state) is performed, the information processing apparatus of the present invention restores only an operating system (OS) to a state of an execution in a main storage memory (RAM), and thereafter restores processes in the OS to a state of an execution. Further, the OS sequentially transfers images of the processes to the RAM from a non-volatile storage apparatus, and resumes execution of the processes from a process for which transfer is complete.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: February 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keigo Goda
  • Patent number: 8949297
    Abstract: Embodiments of a system and method manage a configuration of a plurality of content switching devices in a networked system by generating a first configuration data file and translating the first configuration data file into one or more device specific configuration data files, each device specific configuration file corresponding to a device type of the one or more content switching devices. Some embodiments of the system and method then communicate the one or more device specific configuration data files to each content switching device of a corresponding device type to configure each content switching device.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: February 3, 2015
    Assignee: eBay Inc.
    Inventors: Armond Bigian, John T. Feldmeier, Connie Y. Yang
  • Publication number: 20150033242
    Abstract: A method for automatic task-level parallelization of execution of a computer program with automatic concurrency control. According to this invention, shared data in memory must be queried. Such memory queries represent side-effects of their enclosing tasks and allow determining how tasks must be executed with regard to each other based on intersections of their queried data. Tasks that have intentions to modify the same data (their side-effects intersect) must be executed sequentially; otherwise, tasks can be executed in parallel.
    Type: Application
    Filed: July 29, 2013
    Publication date: January 29, 2015
    Inventor: Andriy Michailovich Stepanchuk
  • Patent number: 8943511
    Abstract: A parallel allocation calculating unit calculates a parallel allocation candidate which is an element candidate in target data allocated per processing performed in parallel. A parallel calculation amount estimation processing unit estimates the calculation amount required for parallel processing when a parallel allocation candidate is allocated, based on a nonzero element count in the target data. An optimality decision processing unit decides whether or not the parallel allocation candidate is optimal based on the calculated calculation amount, and allocates the optimal element per processing performed in parallel.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: January 27, 2015
    Assignee: NEC Corporation
    Inventors: Ryohei Fujimaki, Kouhei Hayashi
  • Patent number: 8943461
    Abstract: A method, apparatus and computer program product is provided to create an integration process between a source system and target system. The method includes creating a mapping between one or more source objects and one or more target objects and generating a complete workflow as part of an integration process between a respective source system and target system. A limited subset of operations is selectively included from a sequence of activities in the complete workflow that interact with the one or more source objects and one or more target objects. The limited subset of operations selected from the complete workflow is sequenced in a stepwise template that streamlines the integration process between the source system and target system, by focusing on mappings between and operations performed upon source objects and target objects associated with the limited subset of operations selected from the operations in the complete workflow.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Vasile Patrascu, Rishi Vaish