Abstract: Multi-threaded processing with reduced context switching is disclosed. Context switches may be avoided through the use of pre-emption notification, a pre-emption wait time attribute and a no-context-save yield.

Abstract: A method and apparatus is disclosed for preventing loops on a network topology which includes virtual switches and virtual machines. For example, a virtualization management application may prevent loops from being introduced into a network topology where a virtual machine forwards traffic between any two (or more) virtual network interface cards (vNICs). A method to prevent loops may include receiving a request to create a virtual network interface (vNIC) for a virtual machine (VM) instance on a computing system, and in response to determining that the requested vNIC is to be connected to the same network segment as an existing vNIC of the VM instance, failing the request to generate the requested vNIC.

Abstract: When executing plural application programs in parallel, a control unit assigns a small storage area to each application program so that a part of a function implemented by execution of each application program is provided. When providing a service of high value to a user, a control unit assigns a large storage area to any one of the application programs so that a full function that is implemented by execution of the application program is provided.

Abstract: Guiding OS thread scheduling in multi-core and/or multi-threaded microprocessors by: determining, for each thread among the active threads, the power consumed by each instruction type associated with an instruction executed by the thread during the last context switch interval; determining for each thread among the active threads, the power consumption expected for each instruction type associated with an instruction scheduled by said thread during the next context switch interval; generating at least one combination of N threads among the active threads (M), and for each generated combination determining if the combination of N threads satisfies a main condition related to the power consumption per instruction type expected for each thread of the thread combination during the next context switch interval and to the thread power consumption per instruction type determined for each thread of the thread combination during the last context switch interval; and selecting a combination of N threads.

Abstract: A mobile terminal and controlling method thereof are disclosed, by which a scheduling function of giving a processing order to each of a plurality of tasks is supported. The present invention includes a memory including an operating system having a scheduler configured to perform a second scheduling function on a plurality of tasks, each having a processing order first-scheduled in accordance with a first reference and a processor performing an operation related to the operating system, the processor processing a plurality of the tasks. Moreover, if a first task among a plurality of the first-scheduled tasks meets a second reference, the scheduler performs the second scheduling function by changing the processing orders to enable the first task to be preferentially processed.

Abstract: According to one embodiment, an information processing device includes an OS and a virtual machine switching section. The OS accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory. The virtual machine switching section switches a virtual machine in exection from a first virtual machine to a second virtual machine while a cache process is executed, when cache miss in a process executed by the first virtual machine is detected.

Abstract: A wake-and-go mechanism is provided for a data processing system. When a thread first starts executing, a wake-and-go mechanism automatically allocates space for thread state in a hardware private array and space for a target address and other information, if any, in a wake-and-go array. If the hardware private array comprises a reserved portion of system memory, then the wake-and-go mechanism may request a sufficient portion of memory to store thread state for the thread. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. When a thread ends execution and is no longer in the run queue of the processor, the wake-and-go mechanism de-allocates the space for the thread state information for that thread.

Abstract: A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The wake-and-go mechanism may save the state of the thread in a hardware private array. The hardware private array may comprise a plurality of memory cells embodied within the processor or pervasive logic associated with the bus, for example. Alternatively, the hardware private array may be embodied within logic associated with the wake-and-go storage array.

Abstract: A method, medium and apparatus for storing and restoring a register context for a fast context switching between tasks is disclosed. The method, medium and apparatus may improve overall operating speed of a system by increasing the speed of context switching. The method may include adding an update code for updating information of live registers to a task file that includes a code of a task to perform a specified function, converting the task file having the update code added thereto into a run file, updating the information of the live registers with the update code during running of the task using the run file, and storing a live register context according to the updated information of the registers.

Abstract: In one embodiment, an apparatus for managing hypercalls in a hypervisor having an interrupt handler and a schedule is described. A deferrable low-overhead hypercall (DLH) module is configured to assign a separate DLH queue to each of a plurality of virtual machines when the virtual machine is initialized. Each entry in the separate DLH queue represents a hypercall routine. When one of the virtual machines notifies the interrupt handler of at least a deferrable hypercalls to be executed, the scheduler selects at least a virtual CPU (VCPU) and assigns them to the virtual machine to run on at least a physical CPU (PCPU). The DLH module executes the at least a deferrable hypercall inserted in a DLH queue assigned to the virtual machine before restoring the VCPU context to the virtual machine having the at least an assigned VCPU.

Abstract: A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

Abstract: An integrated circuit device comprising an instruction processing module for performing operations on data in accordance with received instructions. The instruction processing module comprises a context selector unit arranged to selectively provide access to at least one process attribute(s) within a plurality of process contexts in accordance with at least one context selector value received thereby. The instruction processing module is arranged to receive an instruction comprising a context indication for a process attribute with which an operation is to be performed, provide the context selector value based at least partly on the context indication to the context selector unit, and execute the operation to be performed with the process attribute for at least one process context to which the context selector unit provides access in accordance with the context selector value.

Abstract: Extended features such as registers and functions within processors are made available to operating systems (OS) using an extended-state driver and by modifying instruction set extensions, such as XSAVE. A map-table designates a correspondence between memory locations for storing data relating to extended features not supported by the OS and called by an application. As a result, applications may utilize processor resources which are unsupported by the OS.

Abstract: A sandbox tool can cooperate with components of a secure operating system to create an isolated execution environment for accessing untrusted content without exposing other processes and resources of the computing system to the untrusted content. The sandbox tool can allocate resources (storage space, memory, etc) of the computing system, which are necessary to access the untrusted content, to the isolated execution environment, and apply security polices of the operating system to the isolated execution environment such that untrusted content running in the isolated execution environment can only access the resources allocated to the isolated execution environment.

Abstract: An apparatus and method provide for profile optimizations at a binary level. Thread specific data may be used to lay out a procedure in a binary. In one example, a hot thread may be identified and a layout may be generated based on the identified hot thread. Also, threads of an application may be ranked according to frequency of execution of the corresponding threads. The layout may be created based on the different threads of differing frequency of execution and conflicts between a hottest thread and each of the other threads of the application. In another example, different threads of the application may conflict. For example, two threads may contain operations that overlap temporally to create a race condition. A layout of the application threads may be created based on conflicting threads.

Abstract: Mechanisms are provided for dynamically determining one or more automation levels for tasks of a workflow. The mechanisms receive a workflow from a source component and receiving context and state information for an environment in which the workflow is to be performed. One or more tasks and associated task attributes are identified in the workflow and applying one or more automation rules to the context and state information and the task attributes to generate one or more automation level settings from the one or more tasks. The one or more tasks are performed in the environment in accordance with the one or more automation level settings. The automation level settings specify a degree of automation to be used when performing the one or more tasks.

Abstract: A technique for managing read-copy update readers that have been preempted while executing in a read-copy update read-side critical section. A single blocked-tasks list is used to track preempted reader tasks that are blocking an asynchronous grace period, preempted reader tasks that are blocking an expedited grace period, and preempted reader tasks that require priority boosting. In example embodiments, a first pointer may be used to segregate the blocked-tasks list into preempted reader tasks that are and are not blocking a current asynchronous grace period. A second pointer may be used to segregate the blocked-tasks list into preempted reader tasks that are and are not blocking an expedited grace period. A third pointer may be used to segregate the blocked-tasks list into preempted reader tasks that do and do not require priority boosting.

Abstract: A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.

Abstract: A method of enabling multiple different operating systems to run concurrently on the same RISC computer, comprising selecting a first operating system to have a relatively high priority (the realtime operating system, such as C5); selecting at least one secondary operating system to have a relatively lower priority (the general purpose operating system, such as Linux); providing a common program (a hardware resource dispatcher similar to a nanokernel) arranged to switch between said operating systems under predetermined conditions; and providing modifications to said first and second operating systems to allow them to be controlled by said common program.

Abstract: A method, for monitoring resources of a system for performing a first task and a second task, includes calculating a first completion count of the first task; calculating a second completion count of the second task; and determining whether the resources of the system are exhausted according to the first completion count and the second completion count.

Abstract: Provided are a method, system, and program for executing multiple threads in a processor. Credits are set for a plurality of threads executed by the processor. The processor alternates among executing the threads having available credit. The processor decrements the credit for one of the threads in response to executing the thread and initiates an operation to reassign credits to the threads in response to depleting all the thread credits.

Abstract: Method, system, and computer program product embodiments for synchronizing workitems on one or more processors are disclosed. The embodiments include executing a barrier skip instruction by a first workitem from the group, and responsive to the executed barrier skip instruction, reconfiguring a barrier to synchronize other workitems from the group in a plurality of points in a sequence without requiring the first workitem to reach the barrier in any of the plurality of points.

Abstract: Two or more processors that each provides a specified thread to access a shared resource that can only be accessed by one thread at a given time. A locking mechanism enables one of the threads to access the shared resource while other threads are retained in a waiting queue. Responsive to an additional thread that is not one of the specified threads being provided access the shared resource during an identified time period, and responsive to a first criterion an a second criterion being met, the additional thread accesses the shared resource before the other threads in the waiting queue.

Abstract: A network device establishes a logical channel with each server device of multiple server devices, where each logical channel is not shared with another server device of the multiple server devices. The network device also determines a network loopback Internet protocol (IP) address for each server device of the multiple server devices, and associates each network loopback IP address with a corresponding logical channel. The network device further receives a packet destined for a particular server device, and provides the packet to the particular server device via the logical channel associated with the particular server device.

Abstract: Ensuring real-time performance of multitask control and improving the processing efficiency of a system provided with a processor processing while switching between a plurality of tasks. The system includes an execution unit executing instructions on individual tasks while switching from one task to another, a distinguishing unit executing an instruction determined to be a predetermined instruction. The system further includes a determination unit set so that on condition that the instruction to be executed is the predetermined instruction, it determines whether to allow the execution unit to execute the predetermined instruction or to perform a task switching process without executing the predetermined instruction based on a predetermined condition.

Abstract: A device stores a plurality of applications and a list of associations for those applications. The applications are preferably stored within a secondary memory of the device, and once launched each application is loaded into RAM. Each application is preferably associated to one or more of the other applications. Preferably, no applications are launched when the device is powered on. A user selects an application, which is then launched by the device, thereby loading the application from the secondary memory to RAM. Whenever an application is determined to be associated with a currently active state application, and that associated application has yet to be loaded from secondary memory to RAM, the associated application is pre-launched such that the associated application is loaded into RAM, but is set to an inactive state.

Abstract: Task scheduling in a processing system having a main memory and a processor having a plurality of software-configurable registers is disclosed. The processor may be a synergistic processing unit (SPU) of a cell processor. The processing system operates under the control of a kernel and a program code. A subset of the plurality of software-configurable registers is reserved for use by the kernel. Upon occurrence of an interrupt event requiring control of the processor by the kernel, the kernel may be run on the processor without saving the contents the plurality of registers.

Abstract: Various technologies and techniques are disclosed for switching threads within routines. A controller routine receives a request from an originating routine to execute a coroutine, and executes the coroutine on an initial thread. The controller routine receives a response back from the coroutine when the coroutine exits based upon a return statement. Upon return, the coroutine indicates a subsequent thread that the coroutine should be executed on when the coroutine is executed a subsequent time. The controller routine executes the coroutine the subsequent time on the subsequent thread. The coroutine picks up execution at a line of code following the return statement. Multiple return statements can be included in the coroutine, and the threads can be switched multiple times using this same approach. Graphical user interface logic and worker thread logic can be co-mingled into a single routine.

Abstract: Multi-threaded processing with reduced context switching is disclosed. Context switches may be avoided through the use of pre-emption notification, a pre-emption wait time attribute and a no-context-save yield.

Abstract: A method and apparatus are provided for efficiently transferring data between a first and second processors having shared memory. A plurality of data packets are aggregated into a packet bundle at the first processor. The packet bundle is then transferred from the first processor to the second processor using the shared memory, wherein the transfer of the packet bundle is performed in a single context switch at the first processor. The packet bundle is then unbundled into individual data packets at the second processor, wherein a processing load of the second processor is reduced due to the aggregation of the data packets into the packet bundle by the first processor.

Abstract: A system and method deterministically switches context in a real-time scheduler to guarantee schedule periodicity. The method includes determining a time slice for each of the plurality of processes. The method includes determining a time slice switch duration between consecutive ones of the time slices. The method includes determining a starting point for each time slice. The method includes generating a schedule as a function of the time slices, the time slice switch durations, and the starting points of the time slices. The schedule includes an order for each of the time slices for a respective one of the plurality of processes. Each of the time slices and each of the time slice switch durations are required to run for their entire duration to guarantee a periodicity of the schedule.

Abstract: The present invention relates generally to computer operating systems, and more specifically, to operating system calls in a symmetric multiprocessing (SMP) environment. Existing SMP strategies either use a single lock or multiple locks to limit access to critical areas of the operating system to one thread at a time. These strategies suffer from a number of performance problems including slow execution, large software and execution overheads and deadlocking problems. The invention applies a single lock strategy to a micro kernel operating system design which delegates functionality to external processes. The micro kernel has a single critical area, the micro kernel itself, which executes very quickly, while the external processes are protected by proper thread management. As a result, a single lock may be used, overcoming the performance problems of the existing strategies.

Abstract: The problem which is being addressed by this invention is the lack of determinism in mass market operating systems. This invention provides a mechanism for mass market operating systems running on mass market hardware to be extended to create a true deterministic responsive environment. This is accomplished through programming hardware elements of the scheduler to behave deterministically with respect to the software scheduler.

Abstract: A scheduler in a process of a computer system includes a local collection of tasks for each processing resource allocated to the scheduler and at least one general collection of tasks. The scheduler assigns each task that becomes unblocked to the local collection corresponding to the processing resource that caused the task to become unblocked. When a processing resource becomes available, the processing resource attempts to execute the most recently added task in the corresponding local collection. If there are no tasks in the corresponding local collection, the available processing resource attempts to execute a task from the general collection.

Abstract: A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes a hardware concurrency engine coupled to the plurality of processors. The concurrency engine is capable of managing a plurality of concurrency primitives that coordinate execution of the threads by the processors. The concurrency primitives could represent objects, and the processors may be capable of using the objects by reading from and/or writing to addresses in an address space associated with the concurrency engine. Each address may encode an object index identifying one of the objects, an object type identifying a type associated with the identified object, and an operation type identifying a requested operation involving the identified object.

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Abstract: Methods and apparatus, including computer program products, for compiling workflows into instructions for a state correlation engine. In general, data characterizing a workflow of a process is received and a network representation of event-condition-action rules representing the workflow is generated. The workflow of the process may be modeled in accordance with a notation similar to the Business Process Modeling Notation. The network representation of event-condition-action rules may include a combination of source nodes representing events, operator nodes representing conditions, and action nodes representing transactions. Events of the source nodes may be represented types of objects of a type language, where a correlation engine is to execute an event-condition-action rule based on an existence of a combination of types of a rule.

Abstract: The information processing device in the simultaneous multi-threading system is operated in an inter-thread performance load arbitration control method, and includes: an instruction input control unit for sharing among threads control of inputting an instruction in an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit.

Abstract: Two threads may communicate via shared memory using two different modes. In a polling mode, a receiving thread may poll an indicator set by the sending thread to determine if a message is present. In a blocking mode, the receiving thread may wait until a synchronization object is set by the sending thread which may cause the receiving thread to return to the polling mode. The polling mode may have low latency buy may use processor activity of the receiving thread to repetitively check the indictor. The blocking mode may have a higher latency but may allow the receiving thread to enter a sleep mode or perform other activities.

Abstract: A computer-implemented method for managing processing resources of a computerized system having at least a first processor and a second processor, each of the processors operatively interconnected to a memory storing a set of data to be processed by a processor, the method comprising: monitoring data accessed by the first processor while executing; and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.

Abstract: A system is set forth that includes a processor, one or more memory storage units, and software code stored in the one or more memory storage units. The software code is executable by the processor to generate a plurality of adaptive partitions that are each associated with one or more process threads. Each of the plurality of adaptive partitions has a corresponding processor budget that is assigned to it. The process threads include a mutex holding thread and a mutex waiting thread. The mutex holding thread is associated with a first adaptive partition and may gain exclusive access to a mutex object. The mutex waiting thread is associated with a second adaptive partition and must wait for access to the mutex object while the mutex object is held by the mutex holding thread. The software code further includes a scheduling system that selectively allocates the processor to run the process threads based, at least in part, on the processor budget of the associated adaptive partitions.

Abstract: Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.

Abstract: Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

Abstract: A print relay system capable of connecting to an image forming apparatus and a print service system, which is provided by a vendor that publishes a unique specification for executing data communication with the image forming apparatus includes an acquisition unit configured to, in response to the print service system receiving a printing instruction input by a user via a client, acquire data from the print service system according to a first specification, which is the unique specification for data communication between the print service system and a relay virtual printer, and a transmission unit configured to transmit the data acquired by the acquisition unit from the relay virtual printer to the image forming apparatus according to a second specification for executing data communication between the relay virtual printer and the image forming apparatus.

Abstract: Methods, systems, apparatuses and program products for providing for communications within a computing environment that provides for execution isolation, especially a DXE (Driver Execution Environment) phase of a PC (personal computer) startup process. Provision is made for blocking of server threads awaiting service requests and blocking client thread awaiting server responses, together with marshalling formal parameter descriptions and service request/response arguments across disparate execution contexts that disallow simple data redirection between them.

Abstract: A method and system for using bundle decoders in a processing pipeline is disclosed. In one embodiment, to perform a context switch between a first process and a second process operating in a processing pipeline, the first state information that is associated with the first process is placed on a connection separate from the processing pipeline. A number of decoders are coupled to this connection. The decoders obtain the first state information from a number of pipeline units on the processing pipeline by monitoring the data stream going into these pipeline units. Also, to restore the first state information after having switched out the second state information that is associated with the second process, the first state information is placed on the connection for the decoders to retrieve.

Abstract: Execution context isolation during the DXE phase of computer start-up. Provision is made for referencing and dereferencing execution contexts and thereby providing execution isolation across contexts. In response to invoking a BIOS kernel function during a Driver Execution Environment (DXE) phase of a boot-up of the computer, the BIOS kernel associates a first processor context with the sequence of instructions, determines that scheduling the sequence of instructions requires a switch from a second processor context to the first processor context, performs a context switch action, during the DXE phase of the boot-up of the computer, to switch from the second processor context to the first processor context.

Abstract: The invention in particular has as an object supervising a scheduler for the management of processing time sharing in a multitask data-processing system comprising a computation unit having a standard execution mode and a preferred execution mode for executing a plurality of applications. The execution time for the said plurality of applications is divided into a plurality of periods and a minimal time for access per period to the said computation unit is determined for at least one application of the said plurality of applications. For at least one period, the said preferred execution mode is associated with the said at least one application and the said at least one application is executed according to at least the said minimal time for access to the said computation unit. For the said at least one period, the said standard execution mode is associated with the applications of the said plurality of applications and at least any one of the applications of the said plurality of applications is executed.

Abstract: Methods and systems for direct device access are disclosed. Aspects of one method may include a plurality of GOSs directly accessing a first network interface device, where the first network interface device may provide access to a network. One or more of the GOSs may be migrated to directly access a second network interface device, based on state information for each of the GOSs, where the state information may be maintained by the host. The GOSs may communicate data to a device coupled to the network by direct accessing the first and/or second network interface device. Similarly, the first and/or second network interface device may communicate data received from a device coupled to the network to one or more of the plurality of GOSs via direct access of the first and/or second network interface device.

Abstract: A method for tagging cache entries to support context switching for virtual machines and for operating systems. The method includes, storing a plurality of entries within a cache of a CPU of a computer system, wherein each of the entries includes a context ID, handling a first portion of the entries as local entries when the respective context IDs indicate a local status, and handling a second portion of the entries as global entries when the respective context IDs indicate a global status.