Abstract: The present invention relates to a coating composition, especially, relates to an aqueous coating composition with improved liquid stain repellency, it has a fraction of critical pigment volume concentration of from 35% to 110%, and comprises (i) pigment composition, including 15 wt. %-100 wt. %, in percentage by weight based on the dry weight of the pigment composition, polymer-encapsulated pigment; and 0-85 wt. %, in percentage by weight based on the dry weight of the pigment composition, un-encapsulated pigment; and (ii) 0.01 wt. %-5 wt. %, in percentage by dry weight based on the wet weight of the aqueous coating composition, at least one paraffin wax emulsion.

Abstract: Embodiments of the present disclosure provide for nanoparticles, methods of making nanoparticles, materials including nanoparticles, the use of materials including nanoparticles, and the like.

Abstract: A thermal and electrical conducting apparatus includes a few-layer graphene film having a thickness D where D?1.5 nm and a plurality of carbon nanotubes crystallographically aligned with the few-layer graphene film.

Abstract: A porous carbonaceous composite material including a core including a carbon nanotube (CNT); and a coating layer on the core, the coating layer including a carbonaceous material including a hetero element.

Abstract: A conventional polymer is grafted from a plasma polymer layer provided at a substrate surface by radical polymerisation initiated from plasma induced radicals present at or in the plasma polymer, particularly radicals provided during deposition of the plasma polymer.

Abstract: A method for depositing graphene is provided. The method includes depositing a layer of non-conducting amorphous carbon over a surface of a substrate and depositing a transition metal in a pattern over the amorphous carbon. The substrate is annealed at a temperature below 500° C., where the annealing converts the non-conducting amorphous carbon disposed under the transition metal to conducting amorphous carbon. A portion of the pattern of the transition metal is removed from the surface of the substrate to expose the conducting amorphous carbon.

Abstract: An anode active material, an anode including the anode active material, a lithium battery including the anode, and a method of preparing the anode active material. The anode active material includes: a multilayer metal nanotube including: an inner layer; and an outer layer on the inner layer, wherein the inner layer includes a first metal having an atomic number equal to 13 or higher, and the outer layer includes a second metal different from the first metal.

Abstract: A method of forming a non-volatile memory device includes providing a substrate having a surface, depositing a dielectric overlying the surface, forming a first wiring structure overlying the dielectric, depositing silicon material overlying the first wiring structure, the silicon layer having a thickness of less than about 100 Angstroms, depositing silicon germanium material at a temperature raging from about 400 to about 490 Degrees Celsius overlying the first wiring structure using the silicon layer as a seed layer, wherein the silicon germanium material is substantially free of voids and has polycrystalline characteristics, depositing resistive switching material (e.g. amorphous silicon material) overlying the silicon germanium material, depositing a conductive material overlying the resistive material, and forming a second wiring structure overlying the conductive material.

Abstract: A non-volatile memory structure includes a substrate; a poly gate structure formed on the substrate; a contact etching stop layer formed over the poly gate structure and including at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and an inter-layer dielectric layer formed on the first silicon oxide layer. The first silicon oxide layer has a density higher than that of the inter-layer dielectric layer.

Abstract: A method for forming a semiconductor device such as a MOSFET. The method includes forming gate electrode pillars on a silicon substrate via material deposition and etching. Following the etching step to define the pillars, an epitaxial silicon film is grown on the substrate between the pillars prior to forming recesses in the substrate for the source/drain regions of the transistor. The epitaxial silicon film compensates for substrate material that may be lost during formation of the gate electrode pillars, thereby producing source/drain recesses having a configuration amenable to be filled uniformly with silicon for later forming the source/drain regions in the substrate.

Abstract: A fabrication process for conformal coating of a thin polymer electrolyte layer on nanostructured electrode materials for three-dimensional micro/nanobattery applications, compositions thereof, and devices incorporating such compositions. In embodiments, conformal coatings (such as uniform thickness of around 20-30 nanometer) of polymer Polymethylmethacralate (PMMA) electrolyte layers around individual Ni—Sn nanowires were used as anodes for Li ion battery. This configuration showed high discharge capacity and excellent capacity retention even at high rates over extended cycling, allowing for scalable increase in areal capacity with electrode thickness. Such conformal nanoscale anode-electrolyte architectures were shown to be efficient Li-ion battery system.

Abstract: A water treatment device includes an inner canister or cylinder that includes a seal and a filter assembly attached on one end. The water treatment device also includes an outer canister which is filled with unpurified water. The inner canister or cylinder is pressed into the outer canister to produce pressure on unpurified water that forces the unpurified water through the filter assembly. The inner canister or cylinder can be opened to reveal drinkable, or substantially purified water.

Abstract: A processing technology is for the fabrication at low temperatures of ferroelectric crystalline oxide thin films, among others PbZrxTi1-xO3 (PZT) (<400° C. for PZT) with ferroelectric properties appropriate for integration in devices. The method is also for the fabrication of ferroelectric thin films of bronze tungsten (A2B2O6), perovskite (ABO3), pyrochlore (A2B2O7) and bismuth-layer (Bi4Ti3O12) structures, in which A and B are mono, bi-, tri-, tetra- and pentavalent ions.

Abstract: A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.

Abstract: An ultra-violet light-emitting diode (LED) array, 12, and method for fabricating same with an AlInGaN multiple-quantum-well active region, 500, exhibiting stable cw-powers. The LED includes a template, 10, with an ultraviolet light-emitting array structure on it. The template includes a first buffer layer, 321, then a second buffer layer, 421, on the first preferably with a strain-relieving layer in both buffer layers. Next there is a semiconductor layer having a first type of conductivity, 500, followed by a layer providing a quantum-well region, 600, with an emission spectrum ranging from 190 nm to 369 nm. Another semiconductor layer having a second type of conductivity is applied next, 800. A first metal contact, 980, is a charge spreading layer in electrical contact with the first layer and between the array of LED's. A second contact, 990, is applied to the semiconductor layer having the second type of conductivity, to complete the LED.

Abstract: According to one embodiment, a magnetoresistive element includes first and second magnetic layers and a first nonmagnetic layer. The first magnetic layer has an axis of easy magnetization perpendicular to a film plane, and a variable magnetization. The second magnetic layer has an axis of easy magnetization perpendicular to a film plane, and an invariable magnetization. The first nonmagnetic layer is provided between the first and second magnetic layers. The second magnetic layer includes third and fourth magnetic layers, and a second nonmagnetic layer formed between the third and fourth magnetic layers. The third magnetic layer is in contact with the first nonmagnetic layer and includes Co and at least one of Zr, Nb, Mo, Hf, Ta, and W.

Abstract: The present invention relates to a method for producing an optical member base material for EUVL, comprising performing the following in this order to obtain an optical member base material for EUVL: a preliminary-polishing step of preliminarily polishing a film forming surface and a back surface of the film forming surface of a glass substrate; a measuring step of measuring a total thickness distribution and a flatness of the glass substrate; and a corrective-polishing step of locally polishing only the back surface of the glass substrate depending on the measurement result of the measuring step.

Abstract: Disclosed herein are nanofilm coatings for implantable medical devices comprising a diblock or triblock copolymer (PEO-PMMA or PMOXA-PDMS-PMOXA, respectively). Such nanofilms, may be used, for example, as amphiphilic supports for therapeutic agents. These materials are conducive towards the formation of active substrates for a suite of biological and medical applications.

Abstract: A coated substrate includes a substrate and a coating containing a water insoluble polymer and a water soluble polymer, the two polymers, due to different water affinity, forming a nanosegregant on the substrate. Also disclosed are a method of preparing the above-described coated substrate and the use of this coated substrate in a solid-state supercapacitor.

Abstract: To provide a novel material exhibiting excellent light-emitting characteristics using a heavy metal element having relatively abundant reserve.

Abstract: A crystalline perovskite crystalline composite paraelectric material includes nano-regions containing rich N3? anions dispersed in a nano-grain sized matrix of crystalline oxide perovskite material, wherein (ABO3-?)?-(ABO3-?-?N?)1-?. A represents a divalent element, B represents a tetravalent element, ? satisfies 0.005???1.0, 1-? satisfies 0.05?1-??0.9, and 1-? is an area ratio between the regions containing rich N3? anions and the matrix of remaining oxide perovskite material.

Abstract: The present invention relates to a heterophasic polypropylene composition with rather high melt flow rate, high stiffness, acceptable impact properties and an advantageous balance between stiffness and transparency. Still further, the present invention is also directed to a process for producing the inventive polypropylene composition, to an article made of the inventive polypropylene composition and to the use of the inventive polypropylene composition for the production of films and moulded articles, such as thin-walled plastic containers for packaging. The inventive heterophasic polypropylene composition comprises at least a propylene homopolymer fraction, a propylene random copolymer fraction, two different ethylene-propylene rubber fractions and an ethylene homo- or copolymer fraction.

Abstract: A thermal and electrical conducting apparatus includes a few-layer graphene film having a thickness D where D?1.5 nm and a plurality of carbon nanotubes crystallographically aligned with the few-layer graphene film.

Abstract: The present disclosure relates to a lithium ion battery. The lithium ion battery cathode includes a cathode, a separator, an anode, and a nonaqueous electrolyte solution. The cathode includes a cathode current collector and a cathode material layer disposed on a surface of the cathode current collector. The cathode material layer comprises cathode active material, conductive agent, and adhesive uniformly mixed together. The cathode active material comprises cathode active material particles and AlPO4 layers coated on surfaces of the cathode active material particles. The separator includes a porous membrane and a protective layer coated on a surface of the porous membrane. The protective layer prevents the separator from being melted during charging or discharging of the lithium ion battery.

Abstract: An acousto-optic device includes an acousto-optic medium having a multi-layer nanostructure; and a sonic wave generator configured to apply sonic waves to the acousto-optic medium having the multi-layer nanostructure. The acousto-optic medium having the multi-layer nanostructure includes a second layer formed of at least two materials that have different dielectric constants and alternate with each other; and a first layer disposed on a first surface of the second layer and formed of a first material, and/or a third layer disposed on a second surface of the second layer and formed of a fourth material.

Abstract: A method for making a flexible OLED lighting device includes forming a plurality of OLED elements on a flexible planar substrate, wherein at least one of the OLED elements includes a continuous respective anode layer formed over the substrate, one or more organic light emitting materials formed over the anode layer, a cathode layer formed over the light emitting materials, and an encapsulating protective cover formed over the cathode layer. At least one of the OLED elements defines a continuous light region on the substrate, wherein the substrate and combination of OLED elements define an active light area. The active light area is bendable from a flat planar configuration to a bend configuration having a design bending radius. The thickness of the cathode layer is formed between a minimum thickness value and a maximum thickness value as a function of the size of the active light area and the design bending radius. An OLED in accordance with these aspects is also provided.

Abstract: A semiconductor device with reduced defect density is fabricated by forming localized metal silicides instead of full area silicidation. Embodiments include forming a transistor having a gate electrode and source/drain regions on a substrate, forming a masking layer with openings exposing portions of both the gate electrode and source/drain regions over the substrate, depositing metal in the openings on the exposed portions, forming silicides in the openings, and removing unreacted metal and the masking layer.

Abstract: A 3-terminal electronic device includes: a control electrode; a first electrode and a second electrode; and an active layer that is provided between the first electrode and the second electrode and is provided to be opposed to the control electrode via an insulating layer. The active layer includes a collection of nanosheets. When it is assumed that the nanosheets have an average size LS and the first electrode and the second electrode have an interval D therebetween, LS/D?10 is satisfied.

Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.

Abstract: A lithium-ion secondary battery includes a positive electrode, a negative electrode containing an active material, and an electrolytic solution, in which the active material includes a core portion capable of occluding and releasing lithium ions, and a covering portion arranged on at least part of a surface of the core portion, in which the covering portion contains, as constituent elements, Si, O, and at least one element M1 selected from Li, C, Mg, Al, Ca, Ti, Cr, Mn, Fe, Co, Ni, Cu, Ge, Zr, Mo, Ag, Sn, Ba, W, Ta, Na, and K, and the atomic ratio y (O/Si) of O to Si is 0.5?y?1.8.

Abstract: A coating film comprises a binder component containing an organosilicon compound; and aggregated particles of silica based fine particles, the aggregated particles are dispersed in the binder component. The aggregated particles are protruded from a surface of the coating film to thereby form convex portions. When a shape of each of the convex portions is assumed to be a shape of a semiellipse spherical body including a long radius “a”, a short radius “b” and a protrusion height “c”, the convex portions include enlarged convex portions each of which satisfies the following relation: ??abc?1.0×10?12. A number of the enlarged convex portions is 200 or less per 1 mm2 of the surface of the coating film.

Abstract: Compositions and methods of producing discrete nanotubes and nanoplates and a method for their production. The discrete nanotube/nanoplate compositions are useful in fabricated articles to provide superior mechanical and electrical performance. They are also useful as catalysts and catalyst supports for chemical reactions.

Abstract: A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed.

Abstract: A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands.

Abstract: A solid electrolyte includes a sulfide-based electrolyte and a coating film including a water-resistant, lithium conductive polymer on a surface of the sulfide-based electrolyte, a method of preparing the solid electrolyte, and a lithium battery including the solid electrolyte.

Abstract: An anode for an organic light emitting device which introduces a metal oxide to improve flows of charges, and an organic light emitting device using the anode. The anode for the organic light emitting device has excellent charge injection characteristics, thereby improving power consumption of the organic light emitting device.

Abstract: In one aspect, a cathode including the first metal layer, the transparent conductive layer formed on the first metal layer, and the second metal layer formed on the transparent conductive layer is applied to the organic light emitting device and thicknesses of the first metal layer, the transparent conductive layer, and the second metal layer are controlled so that the external light reflection of the organic light emitting device is prevented. The cathode may further include the third metal layer formed on the second metal layer.

Abstract: A method for fabricating a high voltage transistor includes the following steps. Firstly, a substrate is provided. A first sacrificial oxide layer and a hard mask layer are sequentially formed over the substrate. The hard mask layer is removed, thereby exposing the first sacrificial oxide layer. Then, a second sacrificial oxide layer is formed on the first sacrificial oxide layer. Afterwards, an ion-implanting process is performed to introduce a dopant into the substrate through the second sacrificial oxide layer and the first sacrificial oxide layer, thereby producing a high voltage first-type field region of the high voltage transistor.

Abstract: A nano graphene-enabled vanadium oxide composite composition for use as a lithium battery cathode active material, wherein the composite composition is formed of one or a plurality of graphene, graphene oxide, or graphene fluoride sheets or platelets and a plurality of nano-particles, nano-rods, nano-wires, nano-sheets, and/or nano-belts of a vanadium oxide with a size smaller than 100 nm (preferably smaller than 20 nm, further preferably smaller than 10 nm, and most preferably smaller than 5 nm), and wherein the graphene, graphene oxide, or graphene fluoride (having a thickness <20 nm, preferably <10 nm, further preferably <5 nm, and being most preferably of single-layer or less than 5 layers) is in an amount of from 0.01% to 50% (preferably <10%) by weight based on the total weight of graphene, graphene oxide or graphene fluoride and the vanadium oxide combined.

Abstract: A semiconductor device and manufacturing method therefor includes a ?-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a ?-shaped recess.

Abstract: A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.

Abstract: A method of growing carbon nanomaterials on a substrate wherein the substrate is exposed to an oxidizing gas; a seed material is deposited on the substrate to form a receptor for a catalyst on the surface of said substrate; a catalyst is deposited on the seed material by exposing the receptor on the surface of the substrate to a vapor of the catalyst; and substrate is subjected to chemical vapor deposition in a carbon containing gas to grow carbon nanomaterial on the substrate.

Abstract: The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate, forming sequentially a first high-k dielectric layer, an adjusting layer, a second high-k dielectric layer and a metal gate on the substrate, etching the first high-k dielectric layer, the adjusting layer, the second high-k dielectric layer and the metal gate to form a gate stack. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes to arrange an adjusting layer between two layers of high-k dielectric layer, which effectively avoids reaction of the adjusting layer with the metal gate because of their direct contact, so as to maintain the performance of semiconductor devices.

Abstract: A porous membrane material comprising a porous membrane substrate coated with a thin, uniform coating of a different material. The membrane material can have high electrical conductivity. The membrane material can exhibit a very high ratio of electrical conductivity to thermal conductivity. The porous membrane substrate may be removed to form the membrane.

Abstract: Nanoparticles with a metal or metallic core and an outer shell comprising a matrix and a dopant. For example, a nanoparticle can have a gold core and outer shell comprising silica and an organic dye. Such nanoparticles can have use in, for example, optical communication applications, chemical and biosensing applications, and imaging applications.

Abstract: A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices.

Abstract: A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.

Abstract: The present invention relates to effect pigments having a substrate which has a coating comprising a complex metal oxide containing copper, iron and manganese, and to a process for the preparation of the effect pigments, to the use of the effect pigments in paints, coatings, powder coatings, printing inks, plastics, ceramic materials, glasses, in cosmetic formulations, for laser marking and for the preparation of pigment preparations and dry preparations.

Abstract: A hot dip galvannealed steel sheet, which is a plated steel sheet, the plated sheet including an oxide layer being formed on the surface of the plated steel sheet, having an average thickness of 10 nm or more, and containing Zn and at least one element selected from the group consisting of Zr, Ti and Sn.