Nanowire Or Quantum Wire (axially Elongated Structure Having Two Dimensions Of 100 Nm Or Less) Patents (Class 977/762)
  • Patent number: 8766272
    Abstract: “An imaging device formed as an active pixel array combining a CMOS fabrication process and a nanowire fabrication process. The pixels in the array may include a single or multiple photogates surrounding the nanowire. The photogates control the potential profile in the nanowire, allowing accumulation of photo-generated charges in the nanowire and transfer of the charges for signal readout. Each pixel may include a readout circuit which may include a reset transistor, charge transfer switch transistor, source follower amplifier, and pixel select transistor. A nanowire is generally structured as a vertical rod on the bulk semiconductor substrate to receive light energy impinging onto the tip of the nanowire. The nanowire may be configured to function as either a photodetector or a waveguide configured to guild the light to the substrate. Light of different wavelengths can be detected using the imaging device.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Zena Technologies, Inc.
    Inventors: Young-June Yu, Munib Wober
  • Publication number: 20140174155
    Abstract: The present invention provides a hybrid nanomaterial electrode, comprising a pair of spaced-apart electrodes, at least three pairs of metallic nanowires disposed between the electrodes and respectively connected with the electrodes, and at least a detecting material connecting with the metallic nanowires. The detecting material is formed as a semiconductor nanostructure or a conductor nanostructure. The hybrid nanomaterial electrode of the present invention can be used in a gas detector for detecting volatile organic compounds, and has the advantage of providing high sensitivity, low detection limit, and the ability to operate at room temperature.
    Type: Application
    Filed: May 1, 2013
    Publication date: June 26, 2014
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: CHIEN-CHONG HONG, ZI-XIANG LIN, KUO-CHU HWANG
  • Publication number: 20140175374
    Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.
    Type: Application
    Filed: March 2, 2014
    Publication date: June 26, 2014
    Applicant: Intemational Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20140175375
    Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer.
    Type: Application
    Filed: March 2, 2014
    Publication date: June 26, 2014
    Applicant: Intemational Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8759810
    Abstract: A phase change memory device that utilizes a nanowire structure. Usage of the nanowire structure permits the phase change memory device to release its stress upon amorphization via the minimization of reset resistance and threshold resistance.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 24, 2014
    Assignee: The Trustees Of The University Of Pennsylvania
    Inventors: Ritesh Agarwal, Mukut Mitra, Yeonwoong Jung
  • Publication number: 20140173786
    Abstract: Nanowire apparatus and methods of using the same are disclosed. The apparatus include nanowires that are attached to and extend from varying substrates and can be used in the manipulation of cells and/or sensing of cellular and subcellular characteristics. The methods include using the apparatus to sense forces exerted by a single cell or using the apparatus to manipulate one or more cells.
    Type: Application
    Filed: February 21, 2014
    Publication date: June 19, 2014
    Applicant: Kansas State University Research Foundation
    Inventors: Bret Flanders, Govind Paneru
  • Patent number: 8754359
    Abstract: An embodiment relates to a device comprising a substrate having a front side and a back-side that is exposed to incoming radiation, a nanowire disposed on the substrate and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: June 17, 2014
    Assignee: Zena Technologies, Inc.
    Inventors: Young-June Yu, Munib Wober
  • Patent number: 8748799
    Abstract: An image sensor comprising a substrate and one or more of pixels thereon. The pixels have subpixels therein comprising nanowires sensitive to light of different color. The nanowires are functional to covert light of the colors they are sensitive to into electrical signals.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: June 10, 2014
    Assignee: Zena Technologies, Inc.
    Inventor: Munib Wober
  • Publication number: 20140154785
    Abstract: A method of fabricating polymer single nanowires, comprising the steps of: spin coating a polymethylmethacrylate resist onto a silicon wafer patterned with at least one gold electrode pair; creating a nanochannel using e-beam lithography between each pair of the at least one gold electrode pairs; placing the silicon wafer into an aniline monomer polymerization solution; reacting the polymerization solution to give a coated wafer and a polyaniline film; and cleaning the coated wafer of polymethylmethacrylate resist and polyaniline film to give at least one gold electrode pair with a connecting polymer single nanowire.
    Type: Application
    Filed: May 23, 2013
    Publication date: June 5, 2014
    Inventors: Minhee Yun, David Schwartzman, Jiyong Huang
  • Publication number: 20140151757
    Abstract: Single crystalline semiconductor fins are formed on a single crystalline buried insulator layer. After formation of a gate electrode straddling the single crystalline semiconductor fins, selective epitaxy can be performed with a semiconductor material that grows on the single crystalline buried insulator layer to form a contiguous semiconductor material portion. The thickness of the deposited semiconductor material in the contiguous semiconductor material portion can be selected such that sidewalls of the deposited semiconductor material portions do not merge, but are conductively connected to one another via horizontal portions of the deposited semiconductor material that grow directly on a horizontal surface of the single crystalline buried insulator layer. Simultaneous reduction in the contact resistance and parasitic capacitance for a fin field effect transistor can be provided through the contiguous semiconductor material portion and cylindrical contact via structures.
    Type: Application
    Filed: December 3, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Josephine B. Chang, Michael A. Guillorn, Amlan Majumdar
  • Publication number: 20140154621
    Abstract: The disclosure relates generally to toner additives, and in particular, toner additives that provide desired higher toner charge and low relative humidity (RH) sensitivity. The toner additives comprise titania nanotubes or titania nanosheets in combination with or in place of the commonly used anatase or rutile crystalline titania.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicants: NATIONAL RESEARCH COUNCIL OF CANADA, XEROX CORPORATION
    Inventors: RICHARD P. VEREGIN, Qingbin Li, Andriy Kovalenko, Sergey Gusarov
  • Publication number: 20140154454
    Abstract: The heat resistant seal member according to one aspect of the present disclosure contains, for 100 parts by weight of a ternary fluoroelastomer, 5 to 15 parts by weight of first carbon nanofibers, 10 to 15 parts by weight of second carbon nanofibers, and 0 to 20 parts by weight of carbon black. The total amount of the first carbon nanofibers and the second carbon nanofibers are 15 to 30 parts by weight, and the total amount of the first carbon nanofibers, the second nanofibers, and the carbon black is 20 to 45 parts by weight. The heat resistant seal member can achieve a compression set of not more than 40% after 70 hours and 25% compressibility in a hydrogen sulfide gas atmosphere at 200° C.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 5, 2014
    Applicants: Shinshu University, Schlumberger Technology Corporation
    Inventors: Hiroyuki Ueki, Toru Noguchi, Masaei Ito
  • Publication number: 20140154564
    Abstract: Provided are an anode active material including carbon-based particles, silicon nanowires grown on the carbon-based particles, and a carbon coating layer on surfaces of the carbon-based particles and the silicon nanowires, and a method of preparing the anode active material. Since the anode active material of the present invention is used in a lithium secondary battery, physical bonding force between the carbon-based particles and the silicon nanowires may not only be increased but conductivity may also be improved. Thus, lifetime characteristics of the battery may be improved.
    Type: Application
    Filed: January 30, 2014
    Publication date: June 5, 2014
    Applicant: LG Chem, Ltd.
    Inventors: Jung Woo Yoo, Won Jong Kwon, Eui Yong Hwang, Kil Sun Lee, Je Young Kim, Yong Ju Lee
  • Patent number: 8735797
    Abstract: An embodiment relates to a device comprising a substrate having a front side and a back-side that is exposed to incoming radiation, a nanowire disposed on the substrate and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: May 27, 2014
    Assignee: Zena Technologies, Inc.
    Inventors: Young-June Yu, Munib Wober
  • Patent number: 8736011
    Abstract: A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: May 27, 2014
    Assignee: Alphabet Energy, Inc.
    Inventors: Mingqiang Yi, Gabriel A. Matus, Matthew L. Scullin, Chii Guang Lee, Sylvain Muckenhirn
  • Publication number: 20140138610
    Abstract: A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicant: International Business Machines Corporation
    Inventors: Michael C. Gaidis, Alexander J. Gaidis
  • Publication number: 20140141555
    Abstract: A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: GLO AB
    Inventor: Truls Lowgren
  • Publication number: 20140126280
    Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Michael C. Gaidis, William Gallagher, Luc Thomas
  • Publication number: 20140126281
    Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.
    Type: Application
    Filed: November 30, 2012
    Publication date: May 8, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Michael C. Gaidis, William Gallagher, Luc Thomas
  • Patent number: 8716695
    Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Conal E. Murray
  • Patent number: 8716072
    Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Josephine B. Chang, Leland Chang, Jeffrey W. Sleight
  • Patent number: 8715536
    Abstract: An electrically conductive material includes a plurality of nanowires and a plurality of nanoconnectors. The ratio by weight of the plurality of nanowires to the plurality of nanoconnectors is in a range of from 1:9 to 9:1. Nanoconnectors can be heated by thermal energy or light energy so that the nanoconnectors can be closely interconnected to each other and to nanowires, resulting in significant increase of the electrical conductivity of the electrically conductive material.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: May 6, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yu Ming Wang, Yion Ni Liu, Yeu Kuen Wei, Chen Chih Yeh, Ming Jyh Chang
  • Publication number: 20140119111
    Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; a first electrode and a second electrode provided to different locations of the magnetic nanowire; a third electrode including a magnetic layer, the third electrode being provided to a location of the magnetic nanowire between the first electrode and the second electrode; an intermediate layer provided between the magnetic nanowire and the third electrode, the intermediate layer being in contact with the magnetic nanowire and the third electrode; a fourth electrode of a nonmagnetic material provided onto the magnetic nanowire and being on the opposite side of the magnetic wire from the third electrode; and an insulating layer provided between the magnetic nanowire and the fourth electrode, the insulating layer being in contact with the magnetic nanowire and the fourth electrode.
    Type: Application
    Filed: October 2, 2013
    Publication date: May 1, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shiho Nakamura, Tsuyoshi Kondo, Hirofumi Morise, Takuya Shimada
  • Publication number: 20140117308
    Abstract: The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.
    Type: Application
    Filed: October 28, 2013
    Publication date: May 1, 2014
    Inventors: Berangere Hyot, Benoit Amstatt, Marie-Francoise Armand
  • Patent number: 8710488
    Abstract: A first exemplary device has a substrate, a nanowire and a doped epitaxial layer surrounding the nanowire. The nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength. The first exemplary device may further have an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. A second exemplary device has a substrate, a nanowire and one or more photogates surrounding the nanowire. The nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength. The second exemplary device may have an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. The one or more photogates comprise an epitaxial layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: April 29, 2014
    Assignee: Zena Technologies, Inc.
    Inventors: Young-June Yu, Munib Wober
  • Publication number: 20140110763
    Abstract: A nano resonance apparatus includes a gate electrode configured to generate a magnetic field, and a nanowire connecting a source electrode to a drain electrode and configured to vibrate in the presence of the magnetic field. The nanowire includes a protruding portion extending in a direction of the gate electrode.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 24, 2014
    Applicants: Korea University Industrial & Academic Collaboration Foundation, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In Sang Song, Ho Soo Park, Duck Hwan Kim, Sang Uk Son, Jae Shik Shin, Jae-Sung Rieh, Byeong Kwon Ju, Dong Hoon Hwang
  • Patent number: 8703988
    Abstract: Nanostructures are formed from alkylated derivatives of aromatic acids of the formula: wherein at least one of R1 to R6 represents a carboxylic acid group, a primary amide group, an ester group, an amidine group, or a salt thereof, at least one other of R1 to R6 is X—Rc, and the remaining of R1 to R6 independently represent H or substituted or unsubstituted organic groups; X represents a linking group; and Rc represents a substituted or unsubstituted alkyl group.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: April 22, 2014
    Assignees: Xerox Corporation, National Research Council of Canada
    Inventors: Darren Andrew Makeiff, Rina Carlini
  • Patent number: 8703271
    Abstract: A thermal interface material (1) comprises a bulk polymer (2) within which is embedded sub-micron (c. 200 to 220 nm) composite material wires (3) having Ag and carbon nanotubes (“CNTs”) 4. The CNTs are embedded in the axial direction and have diameters in the range of 9.5 to 10 nm and have a length of about 0.7 ?m. In general the pore diameter can be in the range of 40 to 1200 nm. The material (1) has particularly good thermal conductivity because the wires (3) give excellent directionality to the nanotubes (4)—providing very low resistance heat transfer paths. The TIM is best suited for use between semiconductor devices (e.g. power semiconductor chip) and any type of thermal management systems for efficient removal of heat from the device.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: April 22, 2014
    Assignee: University College Cork—National University of Ireland
    Inventors: Kafil M. Razeeb, Saibal Roy, James Francis Rohan, Lorraine Christine Nagle
  • Publication number: 20140104941
    Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; first insulating layers provided on a first surface of the magnetic nanowire, each of the first insulating layers having a first and second end faces, a thickness of the first insulating layer over the first end face being thicker than a thickness of the first insulating layer over the second end face; first electrodes on surfaces of the first insulating layers opposite to the first surface; second insulating layers on the second surface of the magnetic nanowire, each of the second insulating layers having a third and fourth end faces, a thickness of the second insulating layer over the third surface being thicker than a thickness of the second insulating layer over the fourth end face; and second electrodes on surfaces of the second insulating layers.
    Type: Application
    Filed: September 9, 2013
    Publication date: April 17, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi KONDO, Hirofumi MORISE, Shiho NAKAMURA, Takuya SHIMADA, Yoshiaki FUKUZUMI, Hideaki AOCHI
  • Publication number: 20140106134
    Abstract: The present invention relates to methods of fabricating transparent conductive films based on nanomaterials, in particular, silver nanowires. The present invention incorporates a single step of annealing and patterning the conductive films by using a high energy flash lamp without post treatment to improve the conductivity and create substantially invisible patterns on the films for use in touch panel or display manufacturing industry.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: Nano and Advanced Materials Institute Limited
    Inventors: Li FU, Caiming SUN, Man-Ho SO, Kai LI, Chau-Shek LI, Tak-Hei LAM
  • Patent number: 8696947
    Abstract: Methods of recovering compositions comprising nanowires and the product compositions are disclosed and claimed. The product compositions produced by these methods are able to provide equivalent performance to virgin raw materials in transparent conductive film manufacturing processes.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: April 15, 2014
    Assignee: Carestream Health, Inc.
    Inventors: Richard R. Ollmann, Chaofeng Zou, Gary E. Labelle, Doreen C. Lynch
  • Patent number: 8697587
    Abstract: A nonwoven web of fibers that have a number average diameter of less than 1 micron. The web can have a Poisson Ratio of less than about 0.8, a solidity of at least about 20%, a basis weight of at least about 1 gsm, and a thickness of at least 1 micrometer.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: April 15, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Pankaj Arora, Guanghui Chen, Simon Frisk, David Keith Graham, Jr., Robert Anthony Marin, Hageun Suh
  • Patent number: 8698122
    Abstract: A silicon nanowire including metal nanoclusters formed on a surface thereof at a high density. The metal nanocluster improves electrical and optical characteristics of the silicon nanowire, and thus can be usefully used in various electrical devices such as a lithium battery, a solar cell, a bio sensor, a memory device, or the like.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: April 15, 2014
    Assignees: Samsung Electronics Co., Ltd., Dongguk University Industry-Academic Cooperation Foundation
    Inventors: Gyeong-su Park, In-yong Song, Sung Heo, Dong-wook Kwak, Hoon Young Cho, Han-su Kim, Jae-man Choi, Moon-seok Kwon
  • Patent number: 8699206
    Abstract: Methods and apparatus for storing information or energy. An array of nano vacuum tubes is evacuated to a pressure below 10?6 Torr, where each nano vacuum tube has an anodic electrode, a cathodic electrode spaced apart from the anodic electrode, and an intervening evacuated region. An excess of electrons is stored on the cathodic electrode.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: April 15, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Alfred W. Hubler, Onyeama Osuagwu
  • Publication number: 20140097502
    Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 10, 2014
    Applicants: Seoul National University R & DB Foundation, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Chul SUN, Byung-Gook PARK
  • Publication number: 20140090842
    Abstract: A variety of methods and compositions are disclosed, including, in one embodiment, a method of cementing comprising: providing an aqueous dispersion comprising deagglomerated inorganic nanotubes and water; preparing a cement composition using the aqueous dispersion; introducing the cement composition into a subterranean formation; and allowing the cement composition to set. Another method comprises a method of cementing comprising: providing an ultrasonicated aqueous dispersion comprising deagglomerated nanoparticles, a dispersing agent, and water; preparing a cement composition using the aqueous dispersion; introducing the cement composition into is subterranean formation; and allowing the cement composition to set.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: HALLIBURTON ENERGY SERVICES, INC.
    Inventors: Rahul Chandrakat Patil, Ramesh Muthusamy, B. Raghava Reddy, Abhimanyu Pramod Deshpande, Sohini Bose
  • Patent number: 8685877
    Abstract: A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 1017 atoms/cm3 to be obtained.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: April 1, 2014
    Assignee: IMEC
    Inventors: Francesca Iacopi, Philippe M. Vereecken
  • Patent number: 8685323
    Abstract: Methods and apparatuses for encapsulating inorganic micro- or nanostructures within polymeric microgels are described. In various embodiments, viruses are encapsulated with microgels during microgel formation. The viruses can provide a template for in situ synthesis of the inorganic structures within the microgel. The inorganic structures can be distributed substantially homogeneously throughout the microgel, or can be distributed non-uniformly within the microgel. The inventive microgel compositions can be used for a variety of applications including electronic devices, biotechnological devices, fuel cells, display devices and optical devices.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: April 1, 2014
    Assignees: Massachusetts Institute of Technology, President and Fellows of Harvard College
    Inventors: Yoon Sung Nam, Angela Belcher, Andrew Magyar, Daeyeon Lee, Jin-Woong Kim, David Weitz
  • Patent number: 8685348
    Abstract: The invention concerns a nanowire structural element which is suited for implementation in, for example, a microreactor system or microcatalyzer system. For the production of the nanowire structural element, a template based process is used wherein the electrochemical deposition of the nanowires in nanopores is ideally carried out at least until caps are formed and said caps ideally are at least partially merged together. After reinforcing the two cover layers the structured hollow chamber between the two cover layers is cleared by dissolving the template foil and removing the dissolved template material, wherein the two cover layers remain intact. In this manner, a stable sandwich-like nanostructure is constructed with a two-dimensional hollow chamber-like structure in the plane parallel to the cover layers contained on both sides by the cover layers and permeated in a column-like manner with nanowires.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: April 1, 2014
    Assignee: GSI Helmholtzzentrum fur Schwerionenforschung GmbH
    Inventors: Thomas Cornelius, Wolfgang Ensinger, Reinhard Neumann, Markus Rauber
  • Patent number: 8685844
    Abstract: A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions. The amorphous alumina portions are removed and the remaining dense alumina portions which have an ordered lattice arrangement are employed as an etch mask. After removing the amorphous alumina portions, each dense alumina portion has a width which is also less than 10 nm.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8680514
    Abstract: An electric energy generator may include a semiconductor layer and a plurality of nanowires having piezoelectric characteristics. The electric energy generator may convert optical energy into electric energy if external light is applied and may generate piezoelectric energy if external pressure (e.g., sound or vibration) is applied.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jun Park, Seung-nam Cha
  • Patent number: 8679949
    Abstract: A silicon nanowire includes metal nanoclusters formed on a surface thereof at a high density. The metal nanoclusters improve electrical and optical characteristics of the silicon nanowire, and thus can be usefully used in various electrical devices such as a lithium battery, a solar cell, a bio sensor, a memory device, or the like.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: March 25, 2014
    Assignees: Samsung Electronics Co., Ltd., Dongguk University Industry-Academic Cooperation Foundation
    Inventors: Gyeong-su Park, In-yong Song, Sung Heo, Dong-wook Kwak, Hoon Young Cho, Han-su Kim, Jae-man Choi, Moon-seok Kwon
  • Patent number: 8680574
    Abstract: A hybrid nanostructure array having a substrate and two types of nanostructures, including a set of first nanostructures extending from the substrate and a set of second nanostructures interspersed among the first nanostructures. The first and second nanostructures comprise structures having nanoscale proportions in two dimensions and being elongate in the third dimension. For example, the nanostructures can be nanotubes, nanowires, nanorods, nanocolumns, and/or nanofibers. Also disclosed is a hybrid nanoparticle array using two different types of nanoparticles that have all three dimensions in the nanoscale. The two types of nanostructures or nanoparticles can vary in composition, shape, or size.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: March 25, 2014
    Assignee: The Regents of The University of Michigan
    Inventor: Anastasios John Hart
  • Publication number: 20140079912
    Abstract: The present disclosure relates to solution processed nanomaterials, and methods for their manufacture, with activity in the infrared (IR) region for a variety of commercial and defense applications, including conformal large-area IR coatings, devices and pigments that necessitate an absorption band edge in the MWIR or LWIR.
    Type: Application
    Filed: September 17, 2012
    Publication date: March 20, 2014
    Inventors: Larken E. Euliss, Brett Nosho, Nicole L. Abueg, G. Michael Granger, Peter D. Brewer, Maryam Behroozi
  • Publication number: 20140080293
    Abstract: A solar cell includes a plurality of nanowires arranged such that diameters of the nanowires sequentially increase in a first direction along a path of incident light. In a method of forming nanowires, a catalyst layer is formed on a substrate, a plurality of nanoparticles are formed by thermally processing the catalyst layer, and nanowires are grown from the plurality of nanoparticles. The catalyst layer has a thickness that increases in a first direction, and the plurality of nanoparticles have diameters that increase in the first direction.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jun PARK, Chan-wook BAIK
  • Patent number: 8673750
    Abstract: A method can include depositing a thin metal film on a substrate of a sample, establishing a metal island on the substrate by patterning the thin metal film, and annealing the sample to de-wet the metal island and form a metal droplet from the metal island. The method can also include growing a nanowire on the substrate using the metal droplet as a catalyst, depositing a thin film of a semiconductor material on the sample, annealing the sample to allow for lateral crystallization to form a crystal grain, and patterning the crystal grain to establish a crystal island. An electronic device can be fabricated using the crystal island.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: March 18, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Robert A. Street, Sourobh Raychaudhuri
  • Publication number: 20140072871
    Abstract: A rechargeable lithium cell comprising: (a) an anode comprising an anode active material; (b) a cathode comprising a hybrid cathode active material composed of an electrically conductive substrate and a phthalocyanine compound chemically bonded to or immobilized by the conductive substrate, wherein the phthalocyanine compound is in an amount of from 1% to 99% by weight based on the total weight of the conductive substrate and the phthalocyanine compound combined; and (c) electrolyte or a combination of electrolyte and a porous separator, wherein the separator is disposed between the anode and the cathode and the electrolyte is in ionic contact with the anode and the cathode. This secondary cell exhibits a long cycle life, the best cathode specific capacity, and best cell-level specific energy of all rechargeable lithium-ion cells ever reported.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Inventors: Guorong Chen, Zhenning Yu, Aruna Zhamu, Bor Z. Jang
  • Publication number: 20140070251
    Abstract: The invention provides a reflective phase retarder and a semiconductor light-emitting device including such reflective phase retarder. The reflective phase retarder of the invention converts an incident light beam with a first type polarization into the light with a second type polarization, and reflects the converted light beam with the second type polarization out.
    Type: Application
    Filed: May 3, 2013
    Publication date: March 13, 2014
    Applicant: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventor: Yi-Jun Jen
  • Publication number: 20140072879
    Abstract: Disclosed is an electrode material comprising a phthalocyanine compound encapsulated by a protective material, preferably in a core-shell structure with a phthalocyanine compound core and a protective material shell. Also disclosed is a rechargeable lithium cell comprising: (a) an anode; (b) a cathode comprising an encapsulated or protected phthalocyanine compound as a cathode active material; and (c) a porous separator disposed between the anode and the cathode and/or an electrolyte in ionic contact with the anode and the cathode. This secondary cell exhibits a long cycle life, the best cathode specific capacity, and best cell-level specific energy of all rechargeable lithium-ion cells ever reported.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Inventors: Guorong Chen, Bor Z. Jang, Aruna Zhamu
  • Patent number: 8669544
    Abstract: Amongst the candidates for very high efficiency solid state light sources and full solar spectrum solar cells are devices based upon InGaN nanowires. Additionally these nanowires typically require heterostructures, quantum dots, etc which all place requirements for these structures to be grown with relatively few defects and in a controllable reproducible manner. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. According to the invention a method of growing relatively defect free nanowires and associated structures for group IIIA-nitrides is presented without the requirement for foreign metal catalysts and overcoming the non-uniform growth of prior art non-catalyst growth techniques. According to other embodiments of the invention self-organizing dot-within-a-dot nanowire and dot-within-a-dot-within-a-well nanowire structures are presented.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 11, 2014
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Zetian Mi, Kai Cui, Hieu Pham Trung Nguyen