Information Storage Or Retrieval Using Nanostructure Patents (Class 977/943)
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Patent number: 8228743Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: GrantFiled: February 10, 2011Date of Patent: July 24, 2012Assignee: Micron Technology, Inc.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Nirmal Ramaswamy, Ronald A Weimer, Arup Bhattacharyya
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Publication number: 20120175696Abstract: Multilayer floating gate field-effect transistor (FET) devices and related methods are provided. A multilayer floating gate FET device can include a first floating gate separated via a first dielectric layer from a channel of the device and a second floating gate separated via a second dielectric layer from the first floating gate. The second dielectric layer between the first floating gate and the second floating gate permits a redistribution of charge between the first and second floating gates from one of the floating gates to the other when under the influence of a first electrical field from a first voltage. In some embodiments, a redistribution of charge between the first and second floating gates with electrons being supplied through a channel to the first and second floating gates can occur when under the influence of a second electrical field from a second voltage that is greater than the first voltage.Type: ApplicationFiled: November 9, 2011Publication date: July 12, 2012Applicant: NORTH CAROLINA STATE UNIVERSITYInventors: Paul D. Franzon, Neil Di Spigna, Daniel Schinke
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Patent number: 8217490Abstract: Under one aspect, a non-volatile nanotube switch includes a first terminal; a nanotube block including a multilayer nanotube fabric, at least a portion of which is positioned over and in contact with at least a portion of the first terminal; a second terminal, at least a portion of which is positioned over and in contact with at least a portion of the nanotube block, wherein the nanotube block is constructed and arranged to prevent direct physical and electrical contact between the first and second terminals; and control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube block can switch between a plurality of electronic states in response to a plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube block provides an electrical pathway of different resistance between the first and second terminals.Type: GrantFiled: August 8, 2007Date of Patent: July 10, 2012Assignee: Nantero Inc.Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, Ramesh Sivarajan, Eliodor G. Ghenciu, Steven L. Konsek, Mitchell Meinhold, Jonathan W. Ward, Darren K. Brock
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Publication number: 20120170354Abstract: An apparatus including a first electrode; a second electrode including graphene; and a dielectric between the first electrode and the second electrode; input circuitry configured to change a charge state of the dielectric by causing electric charges to be trapped in the dielectric; and output circuitry configured to detect a value dependent upon a quantum capacitance of the graphene of the second electrode, wherein the quantum capacitance of the graphene is dependent upon the charge state of the dielectric.Type: ApplicationFiled: January 5, 2011Publication date: July 5, 2012Inventors: Martti Kalevi VOUTILAINEN, Pirjo M. Pasanen
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Patent number: 8211765Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.Type: GrantFiled: September 9, 2011Date of Patent: July 3, 2012Assignee: Northeastern UniversityInventors: Sivasubramanian Somu, Ahmed Busnaina, Nicol McGruer, Peter Ryan, George G. Adams, Xugang Xiong, Taehoon Kim
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Publication number: 20120161223Abstract: A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.Type: ApplicationFiled: March 8, 2012Publication date: June 28, 2012Inventor: Arup Bhattacharyya
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Publication number: 20120147716Abstract: A thermally-assisted magnetic head that has an air bearing surface (ABS) facing a recording medium and that performs magnetic recording while heating the recording medium includes: a magnetic recording element that includes a pole of which an edge part is positioned on the ABS and which generates magnetic flux traveling to the recording medium; a waveguide that is configured with a core through which light propagates and a cladding, surrounding a periphery of the core, at least one part of which extends to the ABS; a plasmon generator that faces a part of the core and that extends toward the ABS side; and a bank layer that is positioned between the plasmon generator and the pole, and of which an edge part on the ABS side protrudes relative to the plasmon generator.Type: ApplicationFiled: December 8, 2010Publication date: June 14, 2012Applicant: TDK CorporationInventors: Shinji HARA, Kosuke Tanaka, Keita Kawamori, Daisuke Miyauchi, Takahiko Izawa, Eiji Komura
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Publication number: 20120141833Abstract: [Problem] A perpendicular magnetic disk with an improved SNR and an increased recording density by further improving crystal orientation of a preliminary ground layer formed of an Ni-base alloy is provided. [Solution] A typical structure of the perpendicular magnetic disk according to the present invention includes, on a base 110, a soft magnetic layer 130, a Ta alloy layer 140 provided on the soft magnetic layer 130, an Ni alloy layer 142 provided on the Ta alloy layer 140, a ground layer 150 provided on the Ni alloy layer 142 and having Ru as a main component, and a granular magnetic layer 160 provided on the ground layer 150. The Ta alloy layer 140 is a layer containing 10 atomic percent or more and 45 atomic percent or less Ta and having amorphous and soft magnetic properties.Type: ApplicationFiled: May 31, 2011Publication date: June 7, 2012Applicant: WD MEDIA (SINGAPORE) PTE. LTD.Inventors: TEIICHIRO UMEZAWA, KAZUAKI SAKAMOTO
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Patent number: 8193568Abstract: Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.Type: GrantFiled: June 14, 2010Date of Patent: June 5, 2012Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 8193030Abstract: Nonvolatile memory devices may be fabricated to include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to the switching device, a first insulating layer, a middle metal layer, a second insulating layer, an upper metal layer, a carbon nanotube layer, and/or a passivation layer stacked on the lower metal layer.Type: GrantFiled: January 3, 2011Date of Patent: June 5, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-wook Moon, Joong S. Jeon, El Mostafa Bourim, Hyun-deok Yang
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Publication number: 20120132898Abstract: The present invention relates to compositions comprising functionalized or un-functionalized multi cyclic hydrocarbons and functional organic compounds, which can be used in different electronic devices. The invention further relates to an electronic device comprising one or more organic functional layers, wherein at least one of the layers comprises at least one functionalized or un-functionalized multi cyclic hydrocarbon. Another embodiment of the present invention relates to a formulation comprising functionalized or un-functionalized multi cyclic hydrocarbons, from which a thin layer comprising at least one functionalized or un-functionalized multi cyclic hydrocarbon can be formed.Type: ApplicationFiled: July 7, 2010Publication date: May 31, 2012Applicant: Merck Patent GmbHInventors: Junyou Pan, Thomas Eberle, Herwig Buchholz
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Patent number: 8183665Abstract: A high-density memory array. A plurality of word lines and a plurality of bit lines are arranged to access a plurality of memory cells. Each memory cell includes a first conductive terminal and an article in physical and electrical contact with the first conductive terminal, the article comprising a plurality of nanoscopic particles. A second conductive terminal is in physical and electrical contact with the article. Select circuitry is arranged in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals. The article has a physical dimension that defines a spacing between the first and second conductive terminals such that the nanotube article is interposed between the first and second conducive terminals. A logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell.Type: GrantFiled: November 19, 2008Date of Patent: May 22, 2012Assignee: Nantero Inc.Inventors: Claude L. Bertin, Eliodor G. Ghenciu, Thomas Rueckes, H. Montgomery Manning
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Patent number: 8184473Abstract: A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.Type: GrantFiled: August 31, 2010Date of Patent: May 22, 2012Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Jin-gyoo Yoo, Cheol-soon Kim, Jung-hoon Lee
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Publication number: 20120120780Abstract: Provided is a thermally-assisted magnetic recording head in which NF-light with sufficiently high light density can be applied to a medium while a write-field generating point and a near-field light (NF-light) generating point are close to each other. The head comprises a plasmon generator provided between a magnetic pole and a waveguide and configured to be coupled with light propagating through the waveguide in a surface plasmon mode to emit NF-light. The plasmon generator comprises: a plasmon propagating part comprising a propagation edge for propagating surface plasmon excited by the light; and a light penetration suppressing part with an extinction coefficient greater than the plasmon propagating part. The light penetration suppressing part is in surface-contact with a surface portion of the plasmon propagating part excluding the propagation edge, and the magnetic pole is in surface-contact with the light penetration suppressing part.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: TDK CORPORATIONInventors: EIJI KOMURA, TSUTOMU CHOU, KOJI SHIMAZAWA
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Publication number: 20120104352Abstract: According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.Type: ApplicationFiled: March 21, 2011Publication date: May 3, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kenji AOYAMA, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
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Publication number: 20120104325Abstract: Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a solution of the same, a method for making the same from a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, imaging devices, phase change layers, and sensor devices.Type: ApplicationFiled: April 23, 2010Publication date: May 3, 2012Applicant: THE UNIVERSITY OF CHICAGOInventors: Dmitri V. Talapin, Maksym V. Kovalenko, Jong-Soo Lee, Chengyang Jiang
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Publication number: 20120104346Abstract: A semiconductor device for providing heat management may include a first electrode with low metal thermal conductivity and a second electrode with low metal thermal conductivity. A metal oxide structure which includes a transition metal oxide (TMO) may be electrically coupled to the first electrode and second electrode and the metal oxide structure may be disposed between the first electrode and second electrode. An electrically insulating sheath with low thermal conductivity may surround the metal oxide structure.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Inventors: Wei Yi, Matthew D. Pickett, Gilberto Medeiros Ribeiro
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Patent number: 8148708Abstract: A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element.Type: GrantFiled: December 26, 2008Date of Patent: April 3, 2012Assignee: Hynix Semiconductor Inc.Inventors: Yun-Taek Hwang, Yu-Jin Lee
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Publication number: 20120075967Abstract: A thermally assisted magnetic head includes a magnetic pole that generates a writing magnetic field from an air bearing surface (ABS); a waveguide through which light propagates; and a plasmon generator generating near-field light from a near-field light generating end surface by coupling the light thereto in a surface plasmon mode. The magnetic pole includes a convex part protruding in a substantially V-shape along a light propagation direction of the waveguide. The plasmon generator includes a substantially V-shaped part contacting the convex part, and as seen from a side of the ABS, a thickness of the plasmon generator in a direction perpendicular to convex part contacting sides gradually increases from an end in a direction away from the waveguide, the convex part contacting sides being linear sides that form the substantially V-shaped part of the plasmon generator and contacting the convex part.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Applicant: TDK CORPORATIONInventors: Tsutomu Chou, Eiji Komura, Shinji Hara, Kosuke Tanaka, Daisuke Miyauchi
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Patent number: 8138572Abstract: The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode of a cell region and a via contact of peripheral circuit region. Therefore, capacitance of the lower electrode is secured without an etching process for high aspect ratio. Also, the via contact can be formed for corresponding to the height of the lower electrode.Type: GrantFiled: December 17, 2009Date of Patent: March 20, 2012Assignee: Hynix Semiconductor IncInventor: Keon Yoo
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Publication number: 20120063276Abstract: A tubular or spherical nanostructure composed of a plurality of peptides, wherein each of the plurality of peptides includes no more than 4 amino acids and whereas at least one of the 4 amino acids is an aromatic amino acid.Type: ApplicationFiled: November 7, 2011Publication date: March 15, 2012Applicant: Ramot at Tel-Aviv University Ltd.Inventors: Meital Reches, Ehud Gazit
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Patent number: 8134220Abstract: Nanotube switching devices having nanotube bridges are disclosed. Two-terminal nanotube switches include conductive terminals extending up from a substrate and defining a void in the substrate. Nantoube articles are suspended over the void or form a bottom surface of a void. The nanotube articles are arranged to permanently contact at least a portion of the conductive terminals. An electrical stimulus circuit in communication with the conductive terminals is used to generate and apply selected waveforms to induce a change in resistance of the device between relatively high and low resistance values. Relatively high and relatively low resistance values correspond to states of the device. A single conductive terminal and a interconnect line may be used. The nanotube article may comprise a patterned region of nanotube fabric, having an active region with a relatively high or relatively low resistance value. Methods of making each device are disclosed.Type: GrantFiled: June 16, 2008Date of Patent: March 13, 2012Assignee: Nantero Inc.Inventors: H. Montgomery Manning, Thomas Rueckes, Jonathan W. Ward, Brent M. Segal
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Publication number: 20120056145Abstract: According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.Type: ApplicationFiled: February 1, 2011Publication date: March 8, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenji AOYAMA, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
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Patent number: 8130569Abstract: A device for storing data using nanoparticle shuttle memory having a nanotube. The nanotube has a first end and a second end. A first electrode is electrically connected to the first end of the nanotube. A second electrode is electrically connected to the second end of the nanotube. The nanotube has an enclosed nanoparticle shuttle. A switched voltage source is electrically connected to the first electrode and the second electrode, whereby a voltage may be controllably applied across the nanotube. A resistance meter is also connected to the first electrode and the second electrode, whereby the electrical resistance across the nanotube can be determined.Type: GrantFiled: April 27, 2010Date of Patent: March 6, 2012Assignee: The United States of America as represented by the United States Department of EnergyInventor: Alex Karlwalter Zettl
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Patent number: 8110476Abstract: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.Type: GrantFiled: April 6, 2009Date of Patent: February 7, 2012Assignee: SanDisk 3D LLCInventors: Roy E. Scheuerlein, Alper Ilkbahar, April D. Shricker
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Publication number: 20120012809Abstract: A switchable junction (600) having intrinsic diodes with different switching thresholds is disclosed. The switchable junction comprises a first electrode (610) formed of a first conductive material and a second electrode (630) formed of a second conductive material. The junction (600) further includes a memristive matrix (615) configured to form a first and a second electrical interface with the first and second electrodes to form a first rectifying diode interface (626) with a first switching threshold and a second rectifying diode interface (628) with a second switching threshold.Type: ApplicationFiled: June 25, 2009Publication date: January 19, 2012Inventors: Jianhua Yang, Shih-Yuan(SY) Wang, R. Stanley Williams
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Publication number: 20120012803Abstract: According to one embodiment, a nonvolatile memory device includes a lower electrode layer, a nanomaterial assembly layer, and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of micro conductive bodies assembled via a gap. The upper electrode layer is provided on the nanomaterial assembly layer. The portion of the micro conductive bodies is buried at least in a lower part of the upper electrode layer.Type: ApplicationFiled: December 20, 2010Publication date: January 19, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Shigeto OSHINO
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Patent number: 8097871Abstract: Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.Type: GrantFiled: April 30, 2009Date of Patent: January 17, 2012Assignee: Macronix International Co., Ltd.Inventors: Shih-Hung Chen, Yi-Chou Chen
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Patent number: 8093474Abstract: A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A nanostructure in another embodiment includes a substrate having an area with a nanofeature; and a nanowire extending from the nanofeature, the nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A method for forming a nanostructure is also presented. A method for reading and writing data is also presented. A method for preparing nanoparticles is also presented.Type: GrantFiled: March 19, 2008Date of Patent: January 10, 2012Assignee: Lawrence Livermore National Security, LLCInventors: Saleem Zaidi, Joseph W. Tringe, Ganesh Vanamu, Rajiv Prinja
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Patent number: 8089115Abstract: An organic memory device is disclosed that has an active layer, at least one charge storage layer of a film of an organic dielectric material, and nanostractures and/or nano-particles of a charge-storing material on or in the film of dielectric material. Each of the nanostructures and/or nano-particles is separated from the others of the nanostractures and/or nano-particles by the organic dielectric material of the organic dielectric film. A method of manufacturing the organic memory device is also disclosed.Type: GrantFiled: May 22, 2007Date of Patent: January 3, 2012Assignee: Nanyang Technological UniversityInventors: Wei Lin Leong, Pooi See Lee, Yeng Ming Lam, Lixin Song, Ebinazar Benjamin Namdas, G. Subodh Mhaisalkar
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Publication number: 20110309429Abstract: According to one embodiment, in a floating-gate type nonvolatile semiconductor memory device in which a tunnel dielectric film and a control gate electrode are connected between memory cells adjacent via a shallow trench isolation, each of a floating gate electrode and the control gate electrode includes an electric-field concentrated portion having a curvature on the tunnel dielectric film side. The electric-field concentrated portion of the floating gate electrode is formed over a forming position of a channel semiconductor. The electric-field concentrated portion of the control gate electrode is formed over a forming position of the shallow trench isolation.Type: ApplicationFiled: January 28, 2011Publication date: December 22, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Masahiro KIYOTOSHI
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Publication number: 20110291064Abstract: Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode common to a first and a second resistance variable memory cell, a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Eugene P. Marsh, Timothy A. Quick
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Patent number: 8062939Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.Type: GrantFiled: February 18, 2011Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Kenji Kawabata
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Patent number: 8063455Abstract: A multi-terminal electromechanical nanoscopic switching device which may be used as a memory device, a pass gate, a transmission gate, or a multiplexer, among other things.Type: GrantFiled: November 22, 2005Date of Patent: November 22, 2011Assignee: Agate Logic, Inc.Inventors: Louis Charles Kordus, II, Colin Neal Murphy, Malcolm John Wing
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Patent number: 8064249Abstract: A nanowire electromechanical switching device is constructed with a source electrode and a drain electrode disposed on an insulating substrate and spaced apart from each other, a first nanowire vertically grown on the source electrode and to which a V1 voltage is applied, a second nanowire vertically grown on the drain electrode and to which a V2 voltage having an opposite polarity to that of the V1 voltage is applied, and a gate electrode spaced apart from the second nanowire, partially surrounding the second nanowire and having an opening that faces the first nanowire in order to avoid disturbing a mutual switching operation of the first nanowire and the second nanowire and to which a V3 voltage having the same polarity as that of the V2 voltage is applied.Type: GrantFiled: August 14, 2007Date of Patent: November 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Eun Jang, Seung-Nam Cha, Byong-Gwon Song, Yong-Wan Jin
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Publication number: 20110278661Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of electronic devices and systems. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge traps.Type: ApplicationFiled: July 29, 2011Publication date: November 17, 2011Inventors: Eugene P. Marsh, Brenda D. Kraus
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Phase change memory device having phase change material layer containing phase change nano particles
Patent number: 8049202Abstract: A phase change memory device including a phase change material layer having phase change nano particles and a method of fabricating the same are provided. The phase change memory device may include a first electrode and a second electrode facing each other, a phase change material layer containing phase change nano particles interposed between the first electrode and the second electrode and/or a switching device electrically connected to the first electrode. The phase change material layer may include an insulating material.Type: GrantFiled: March 6, 2009Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Ho Khang, Wil-Liam Jo, Dong-Seok Suh -
Patent number: 8050081Abstract: A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation.Type: GrantFiled: April 23, 2008Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jea-Gun Park, Sung-Ho Seo, Woo-Sik Nam, Young-Hwan Oh, Yool-Guk Kim, Hyun-Min Seung, Jong-Dae Lee
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Patent number: 8050078Abstract: Embodiments of the present invention are directed to memristor devices that provide nonvolatile memristive switching. In one embodiment, a memristor device includes a first electrode, a second electrode, and a nanowire disposed between the first electrode and the second electrode. The nanowire is configured with an inner region surrounded by an outer layer. The memristor device may also include a mobile dopant confined to the inner region by repulsive electrostatic forces between the outer layer and the mobile dopant. The resistance of the nanowire is determined by the distribution of the mobile dopant in the inner region.Type: GrantFiled: October 27, 2009Date of Patent: November 1, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Alexandre M. Bratkovski, Viatcheslav Osipov
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Patent number: 8045359Abstract: Disclosed is a switching element including: an insulative substrate; a first electrode and a second electrode provided to the insulative substrate; an interelectrode gap between the first electrode and the second electrode, comprising a gap of a nanometer order which causes switching phenomenon of resistance by applying a predetermined voltage between the first electrode and the second electrode; and a sealing member to seal the interelectrode gap such that the gap is retained.Type: GrantFiled: August 20, 2008Date of Patent: October 25, 2011Assignees: Funai Electric Advanced Applied Technology Research Institute Inc., Funai Electric Co., Ltd.Inventors: Shigeo Furuta, Tsuyoshi Takahashi, Masatoshi Ono
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Patent number: 8031514Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.Type: GrantFiled: April 9, 2008Date of Patent: October 4, 2011Assignee: Northeastern UniversityInventors: Sivasubramanian Somu, Ahmed Busnaina, Nicol McGruer, Peter Ryan, George G. Adams, Xugang Xiong, Taehoon Kim
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Publication number: 20110227032Abstract: A memristor having an active region includes a first electrode. The first electrode comprises a nanostructure formed of at least one metallic single walled nanotube. The memristor also includes a second electrode formed of at least one metallic single walled nanotube. The second electrode is positioned in a crossed relationship with respect to the first electrode. The memristor further includes a switching material positioned between the first electrode and the second electrode, in which the active region is configured to form in the switching material at a cross point of the first electrode and the second electrode.Type: ApplicationFiled: January 15, 2009Publication date: September 22, 2011Inventors: Qiangfei Xia, Jing Tang
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Patent number: 8022408Abstract: Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.Type: GrantFiled: March 22, 2010Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
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Publication number: 20110216584Abstract: An electromechanical switch is described, which comprises a conductive body and a plurality of carbon nanotubes being separate to each other, each of the carbon nanotubes being connected to at least one common terminal electrode with at least one of its ends, wherein in an open state of the switch each of the carbon nanotubes substantially projects along a surface of the conductive body and keeps up a gap to said surface, and wherein in a closed state of the switch at least one carbon nanotube is bend in a direction of the surface to close an electrical contact between said terminal electrode and the conductive body. The size of the gap between the respective carbon nanotube and the surface is different for each one of the plurality of carbon nanotubes.Type: ApplicationFiled: February 11, 2011Publication date: September 8, 2011Inventors: Meinolf Blawat, Herbert Schuetze, Holger Kropp
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Patent number: 8008745Abstract: A non-volatile latch circuit is provided. The non-volatile latch circuit includes a nanotube switching element capable of switching between resistance states and non-volatilely retaining the resistance state. The non-volatile latch circuit includes a volatile latch circuit is capable of receiving and volatilely storing a logic state. When the nanotube switching element is a resistance state, the volatile latch circuit retains a corresponding logic state and outputs that corresponding logic state at an output terminal. A non-volatile register file configuration circuit for use with a plurality of non-volatile register files is also provided. The non-volatile register file configuration circuit includes a selection circuitry and a plurality of nanotube fuse elements, each in electrical communication with one of a plurality of non-volatile register files.Type: GrantFiled: August 8, 2007Date of Patent: August 30, 2011Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, Jonathan W. Ward, Frank Guo, Steven L. Konsek, Mitchell Meinhold
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Publication number: 20110204331Abstract: The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.Type: ApplicationFiled: March 26, 2008Publication date: August 25, 2011Inventors: Lars Samuelson, Claes Thelander
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Publication number: 20110199832Abstract: An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element.Type: ApplicationFiled: April 28, 2011Publication date: August 18, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Insik Jin, Yang Li, Hongyue Liu, Song S. Xue
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Publication number: 20110193044Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam.Type: ApplicationFiled: February 8, 2010Publication date: August 11, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Gurtej S. Sandhu, John Smythe
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Patent number: 7990751Abstract: A nanogap switching element is equipped with an inter-electrode gap portion including a gap of a nanometer order between a first electrode and a second electrode. A switching phenomenon is caused in the inter-electrode gap portion by applying a voltage between the first and second electrodes. The nanogap switching element is shifted from its low resistance state to its high resistance state by receiving a voltage pulse application of a first voltage value, and shifted from its high resistance state to its low resistance state by receiving a voltage pulse application of a second voltage value lower than the first voltage value. When the nanogap switching element is shifted from the high resistance state to the low resistance state, a voltage pulse of an intermediate voltage value between the first and second voltage values is applied thereto before the voltage pulse application of the second voltage value thereto.Type: GrantFiled: December 18, 2008Date of Patent: August 2, 2011Assignees: Funai Electric Advanced Applied Technology Research Institute Inc., National Institute of Advanced Industrial Science and Technology, Funai Electric Co., Ltd.Inventors: Yuichiro Masuda, Shigeo Furuta, Tsuyoshi Takahashi, Tetsuo Shimizu, Yasuhisa Naitoh, Masayo Horikawa
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Patent number: 7986546Abstract: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.Type: GrantFiled: June 30, 2008Date of Patent: July 26, 2011Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Frank Guo, Thomas Rueckes, Steven L. Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X. M. Henry Huang