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  • Programming analog memory cells for reduced variance after retention
    Patent number: 7864573
    Abstract: A method includes defining a nominal level of a physical quantity to be stored in analog memory cells for representing a given data value. The given data value is written to the cells in first and second groups of the cells, which have respective first and second programming responsiveness such that the second responsiveness is different from the first responsiveness, by applying to the cells in the first and second groups respective, different first and second patterns of programming pulses that are selected so as to cause the cells in the first and second groups to store respective levels of the physical quantity that fall respectively in first and second ranges, such that the first range is higher than and the second range is lower than the nominal level. The given data value is read from the cells at a later time.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: January 4, 2011
    Assignee: Anobit Technologies Ltd.
    Inventors: Uri Perlmutter, Ofir Shalvi
  • Reading memory cells using multiple thresholds
    Patent number: 8145984
    Abstract: A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: March 27, 2012
    Assignee: Anobit Technologies Ltd.
    Inventors: Naftali Sommer, Ofir Shalvi, Dotan Sokolov
  • Optimized Selection of Memory Chips in Multi-Chips Memory Devices
    Publication number: 20100220510
    Abstract: A method includes accepting a definition of a type of multi-unit memory device (28) including a set of memory units (24), each having a respective nominal storage capacity, the definition specifying a target memory size of the memory device such that a sum of nominal storage capacities of the memory units in the set is equal to the target memory size. A plurality of the memory units is accepted. The memory units have respective actual storage capacities, at least some of which differ from the respective nominal storage capacity. Multi-unit memory devices including respective sets of the memory units are assembled, such that at least one of the sets includes at least a first memory unit having a first actual capacity that is less than the respective nominal capacity and at least a second memory unit having a second actual capacity that is greater than the nominal capacity.
    Type: Application
    Filed: November 4, 2008
    Publication date: September 2, 2010
    Applicant: ANOBIT TECHNOLOGIES LTD
    Inventor: Ofir Shalvi
  • Reading analog memory cells using built-in multi-threshold commands
    Patent number: 8068360
    Abstract: A method for data storage includes storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values. The memory has at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number. After storing the data, the first data bits are read from the memory cells by executing at least the second built-in command.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: November 29, 2011
    Assignee: Anobit Technologies Ltd.
    Inventor: Micha Anholt
  • Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
    Patent number: 8000135
    Abstract: A method for data storage includes storing data in a group of analog memory cells by writing into the memory cells in the group respective storage values, which program each of the analog memory cells to a respective programming state selected from a predefined set of programming states. The programming states include at least first and second programming states, which are applied respectively to first and second subsets of the memory cells, whereby the storage values held in the memory cells in the first and second subsets are distributed in accordance with respective first and second distributions. Respective first and second medians of the first and second distributions are estimated, and a read threshold is calculated based on the first and second medians. The data is retrieved from the analog memory cells in the group by reading the storage values using the calculated read threshold.
    Type: Grant
    Filed: September 13, 2009
    Date of Patent: August 16, 2011
    Assignee: Anobit Technologies Ltd.
    Inventors: Uri Perlmutter, Shai Winter, Eyal Gurgi, Oren Golov, Micha Anholt
  • Data storage using modified voltages
    Patent number: 7995388
    Abstract: A method for data storage includes storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing an input storage value into the target memory cell. A first read operation, which reads a first output storage value from the target memory cell while biasing the other memory cells with respective first pass voltages, is applied to the target memory cell. A second read operation, which reads a second output storage value from the target memory cell while biasing the other memory cells with respective second pass voltages, is applied to the target memory cell. At least one of the second pass voltages is different from a respective first pass voltage. The data is reconstructed responsively to the first and second output storage values.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: August 9, 2011
    Assignee: Anobit Technologies Ltd.
    Inventors: Shai Winter, Ofir Shalvi
  • Memory device with non-uniform programming levels
    Patent number: 7925936
    Abstract: A method for storing data in a memory, which includes a plurality of analog memory cells, includes defining programming levels that represent respective combinations of at least first and second bits and are represented by respective nominal storage values. The data is stored by mapping the data to storage values selected from among the nominal storage values and writing the storage values to the memory cells. A condition is defined over two or more bit-specific error rates applicable respectively to at least the first and second bits. The bit-specific error rates include a first bit-specific error rate computed over the data stored by the first bits and a second bit-specific error rate computed, separately from the first bit-specific error rate, over the data stored by the second bits. The nominal storage values are set based on the bit-specific error rates so as to meet the condition.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: April 12, 2011
    Assignee: Anobit Technologies Ltd.
    Inventor: Naftali Sommer
  • MEMORY DEVICE WITH INTERNAL SIGNAP PROCESSING UNIT
    Publication number: 20100131827
    Abstract: A method for operating a memory (36) includes storing data in a plurality of analog memory cells (40) that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry (48) that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller (28), which is fabricated on a second semiconductor die that is different from the first semiconductor die, so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.
    Type: Application
    Filed: April 16, 2008
    Publication date: May 27, 2010
    Applicant: ANOBIT TECHNOLOGIES LTD
    Inventors: Dotan Sokolov, Naftali Sommer, Ofir Shalvi, Uri Perlmutter
  • EFFICIENT INTERFERENCE CANCELLATION IN ANALOG MEMORY CELL ARRAYS
    Publication number: 20090158126
    Abstract: A method includes storing data in a group of analog memory cells by writing first storage values to the cells. After storing the data, second storage values are read from the cells using one or more first read thresholds. Third storage values that potentially cause cross-coupling interference in the second storage values are identified, and the third storage values are processed, to identify a subset of the second storage values as severely-interfered values. Fourth storage values are selectively re-read from the cells holding the severely-interfered values using one or more second read thresholds, different from the first read thresholds. The cross-coupling interference in the severely-interfered storage values is canceled using the re-read fourth storage values. The second storage values, including the severely-interfered values in which the cross-coupling interference has been canceled, are processed so as to reconstruct the data stored in the cell group.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 18, 2009
    Applicant: ANOBIT TECHNOLOGIES LTD
    Inventors: Uri Perlmutter, Yoav Kasorla, Oren Golov
  • Efficient interference cancellation in analog memory cell arrays
    Patent number: 8209588
    Abstract: A method includes storing data in a group of analog memory cells by writing first storage values to the cells. After storing the data, second storage values are read from the cells using one or more first read thresholds. Third storage values that potentially cause cross-coupling interference in the second storage values are identified, and the third storage values are processed, to identify a subset of the second storage values as severely-interfered values. Fourth storage values are selectively re-read from the cells holding the severely-interfered values using one or more second read thresholds, different from the first read thresholds. The cross-coupling interference in the severely-interfered storage values is canceled using the re-read fourth storage values. The second storage values, including the severely-interfered values in which the cross-coupling interference has been canceled, are processed so as to reconstruct the data stored in the cell group.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: June 26, 2012
    Assignee: Anobit Technologies Ltd.
    Inventors: Uri Perlmutter, Yoav Kasorla, Oren Golov
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