Search Patents
  • Patent number: 9706667
    Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material. A layer of catalytic adhesive coats walls within the hole. The patterned metal layer is placed over the catalytic adhesive within the hole.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: July 11, 2017
    Assignee: SIERRA CIRCUITS, INC.
    Inventors: Konstantine Karavakis, Kenneth S. Bahl
  • Patent number: 9631279
    Abstract: A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic core material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: April 25, 2017
    Assignee: Sierra Circuits, Inc.
    Inventors: Kenneth S. Bahl, Konstantine Karavakis, Steve Carney
  • Patent number: 9380700
    Abstract: A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: June 28, 2016
    Assignee: Sierra Circuits, Inc.
    Inventors: Konstantine Karavakis, Kenneth S. Bahl, Steve Carney
  • Patent number: 9398703
    Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: July 19, 2016
    Assignee: Sierra Circuits, Inc.
    Inventors: Konstantine Karavakis, Kenneth S. Bahl
  • Patent number: 9674967
    Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: June 6, 2017
    Assignee: Sierra Circuits, Inc.
    Inventors: Konstantine Karavakis, Kenneth S. Bahl
  • Publication number: 20190014667
    Abstract: A circuit board has a dielectric core, a foil top surface, and a thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.
    Type: Application
    Filed: July 10, 2017
    Publication date: January 10, 2019
    Applicant: Sierra Circuits, Inc.
    Inventors: Kenneth S. BAHL, Konstantine KARAVAKIS
  • Publication number: 20190014666
    Abstract: A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etch operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.
    Type: Application
    Filed: July 10, 2017
    Publication date: January 10, 2019
    Applicant: Sierra Circuits, Inc.
    Inventors: Kenneth S. BAHL, Konstantine KARAVAKIS
  • Publication number: 20180158793
    Abstract: A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 7, 2018
    Applicant: Sierra Circuits, Inc.
    Inventors: Kenneth S. BAHL, Konstantine KARAVAKIS
  • Patent number: 9922951
    Abstract: A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.
    Type: Grant
    Filed: November 12, 2016
    Date of Patent: March 20, 2018
    Assignee: Sierra Circuits, Inc.
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Publication number: 20200008306
    Abstract: A circuit board is formed from a non-catalytic laminate coated with an optically curable catalytic adhesive, which, after curing with an optical source such as UV, has a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etch operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.
    Type: Application
    Filed: June 30, 2018
    Publication date: January 2, 2020
    Applicant: Sierra Circuits, Inc.
    Inventors: Konstantine KARAVAKIS, Kenneth BAHL, Steve Carney
  • Publication number: 20190008044
    Abstract: A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Applicant: Sierra CIrcuits, Inc.
    Inventors: Konstantine KARAVAKIS, Kenneth S. BAHL
  • Publication number: 20190274221
    Abstract: A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. Trace channels and apertures are formed into the catalytic laminate, electroless plated with a metal such as copper, filled with a conductive paste containing metallic particles, which are then melted to form traces. In a variation, multiple circuit board layers have channels formed into the surface below the exclusion depth, apertures formed, are electroless plated, and the channels and apertures filled with metal particles. Several such catalytic laminate layers are placed together and pressed together under elevated temperature until the catalytic laminate layers laminate together and metal particles form into traces for a multi-layer circuit board.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 5, 2019
    Applicant: Sierra Circuits, Inc.
    Inventors: Kenneth S BAHL, Konstantine KARAVAKIS
  • Publication number: 20180054889
    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
    Type: Application
    Filed: May 23, 2017
    Publication date: February 22, 2018
    Applicant: Sierra Circuits, Inc.
    Inventors: Kenneth S. BAHL, Konstantine KARAVAKIS
  • Publication number: 20190239349
    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
    Type: Application
    Filed: April 11, 2019
    Publication date: August 1, 2019
    Applicant: Sierra Circuits, Inc.
    Inventors: Kenneth S. BAHL, Konstantine KARAVAKIS
  • Publication number: 20180168036
    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
    Type: Application
    Filed: January 23, 2018
    Publication date: June 14, 2018
    Applicant: Sierra Circuits, Inc.
    Inventors: Kenneth S. BAHL, Konstantine KARAVAKIS
  • Patent number: 9942981
    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 10, 2018
    Assignee: Sierra Circuits, Inc.
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Patent number: 9706650
    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: July 11, 2017
    Assignee: Sierra Circuits, Inc.
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Patent number: 10306756
    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 28, 2019
    Assignee: Sierra Circuits, Inc.
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
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