Search Patents
  • Oriented Polymer Fibers and Methods for Fabricating Thereof
    Publication number: 20080290554
    Abstract: Devices for fabricating oriented polymer fibers, and methods for fabricating thereof by electropulling, are provided.
    Type: Application
    Filed: March 31, 2005
    Publication date: November 27, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Benjamin M. Wu, Michael V. Sofroniew, King-Ning Tu, Yuhuan Xu
  • Prevention of Sn whisker growth for high reliability electronic devices
    Publication number: 20070117475
    Abstract: An electrical lead for an electronic device has a core conductor and a finishing layer of a Sn alloy deposited on a surface of the core conductor of the electrical lead. The finishing layer of the Sn alloy deposited on the surface of the core conductor is of a chemical composition that hinders the formation of Sn whiskers. An electronic device has such an electrical lead.
    Type: Application
    Filed: November 23, 2005
    Publication date: May 24, 2007
    Applicant: Regents of the University of California
    Inventor: King-Ning Tu
  • SINGLE CRYSTAL COPPER, MANUFACTURING METHOD THEREOF AND SUBSTRATE COMPRISING THE SAME
    Publication number: 20150064496
    Abstract: The present invention relates to a single crystal copper having [100] orientation and a volume of 0.1˜4.0×106 ?m3. The present invention further provides a manufacturing method for the single crystal copper and a substrate comprising the same.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventors: Chih CHEN, King-Ning TU, Chia-Ling LU
  • COPPER FILTER WITH FAST VIRUS KILLING ABILITY
    Publication number: 20230284628
    Abstract: A porous copper-based filter material that is electrodeposited with nanotwin copper to provide anti-pathogenic properties, particularly against Covid-19 or the SARS virus. The nanotwin copper is a thin layer of (111) oriented nanotwin copper microstructure.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 14, 2023
    Inventors: King-Ning TU, Yingxia LIU, Chang CHEN, Lit Man POON, Wing Hong CHIN, Jin QU, Yiyuan HENG
  • Method of forming dielectric material suitable for microelectronic circuits
    Patent number: 6280794
    Abstract: An improved dielectric material having pores formed therein and a method for forming the material are disclosed. The material is formed of a polymer. Pores within the polymer are formed by forming solid organic particles within the polymer and eventually vaporizing the particles to form pores within the polymer.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: August 28, 2001
    Assignee: Conexant Systems, Inc.
    Inventors: King-Ning Tu, Yuhuan Xu, Bin Zhao
  • Barrier improvement in thin films
    Patent number: 5294486
    Abstract: An improved thin film barrier with three layers where an interlayer is between barrier layers on each side, the interlayer serving as an atom energy sink. The improved barrier in the diffusion of Cu through Ni into Au where the barrier layers are Ni and the interlayer is Au, making a stack of AuNiAuNiCu, reduces the Cu present in the external Au layer after prolonged annealing in the vicinity of 0.2% atomic.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: March 15, 1994
    Assignee: International Business Machines Corporation
    Inventors: Milan Paunovic, King-Ning Tu
  • Process for protecting solder joints and structure for alleviating electromigration and joule heating in solder joints
    Publication number: 20060027933
    Abstract: This invention provides a process for protecting solder joints, comprising forming an UBM or pad metallurgy in solder joints and then further forming a small solder bump on UBM or pad metallurgy between substrate and chip. Wherein a material of high electric resistance is coated at the ends of UBM or pad metallurgy where substrate is connected to chip, as to equalize the current distribution of solder bump, therefore the electromigration resistance of solder joints is improved by suppressing the current crowding and joule heating phenomenon.
    Type: Application
    Filed: February 28, 2005
    Publication date: February 9, 2006
    Inventors: Chih Chen, Everett Yeh, King-Ning Tu
  • Asymmetric studs and connecting lines to minimize stress
    Patent number: 5504375
    Abstract: In the design of stud and conducting line joints, the conducting line is extended beyond the stud without any significant overhang of the line in the width direction for minimizing induced stress in order to reduce voids and crack growth in the region where the connecting line is joined to the stud. The preferred length of the extension is in the range approximately between one-quarter and twice the stud dimension. The design is applicable, but not limited to, multilevel integrated circuits used in computers and other electrical devices.
    Type: Grant
    Filed: November 18, 1993
    Date of Patent: April 2, 1996
    Assignee: International Business Machines Corporation
    Inventors: William H. Carlson, Leathen Shi, King-Ning Tu
  • Formation of 3-dimensional silicon silicide structures
    Patent number: 5463254
    Abstract: An epitaxial conductor and a method for forming buried conductor patterns is described incorporating a layer of single crystalline silicon, a pattern formed therein such as a trench, a layer of metal silicide epitaxial formed on the bottom surface of the pattern or trench, a layer of silicon epitaxially formed thereover, and a layer of metal silicide epitaxially formed over the silicon layer. The invention overcomes the problem of twinning defects in the top surface of epitaxial silicide layers.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: October 31, 1995
    Assignee: International Business Machines Corporation
    Inventors: Subramanian S. Iyer, Richard D. Thompson, King-Ning Tu
  • METHODS OF FABRICATING HIGHLY CONDUCTIVE REGIONS IN SEMICONDUCTOR SUBSTRATES FOR RADIO FREQUENCY APPLICATIONS
    Publication number: 20070117345
    Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.
    Type: Application
    Filed: January 23, 2007
    Publication date: May 24, 2007
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: King-Ning Tu, Ya-Hong Xie, Chang-Ching Yeh
  • AUXILIARY PREDICTION SYSTEM FOR PREDICTING RELIABILITY, AND METHOD AND COMPUTER PROGRAM PRODUCT THEREOF
    Publication number: 20220392049
    Abstract: An auxiliary prediction system is provided to predict reliability of an object after a specific operation is applied to the target object. The auxiliary prediction system includes an image correction module and an analysis module. The image correction module performs an image correction procedure to convert an original image of the target object into a first correction image. The analysis module performs a feature analysis on the first correction image through an artificial intelligence model that has been trained, so as to predict whether the target object has a defect or not after the specific operation.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 8, 2022
    Inventors: King-Ning TU, Chih CHEN, Yu-Chieh LO, Nan-Yow CHEN, Kai-Cheng SHIE
  • Electrodeposited Nano-Twins Copper Layer and Method of Fabricating the Same
    Publication number: 20160355940
    Abstract: An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 8, 2016
    Inventors: Chih CHEN, King-Ning TU, Taochi LIU
  • Aluminum-germanium alloys for VLSI metallization
    Patent number: 5308794
    Abstract: An apparatus and method for forming an interconnect through an opening or on an insulation layer with the coefficient of thermal expansion of the interconnect adjusted to reduce the thermal stress between the interconnect and the insulation layer is described incorporating the steps of forming a solid solution of a binary alloy including germanium and aluminum or a ternary alloy including aluminum, germanium and a third element, for example silicon, and forming a precipitate from the solid solution at a reduced temperature with respect to the temperature of forming the solid solution whereby the volume of the precipitate including germanium and the remaining solid solution is larger than the volume of the original solid solution.
    Type: Grant
    Filed: August 18, 1993
    Date of Patent: May 3, 1994
    Assignee: International Business Machines Corporation
    Inventor: King-Ning Tu
  • Smart-cut of a thin foil of poruous Ni from a Si wafer
    Publication number: 20060234079
    Abstract: The present invention is a method of fabricating a self-peeling nickel foil from a silicon wafer. The method includes forming a template of silicon by electrochemically etching a portion of the Si wafer to create a porous Si portion with pores of a desired depth. Then electrolessly plating nickel into the template, wherein the porous silicon portion is converted into a porous nickel portion and continuing the electroless plating until the internal tensile stress at an interface of the porous nickel portion and the silicon wafer is great enough to self-peel the porous nickel portion from the silicon wafer creating a nickel foil.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 19, 2006
    Applicant: University of California, Los Angeles
    Inventors: Xi Zhang, King-Ning Tu
  • Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
    Publication number: 20030148598
    Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.
    Type: Application
    Filed: November 19, 2002
    Publication date: August 7, 2003
    Inventors: King-Ning Tu, Ya-Hong Xie, Chang-Ching Yeh
  • Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
    Patent number: 7772117
    Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: August 10, 2010
    Assignee: The Regents of the University of California
    Inventors: King-Ning Tu, Ya-Hong Xie, Chang-Ching Yeh
  • Auxiliary prediction system for predicting reliability, and method and computer program product thereof
    Patent number: 11688054
    Abstract: An auxiliary prediction system is provided to predict reliability of an object after a specific operation is applied to the target object. The auxiliary prediction system includes an image correction module and an analysis module. The image correction module performs an image correction procedure to convert an original image of the target object into a first correction image. The analysis module performs a feature analysis on the first correction image through an artificial intelligence model that has been trained, so as to predict whether the target object has a defect or not after the specific operation.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 27, 2023
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: King-Ning Tu, Chih Chen, Yu-Chieh Lo, Nan-Yow Chen, Kai-Cheng Shie
  • Electrodeposited nano-twins copper layer and method of fabricating the same
    Patent number: 9476140
    Abstract: An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 25, 2016
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chih Chen, King-Ning Tu, Taochi Liu
  • Method of making copper alloys for chip and package interconnections
    Patent number: 6090710
    Abstract: A method of making Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin is disclosed for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: July 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Constantinou Andricacos, Hariklia Deligianni, James McKell Edwin Harper, Chao-Kun Hu, Dale Jonathan Pearson, Scott Kevin Reynolds, King-Ning Tu, Cyprian Emeka Uzoh
  • Electrodeposited nano-twins copper layer and method of fabricating the same
    Patent number: 10094033
    Abstract: An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 9, 2018
    Assignee: National Chiao Tung University
    Inventors: Chih Chen, King-Ning Tu, Taochi Liu
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