Abstract: A mechanism is provided for minimizing system power in a data processing system. A management control unit determines whether a convergence has been reached in the data processing system. If convergence fails to be reached, the management control unit determines whether a maximum fan flag is set to indicate that a fan is operating at a maximum speed. Responsive to the maximum fan flag failing to be set, a thermal threshold of the data processing system is either increased or decreased and thereby a fan speed of the data processing system is either increased or decreased based on whether the system power of the data processing system has either increased or decreased and based on whether a temperature of the data processing system has either increased or decreased. Thus, a new thermal threshold and a new fan speed are formed. The process is then repeated until convergence has been met.
Type:
Grant
Filed:
March 18, 2010
Date of Patent:
June 11, 2013
Assignee:
International Business Machines Corporation
Inventors:
John B. Carter, Elmootazbellah N. Elnozahy, Malcolm S. Ware, Wei Huang
Abstract: In one embodiment, an improved method for crawling a web site is provided. At least one page of the web site has a reference for executing by a browser to produce an address for a next page. The web site is crawled by the crawler program, which includes querying the web site server. The crawler parses such a reference from one of the web pages, and sends the reference to an applet running in the browser. The address for the next page is determined by the browser responsive to the reference. The address is then sent to the crawler. In an application of the improved crawler, the crawler is used for reducing dynamic data generation on the web site server. In this application, at least some of the web pages are dynamically generated responsive to the crawler queries. The server generated web pages are processed to generate corresponding processed versions of the web pages, so that the processed versions can be served in response to future queries, reducing dynamic generation of web pages by the server.
Type:
Application
Filed:
December 14, 2000
Publication date:
June 20, 2002
Applicant:
International Business Machines Corporation
Inventors:
Elizabeth Adleberg Brodsky, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony
Abstract: A method for providing remote access redirect in a host channel adapter of a system area network are provided. The method provides a mechanism by which a host channel adapter, in response to receiving a marker message, places selected channel(s) of the host channel adapter in a remote access redirect (RAR) mode of operation. During the RAR mode of operation, memory access messages received by the host channel adapter that are destined for portions of an application memory space marked as being protected are converted to RAR receive messages and redirected to a queue pair associated with an operating system rather than the queue pair for the application. The operating system is responsible for serializing access to application memory pages outside of the host channel adapter. The mechanisms of the present invention may be used to perform a checkpoint data integrity operation.
Type:
Grant
Filed:
January 13, 2005
Date of Patent:
March 24, 2009
Assignee:
International Business Machines Corporation
Inventors:
Elmootazbellah Nabil Elnozahy, Peter Anthony Walker
Abstract: A compiler for incorporating error detection into executable code generates conventional assembler language object code from a source code file. The compiler identifies an error detection segment (EDS) in the assembler code, where the EDS includes a subset of basic blocks in the assembler code. The compiler also identifies register and memory references in the EDS and inserts a set of instructions into the EDS. The inserted instructions record an entry state and an exit state of the referenced registers and memory locations. The state information is stored in a checkpoint portion of system memory. The compiler may generate shadow EDS code including instructions mirroring the instructions in the main EDS and verifying instructions that compare results produced by the mirroring instructions with results produced by the main EDS. The shadow EDS initiates an error recovery process if results produced by the shadow EDS and the main EDS differ.
Type:
Grant
Filed:
January 13, 2005
Date of Patent:
March 9, 2010
Assignee:
International Business Machines Corporation
Abstract: In one embodiment, an improved method for crawling a web site is provided. At least one page of the web site has a reference for executing by a browser to produce an address for a next page. The web site is crawled by the crawler program, which includes querying the web site server. The crawler parses such a reference from one of the web pages, and sends the reference to an applet running in the browser. The address for the next page is determined by the browser responsive to the reference. The address is then sent to the crawler. In an application of the improved crawler, the crawler is used for reducing dynamic data generation on the web site server. In this application, at least some of the web pages are dynamically generated responsive to the crawler queries. The server generated web pages are processed to generate corresponding processed versions of the web pages, so that the processed versions can be served in response to future queries, reducing dynamic generation of web pages by the server.
Type:
Grant
Filed:
December 14, 2000
Date of Patent:
May 28, 2013
Assignee:
International Business Machines Corporation
Inventors:
Elizabeth Adleberg Brodsky, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony
Abstract: A method for allocating memory in a data processing system in which a configuration table indicative of the system's physical memory is generated following a boot event. The configuration table is then modified to identify a portion of the system's physical memory thereby hiding the remaining portion from the operating system. Subsequently, a memory allocation request is initiated by an application program. A device driver invoked by the application program then maps physical memory from the hidden portion to the application's virtual address space to satisfy the application request. The application program may be executing on a first node of a multi-node system in which each node is associated with its own local memory, In this embodiment, the node on which the allocated physical memory is located may be derived from the allocation request thereby facilitating application level, allocation of specified portions of physical memory.
Type:
Grant
Filed:
August 17, 2000
Date of Patent:
March 2, 2004
Assignee:
International Business Machines Corporation
Abstract: A method and system for responding to a client request for information from a service device in a data processing network. Initially, the server receives the information request from the client and determines that the requested information is not in the server's cache. The server then generates a storage request and sends the storage request to a network attached storage device. The storage device retrieves the requested information and generates a set of packets containing the requested information. The storage device then sending the generated packets simultaneously to the client to satisfy the client request and to the server to refresh the server cache. The storage request may include protocol information corresponding to the client-server connection that the storage device uses to replicate the client-server protocol stack in the generated packet. Sending the generated packet may comprise including a multicast address in the packet.
Type:
Grant
Filed:
July 26, 2001
Date of Patent:
January 17, 2006
Assignee:
International Business Machines Corporation
Inventors:
Elmootazbellah Nabil Elnozahy, Michael David Kistler
Abstract: Cluster systems having central processor units (CPUs) with multiple processors (MPs) are configured as high density servers. Power density is managed within the cluster systems by assigning a utilization to persistent states and connections within the cluster systems. If a request to reduce overall power consumption within the cluster system is received, persistent states and connections are moved (migrated) within the multiple processors based on their utilization to balance power dissipation within the cluster systems. If persistent connections and states, that must be maintained have a low rate of reference, they may be maintained in processors that are set to a standby mode where memory states are maintained. In this way the requirement to maintain persistent connections and states does not interfere with an overall strategy of managing power within the cluster systems.
Type:
Grant
Filed:
October 31, 2001
Date of Patent:
January 10, 2006
Assignee:
International Business Machines Corporation
Inventors:
Patrick J. Bohrer, Elmootazbellah N. Elnozahy, Thomas W. Keller, Michael D. Kistler, Freeman L. Rawson, III
Abstract: A modular processing module allowing in-situ maintenance is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors, and a plurality of processing nodes. Each processing module side couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system and at least one heatsink that couples to at least a portion of the plurality of processing nodes on one of the processing module sides and is designed such that, when a set of heatsinks in the modular processing module are installed, an empty space is left in a center of the modular processing module.
Type:
Grant
Filed:
August 28, 2012
Date of Patent:
October 1, 2013
Assignee:
International Business Machines Corporation
Inventors:
Wael R. El-Essawy, Elmootazbellah N. Elnozahy, Madhusudan K. Iyengar, Thomas W. Keller, Jr., Juan C. Rubio
Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.
Type:
Application
Filed:
May 26, 2010
Publication date:
December 1, 2011
Applicant:
International Business Machines Corporation
Inventors:
Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, III, Malcolm S. Ware
Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.
Type:
Grant
Filed:
March 9, 2012
Date of Patent:
September 9, 2014
Assignee:
International Business Machines Corporation
Inventors:
Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, Malcolm S. Ware
Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.
Type:
Grant
Filed:
May 26, 2010
Date of Patent:
February 19, 2013
Assignee:
International Business Machines Corporation
Inventors:
Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, III, Malcolm S. Ware
Abstract: A modular processing module allowing in-situ maintenance is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors, and a plurality of processing nodes. Each processing module side couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system and at least one heatsink that couples to at least a portion of the plurality of processing nodes on one of the processing module sides and is designed such that, when a set of heatsinks in the modular processing module are installed, an empty space is left in a center of the modular processing module.
Type:
Grant
Filed:
May 27, 2010
Date of Patent:
October 2, 2012
Assignee:
International Business Machines Corporation
Inventors:
Wael R. El-Essawy, Elmootazbellah N. Elnozahy, Madhusudan K. Iyengar, Thomas W. Keller, Jr., Juan C. Rubio
Abstract: A performance monitor for a computer system that includes an interface, a filter module, and an address mapping module. The interface is suitable for coupling to an interconnect network of the computer system. The interconnect network links a local node of the system with at least one remote node of the system. The interface is configured to extract physical address information from a transaction traversing the interconnect network. The filter module associates the physical address with one of several memory blocks, where each memory block comprises a contiguous portion of the system's physical address space. The address mapping module associates the identified memory block with at least one range of virtual addresses associated with at least one of a plurality of concurrently executing programs and increments each of a set of access counters. The association between the selected memory block and the access counters is facilitated by a pointer field corresponding to the memory block.
Type:
Grant
Filed:
March 31, 1999
Date of Patent:
February 19, 2002
Assignee:
International Business Machines Corporation
Inventors:
Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, David Brian Glasco, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
Abstract: In the Distributed Computing Environment (DCE) standard, availability of directory services is increased by apparatus and methods using agents inserted between requesting clients and servers. By using agents, additional functions are carried out which are not performed in a typical DCE environment. Each agent inserts itself between the requesters and servers by writing over the pointer to the server with information pointing to the agent, thus redirecting requests to themselves. The agent then receives incoming requests and forwards them on to its associated server and other agents. The agent handling requests for the master server is called the "master" agent and the agents handling requests for replica servers are "replica" agents. The agents make sure requests are performed before replying to the original requester. Agents also monitor themselves. If a master agent crashes, the remaining agents elect a new master agent.
Type:
Grant
Filed:
June 20, 1997
Date of Patent:
January 11, 2000
Assignee:
Telcordia Technologies, Inc.
Inventors:
Elmootazbellah Nabil Elnozahy, Vivek Ratan, Mark Edward Segal
Abstract: A system and method for providing in-server caching of shared data involves a server program that defines a server cache in RAM of a server machine and stores a selected file in the server cache. If a cached file is modified through the file system interface of the operating system of the server machine, the operating system automatically issues an upcall to the server program, the upcall identifying the modified file. In response to receipt of the upcall, the server program removes the modified file from the server cache. In one embodiment, the server program responds to a client request requiring access to a requested file by obtaining the requested file from the server cache if the server cache contains that file. Otherwise, the server program calls the operating system to obtain the requested file and then adds that file to the server cache as a cached file. The server program then generates a result based on the requested file and transmits the result to the remote data processing system.
Type:
Grant
Filed:
December 10, 1999
Date of Patent:
August 27, 2002
Assignee:
International Business Machines Corporation
Inventors:
Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
Abstract: A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation lookaside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems.
Type:
Application
Filed:
November 13, 2003
Publication date:
May 19, 2005
Applicant:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Elmootazbellah Elnozahy, James Peterson, Ramakrishnan Rajamony, Hazim Shafi
Abstract: A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation look aside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems.
Type:
Application
Filed:
October 19, 2006
Publication date:
March 22, 2007
Inventors:
Elmootazbellah Elnozahy, James Peterson, Ramakrishnan Rajamony, Hazim Shafi
Abstract: A compression scheme for program executables that run in a reduced instruction set computer (RISC) architecture such as the PowerPC is disclosed. The method and system utilize scope-based compression for increasing the effectiveness of conventional compression with respect to register and literal encoding. First, discernible patterns are determined by exploiting instruction semantics and conventions that compilers adopt in register and literal usage. Additional conventions may also be set for register usage to facilitate compression. Using this information, separate scopes are created such that in each scope there is a more prevalent usage of a limited set of registers or literal value ranges, or there is an easily discernible pattern of register or literal usage. Each scope then is compressed separately by a conventional compressor.
Type:
Grant
Filed:
January 29, 1999
Date of Patent:
May 15, 2001
Assignee:
International Business Machines Corporation
Abstract: A method, apparatus and computer program product are disclosed to enable independent verification of service level agreement between two parties. In one embodiment, a first party contracts the hosting service of a second party to provide said first party with Web page and services on second party's equipment. Said contract contains a Service Level Agreement specifying performance parameters and guarantees for the response time experienced by users of said Web page and services. Independent verification by a third party of said agreement is done for a fee through several steps. In a first step, said third party inserts measuring and reporting instructions into blocks of information maintained on the server of said second party. The measuring instructions are for delivery to the client with the blocks of information. The delivery of the instructions occurs responsive to a request for the information by the client. Once they are delivered, the instructions are executed by the client.
Type:
Application
Filed:
December 14, 2000
Publication date:
June 20, 2002
Applicant:
International Business Machines Corporation