Abstract: Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface of the storage element, and a second electrode over a second surface of the storage element.

Abstract: For example, an Extremely High Throughput (EHT) wireless communication station (STA) may be configured to set a Resource Unit (RU) allocation subfield in an EHT Signal (SIG) field to indicate an RU assignment for an Orthogonal Frequency Division Multiple Access (OFDMA) EHT Physical layer (PHY) Protocol Data Unit (PPDU) according to a predefined RU allocation table, the RU assignment for the OFDMA EHT PPDU comprising a Multiple Resource Unit (MRU) comprising a plurality of RUs; and transmit the OFDMA EHT PPDU comprising the EHT SIG field.

Abstract: Various embodiments of the present disclosure may be used to determine how activation downlink control information (DCI), release DCI, and dynamic retransmission DCI are distinguished for DCI formats 3_0/3_1 for Mode-1 sidelink resource allocation. Furthermore, in case of asynchronous downlink (DL) and sidelink (SL) carriers, embodiments of the present disclosure may be used to determine how a user equipment (UE) determines transmission slots with respect to system frame number (SFN) or direct frame number (DFN) when activated with Type 1 configured scheduling.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to enhance and audio signal.

Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Abstract: An apparatus comprises an input register comprising a state register and a parity field, a first round secure hash algorithm (SHA) datapath communicatively coupled to the state register, comprising a first section to perform a ? step of a SHA calculation, a second section to perform a ? step and a ? step of the SHA calculation, a third section to perform a ? step of the SHA calculation and a fourth section to perform a ? step of the SHA calculation.

Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

Abstract: An embodiment of a latch apparatus for a circuit board comprises a first latch body with a retention mechanism for the circuit board, a second latch body with a coupling mechanism for a connector, and a spring mechanism mechanically coupled between the first latch body and the second latch body. Other embodiments are disclosed and claimed.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions using one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Abstract: Various embodiments herein provide techniques for minimum mean-square error interference rejection combining (MMSE-IRC) processing of a received signal, distributed between a baseband unit (BBU) and a remote radio unit (RRU). The RRU may perform a first phase of processing based on an extended channel that includes a channel of one or more user equipments (UEs) served by the RRU and interference samples that correspond to other cells or additive noise. The first phase may include scaling the interference samples by a scaling coefficient to obtain a modified extended channel, and performing maximum ratio combining (MRC) on the modified extended channel to obtain a processed signal. The RRU may send the processed signal to the BBU for the second phase of processing. The second phase of processing may include regularized zero forcing to remove interference. Other embodiments may be described and claimed.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.

Abstract: In one embodiment, an apparatus includes: a first queue to store requests that are guaranteed to be delivered to a persistent memory; a second queue to store requests that are not guaranteed to be delivered to the persistent memory; a control circuit to receive the requests and to direct the requests to the first queue or the second queue; and an egress circuit coupled to the first queue to deliver the requests stored in the first queue to the persistent memory even when a power failure occurs. Other embodiments are described and claimed.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

Abstract: Techniques are disclosed for using neural network architectures to estimate predictive uncertainty measures, which quantify how much trust should be placed in the deep neural network (DNN) results. The techniques include measuring reliable uncertainty scores for a neural network, which are widely used in perception and decision-making tasks in automated driving. The uncertainty measurements are made with respect to both model uncertainty and data uncertainty, and may implement Bayesian neural networks or other types of neural networks.

Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.

Abstract: Techniques, structures, and materials related to extreme ultraviolet (EUV) lithography are discussed. Multiple patterning inclusive of first patterning a grating of parallel lines and second patterning utilizing EUV lithography to form plugs in the grating, and optional trimming of the plugs may be employed. EUV resists, surface treatments, resist additives, and optional processing inclusive of plug healing, angled etch processing, electric field enhanced post exposure bake are described, which provide improved processing reliability, feature definition, and critical dimensions.

Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.

Abstract: Disclosed herein are non-planar transistor (e.g., nanoribbon) arrangements having asymmetric gate enclosures on at least one side. An example transistor arrangement includes a channel material shaped as a nanoribbon, and a gate stack wrapping around at least a portion of a first face of the nanoribbon, a sidewall, and a portion of a second face of the nanoribbon. Portions of the gate stack provided over the first and second faces of the nanoribbon extend in a direction parallel to the longitudinal axis of the nanoribbon for a certain distance that may be referred to as a “gate length.” A portion of the gate stack wrapping around the sidewall of the nanoribbon does not extend along the entire gate length, but, rather, extends over less than a half of the gate length, e.g., about one third of the gate length, thus making the gate enclosure on that sidewall asymmetric.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to allocate a first memory portion to a first application as a combination of a local memory and remote memory, wherein the remote memory is shared between multiple compute nodes, and manage a first memory balloon associated with the first memory portion based on two or more memory tiers associated with the local memory and the remote memory. Other embodiments are disclosed and claimed.

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract: Methods, systems, and storage media are described for the prioritization of services for control and data transmission for new radio (NR) systems. In particular, some embodiments may be directed to the prioritization of hybrid automatic repeat request-acknowledgment (HARQ-ACK) transmissions. Other embodiments may be described and/or claimed.

Abstract: In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.

Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.

Abstract: Various methods and devices for positioning autonomous agents including verifying a reported agent location using physical attributes of the received signal; improving agent formation for iterative localization; selecting agents for distributed task sharing; intelligent beacon-placement for group localization; relative heading and orientation determination utilizing time of flight; and secure Instrument Landing System (ILS) implementation for unmanned agents.

Abstract: An extension device is positioned within a point-to-point link to connect two devices, where the extension device includes error detection circuitry to detect a set of errors at the extension device. The extension device further includes memory to store an event register, where the extension device is to write data to the event register to describe detection of an error by the error detection circuitry. The extension device further includes a transmitter to transmit a notification signal to indicate the detection of the error and presence of the data in the event register associated with the error.

Abstract: An embodiment of an integrated circuit may comprise circuitry communicatively coupled to two or more sub-non-uniform memory access clusters (SNCs) to allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space. An embodiment of an apparatus may comprise decode circuitry to decode a single instruction, the single instruction to include a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to provide an indicated SNC memory allocation policy (e.g., a SNC policy hint). Other embodiments are disclosed and claimed.

Abstract: An apparatus of an edge computing node, a method, and a machine-readable storage medium. The apparatus is to decode messages from a plurality of clients within the edge computing network, the messages including respective coded data for respective ones of the plurality of clients; computing estimates of metrics related to a global model for federated learning using the coded data, the metrics including a gradient on the coded data; use the metrics to update the global model to generate an updated global model, wherein the edge computing node is to update the global model by calculating the gradient on the coded data based on a linear fit of the global model to estimated labels from the federated learning; and send a message including the updated global model for transmission to at least some of the clients.

Abstract: This disclosure describes systems, methods, and devices related to multi-link device (MLD) device resetup and transition. A device may perform an initial association with a first transition peer. The device may initiate a fast multi-link device (MLD) transition from the first transition peer to a second transition peer, wherein the MLD is configured to use authentication keys, and wherein at least one of the first transition peer or the second transition peer it is an access point (AP) MLD having a plurality of links associated with a plurality of APs within the AP MLD. The device may include an MLD link identification (ID) within a fast basic service set transition element (FTE) of a reassociation request or reassociation response frame, wherein the MLD link ID identifies an individual link of the plurality of links. The device may perform a second association with the second transition peer.

Abstract: In one embodiment, a method of training an autoencoder neural network includes determining autoencoder design parameters for the autoencoder neural network, including an input image size for an input image, a compression ratio for compression of the input image into a latent vector, and a latent vector size for the latent vector. The input image size is determined based on a resolution of training images and a size of target features to be detected. The compression ratio is determined based on entropy of the training images. The latent vector size is determined based on the compression ratio. The method further includes training the autoencoder neural network based on the autoencoder design parameters and the training dataset, and then saving the trained autoencoder neural network on a storage device.

Abstract: An apparatus to facilitate permissions at a computing system platform is disclosed. The apparatus includes a plurality of agents, each including a non-volatile memory storing firmware executed to perform a function associated with the agent and attestation hardware to detect an update at the computing system platform, generate a cryptographic key associated with each of the plurality of agents, perform an attestation with a relying party using the generated cryptographic keys and receive a tuple associated with each of the plurality of agents, wherein a tuple includes one or more permissions indicating platform resources an agent is permitted to access.

Abstract: Embodiments are generally directed to selective packing of patches for immersive video. An embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. The system is select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. The system is to encode the patches into one or more coded pictures according to the selection of the patches.

Abstract: An embodiment of an integrated circuit may comprise first circuitry to manage a memory in accordance with a page size and a channel interleave granularity, and second circuitry coupled to the first circuitry, the second circuitry to store data in a primary region of the memory at a primary address, and manage a mirror of the data in a secondary region of the memory at a secondary address at a regional granularity on demand at run time. Other embodiments are disclosed and claimed.

Abstract: Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory structure that is limitless in size.

Abstract: A device comprises a first comparator to generate a first clock signal based on a reference voltage and a first voltage at an output of a switched-capacitor power converter (SCPC), and a second comparator to generate a first control signal based on the first voltage and a threshold voltage. A sensor is to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal. A frequency divider circuit is to generate a second clock signal based on the first control signal and the second control signal, and in some embodiments, further based on one of the first clock signal or a third clock signal. Controller circuitry is to operate switch circuitry of the SCPC based on the first clock signal.

Abstract: A method, system, and article is directed to automatic content-dependent image processing algorithm selection.

Abstract: Computer computation of exact floating point addition is described. An example of an apparatus includes a first circuit to add first and second floating point inputs, including sorting the inputs to identify a larger input and a smaller input, adding bits in an upper portion of the smaller input to bits of the larger input, generating a high intermediate value based on the sum, and a generating a low intermediate value based on a lower portion of the lower input; and a second circuit to generate first and second outputs based on the high and low intermediate values, wherein the first output plus the second output exactly equals the first input plus the second input.

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a PPDU including a training field. For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station may be configured to determine one or more Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences in a frequency domain based on a count of one or more 2.16 Gigahertz (GHz) channels in a channel bandwidth for transmission of an EDMG PPDU including a TRN field; generate one or more OFDM TRN waveforms in a time domain based on the one or more OFDM TRN sequences, respectively, and based on an OFDM TRN mapping matrix, which is based on a count of the one or more transmit chains; and transmit an OFDM mode transmission of the EDMG PPDU over the channel bandwidth, the OFDM mode transmission comprising transmission of the TRN field based on the one or more OFDM TRN waveforms.

Abstract: A performance monitoring unit of a processor includes one or more performance monitoring counters, and a behavioral detector to sample data from a set of the one or more performance monitoring counters, analyze the sampled data, and identify a type of workload of a software process being executed by the processor.

Abstract: A method and system of image processing of omnidirectional images with a viewpoint shift.

Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

Abstract: Embodiments disclosed herein include temperature control systems. In an embodiment, a temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber, and where the fluid reservoir is between the vacuum source and the spray chamber.

Abstract: Methods, systems, and storage media are described for new radio downlink positioning reference signal (NR DL PRS) resource allocation and configuration. In particular, some embodiments relate to some embodiments relate to NR DL PRS resource configurations such as comb size, number of symbols, DL PRS resource time configuration (e.g., initial start time and periodicity), and providing formulas for calculation of seed for DL PRS sequence generation. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.

Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

Abstract: A method, system, and computer program product, the method comprising: obtaining a data path representing flow of data in processing a service request within a network computing environment having system resources; analyzing the data path to identify usage of the system resources required by the service request processing; determining, based on the usage of the system resources, an optimization action expected to improve the usage of the system resources; and implementing the optimization action in accordance with the data path, thereby modifying operation of the cloud computing environment in handling future service requests.