Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include an interposer having a surface, wherein a material of the interposer includes glass and the interposer includes through-glass vias (TGVs); a photonic integrated circuit (PIC) optically coupled to the surface of the interposer by optical glue or fusion bonding and electrically coupled to the TGVs in the interposer by hybrid bond interconnects; and an optical component optically coupled to the interposer, wherein the optical component is optically coupled to the PIC by an optical pathway through the interposer.

Abstract: For example, a Bluetooth (BT) device may be capable of configuring a BT link for communication between the BT device and a keyboard device. For example, the BT device may be configured to identify a keypress attribute of keypresses on the keyboard device. For example, the BT device may be configured to identify the keypress attribute based on transmissions from the keyboard device to the BT device over the BT link between the BT device and the keyboard device. For example, the BT device may configure a bandwidth (BW) allocation for the BT link, for example, based on the keypress attribute.

Abstract: Various systems and methods for bus-off attack detection are described herein. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.

Abstract: Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a core made of glass and having a surface, the core further including a first region having a first concentration of ions and a second region having a second concentration of ions at the surface of the core; and a third region having a third concentration of ions, wherein the second region is between the third region and the surface of the core, and wherein the third concentration of ions is less than the first and second concentrations of ions; a dielectric with a conductive pathway at the surface of the core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.

Abstract: A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is along a perimeter of the core; and a second optical component coupled to the first optical component, wherein the second optical component is optically coupled to the PIC by an optical pathway through the first optical component.

Abstract: An integrated circuit (IC) package substrate including a glass core having a cavity filter structure, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include a core made of glass, and the core including a first core portion having a first surface and a trench and a ridge in the first surface, the trench and the ridge lined with a conductive material; and a second core portion having a second surface, the second surface lined with the conductive material, wherein the first surface of the first core portion is physically coupled to the second surface of the second core portion forming a cavity filter structure.

Abstract: Signal lines in the pin field of a printed circuit board layout are modified to reduce line impedance and improve signal integrity. The widths of signal lines are extended in the pin field to take full advantage of the available routing space between pads and adjacent signal lines. The signal line extension can be considered a subtractive approach in that the signal lines are extended to occupy the available muting space, with signal line extensions that would otherwise cause design rule violations being subtracted out. The edge of a signal line is extended to a keep-out region associated with a centerline that extends through a plurality of pads arranged in a line and located adjacent to the signal line. The edge of the signal line is also extended to keep-out regions associated with pads in the pin fields.

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a glass core having a surface, a first region having a first concentration of ions extending from the surface of the core to a first depth; a second region having a second concentration of ions greater than the first concentration of ions, the second region between the first region and the surface of the core; a dielectric with a conductive pathway at the surface of the glass core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.

Abstract: A PIC first patch architecture includes a solderless electrical connection at a die interconnect surface. Redistribution layers (RDLs) are patterned onto a face of an integrated circuit (IC) die and photonic integrated circuit (PIC) die prior to placement of the RDLs into a cavity in a glass layer. Optical interconnections for the PIC die are protected during RDL patterning and optical waveguides may be patterned into the glass layer fore or after assembling the PIC first patch including the RDL and glass layer.

Abstract: A processor may aggregate cache misses in a cache, the cache shared by a plurality of input/output (I/O) sources. The processor may aggregate cache occupancy in the cache by the plurality of VO sources. The processor may and identify, based on the aggregating, a first I/O source of the plurality of I/O sources as impacting the cache.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is coupled to the surface of the core by optical glue or by fusion bonding; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the PIC by an optical pathway through the core and the first optical component.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a glass core with a surface and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways and an interconnect die; a processor integrated circuit (XPU) and a photonic integrated circuit (PIC), having an active surface facing towards the core, electrically coupled to the interconnect die and to the conductive pathways; a first optical component optically coupled to the active surface of the PIC and to the surface of the core; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the PIC by an optical pathway through the first optical component and the core.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a glass core with a surface and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) having an active surface, wherein the PIC is coupled to the surface of the core with the active surface facing away from the core; a processor integrated circuit (XPU) electrically coupled to the conductive pathways in the dielectric material and to the active surface of the PIC; a first optical component optically coupled to a lateral surface of the PIC and to the surface of the core; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the PIC by an optical pathway through the first optical component and the core.

Abstract: An apparatus includes a circuit to generate a clock having a period with a duty cycle less than or equal to 90%, and logic to determine a difference in an input voltage between a first time and a second time, at least in part based on the duty cycle of the clock, and to produce a first signal, at least in part based on the difference in the input voltage and a first predetermined threshold.

Abstract: An apparatus to facilitate matrix transposition in matrix multiplication array circuitry is disclosed. The apparatus includes a processor comprising matrix acceleration hardware comprising storage buffers and an array of data processing units (DPUs), wherein the matrix acceleration hardware is to: load data for a source matrix to the storage buffers; generate a transposed matrix corresponding comprising transposed elements of the source matrix; and input the transposed matrix to the array of DPUs for a matrix multiplication operation.

Abstract: An apparatus to facilitate enhancements for accumulator usage and instruction forwarding in matrix multiply pipeline in graphics environment is disclosed. The apparatus includes matrix acceleration hardware comprising a plurality of data processing units, wherein the respective plurality of data processing units comprise: multiply-accumulate hardware to generate intermediate results of a matrix multiplication operation; intermediate accumulation hardware to store the intermediate results of the matrix multiplication operation and accumulate with other intermediate results generated by the multiply-accumulate hardware; a bypass data structure to cause a source operand to bypass the multiply-accumulate hardware; and an adder circuit to add an output from the multiply-accumulate hardware with at least one of the source operand or an output of the intermediate accumulation hardware to generate a final output.

Abstract: An apparatus to facilitate supporting and load balancing multiple double precision pipelines in a graphics environment is disclosed. The apparatus includes a processing core having at least one processing resource comprising: a first double precision (DP) pipeline to support double float operations, the first DP pipeline comprising a first set of floating point units (FPUs) configured in a pipelined configuration to enable new instructions to be issued to the first DP pipeline before previous instructions are complete; and a second DP pipeline to support the double float operations, wherein the second DP pipeline comprising a second set of FPUs configured in a pipelined configuration to enable new instructions to be issued to the first DP pipeline before previous instructions are complete.

Abstract: Apparatuses including general-purpose graphics processing units and graphics multiprocessors that exploit queues or transitional buffers for improved low-latency high-bandwidth on-die data retrieval are disclosed. In one embodiment, a graphics multiprocessor includes at least one compute engine to provide a request, a queue or transitional buffer, and logic coupled to the queue or transitional buffer. The logic is configured to cause a request to be transferred to a queue or transitional buffer for temporary storage without processing the request and to determine whether the queue or transitional buffer has a predetermined amount of storage capacity.

Abstract: The technology disclosed herein includes broadcasting, to a plurality of destination computing systems, a request to live migrate at least one trusted execution environment virtual machine (TVM) to at least one of the plurality of destination computing systems, receiving one or more bids from at least one of the plurality of destination computing systems, allocating the at least one TVM to at least one of the plurality of destination computing systems based at least on a bidding price in the one or more bids, automatically live migrating the at least one TVM to the at least one of the plurality of destination computing systems based on the allocating, and storing live migration allocation information of the at least one TVM on a first blockchain.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine version information for a new firmware component, read dependency information corresponding to the firmware component, and determine if dependency is satisfied between the new firmware component and one or more other firmware components based on the version information and the dependency information of the new firmware component. Other embodiments are disclosed and claimed.

Abstract: Protecting data privacy in a federated learning computing environment includes receiving a model trained by a federated server with public data using global model parameters, getting local shareable data from a local shareable database, training the model with the local shareable data using the global model parameters to generate local model parameters, and obscuring the local model parameters. Protecting data privacy includes sending the local model parameters to the federated server, modifying the model to classify private data, and training the model with the private data using the local model parameters and updating the local model parameters.

Abstract: Embodiments described herein are generally directed to improving performance of a transactional API protocol by adaptively optimizing function call performance at runtime. In an example, a command stream is monitored that includes function calls associated with the transactional API to be carried out by an executer on behalf of an application. An amount of data transmitted over an interconnect between the application and the executer is reduced by: (i) identifying a sequence of multiple of the function calls that represents a batch and satisfies a set of one or more criteria; (ii) creating a template of the batch having a symbolic name and including placeholders for a subset of variable arguments of the multiple of the function calls; and (ii) after observing a subsequent occurrence of the sequence within the command stream, transmitting via the interconnect the symbolic name and values for the subset of variable arguments.

Abstract: An apparatus to facilitate cross-thread register sharing for matrix multiplication compute is disclosed. The apparatus includes matrix acceleration hardware comprising a plurality of data processing units, wherein the respective plurality of data processing units are to: receive a decoded instruction for a first thread having a first register space, wherein the decoded instruction is for a matrix multiplication operation and comprises an indication to utilize a second register space of a second thread for an operand of the decoded instruction for the first thread; access the second register space of the second thread to obtain data for the operand of the decoded instruction; and perform the matrix multiplication operation for the first thread using the data for the operand from the second register space of the second thread.

Abstract: An example of an apparatus may include matrix operation hardware and circuitry coupled to the matrix operation hardware to detect a hardware fault in the matrix operation hardware based at least in part on one or more hardware checksums of data in one or more matrices of the matrix operation hardware. Other embodiments are disclosed and claimed.

Abstract: An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.

Abstract: Integrated circuitry comprising an interconnect level with multi-height lines contacted by complementary multi-height vias. In some examples, a first line of a taller height is contacted by a first via of a shorter height while a second line of a shorter height is contacted by a second via of a taller height. The first and second vias and first and second lines may be subtractively defined concurrently from a same stack of conductive material layers such that the first via comprises a first conductive material layer, and the first line comprises second and third conductive material layers while the second via comprises the first and second conductive material layers and the second line comprises the third conductive material layer.

Abstract: Architectures and processes for redistribution layers in a dielectric cavity to enable an embedded component in semiconductor packaging. The architectures pattern redistribution layers (RDL) over a thick seed and remove dielectric material from the RDL conductive contacts to create the dielectric cavity. The architectures enable 2-sided connections for embedded components in the dielectric cavity with minimal disruption to existing process infrastructure. Such an approach can be used not only for integration of photonic devices, but also for any semiconductor packaging requiring dual sided connection within a dielectric cavity.

Abstract: A system and method of implementing digitally signed secure quick response (SQR) codes include storing captured content as a hash map, calculating a hash of the captured content, where the hash is a unique key that is stored in the hash map, creating a digital signature for the captured content using a private key such that the captured content is digitally signed, generating a SQR code of the digitally signed captured content, and storing the SQR code including the digitally signed captured content in a secure digital (SD) card.

Abstract: Homomorphic encryption (HE) acceleration circuitry includes encode circuitry to encode cleartext data into plaintext data, encrypt circuitry to encrypt the plaintext data into HE ciphertext data according to an HE process, decrypt circuitry to decrypt the HE ciphertext data into the plaintext data according to the HE process, and decode circuitry to decode the plaintext data into the cleartext data.

Abstract: Techniques include an apparatus to retrieve a first parameter for the IDS to monitor a device for a time-synchronized network. The first parameter may represent a number of messages the IDS needs to analyze in order to detect a security attack. The messages may comprise time information to synchronize a clock for a device to a network time for a time-synchronized network. The processor circuitry may retrieve a second parameter for a time sensitive application. The second parameter may represent a defined amount of time error tolerated by the time sensitive application, and determine a third parameter for the IDS based on the first and second parameters. The third parameter may represent a defined frequency to receive a number of messages with time information in order to detect the security attack on the device within a defined time interval. Other embodiments are described and claimed.

Abstract: An apparatus includes a central processing unit (CPU), including a plurality of processing cores, each having a cache memory, a fabric interconnect coupled to the plurality of processing cores and cryptographic circuitry, coupled to the fabric interconnect including mesh stop station to receive memory data and determine a destination of the memory data and encryption circuitry to encrypt/decrypt the memory data based on a destination of the memory data.

Abstract: Disclosed herein are tools and methods for subtractively patterning metals. These tools and methods may permit the subtractive patterning of metal (e.g., copper, platinum, etc.) at pitches lower than those achievable by conventional etch tools and/or with aspect ratios greater than those achievable by conventional etch tools. The tools and methods disclosed herein may be cost-effective and appropriate for high-volume manufacturing, in contrast to conventional etch tools.

Abstract: A bumpless hybrid organic glass interposer. One or more high density pattern (HDP) routing layers are placed on a functional, thin, carrier, separate from the intended organic substrate patch or package. The HDP layer(s) is/are then attached to the substrate package. The interposers achieve electrical connections between the HDP layer and underlying routing layer of the substrate package by utilizing a self-align dry etch process through landing pads connected to the HDP routing.

Abstract: A method and system of image processing with multi-skeleton tracking uses a temporal object key point loss metric.

Abstract: A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

Abstract: One embodiment provides for a computer-readable medium storing instructions that cause one or more processors to perform operations comprising determining a per-layer scale factor to apply to tensor data associated with layers of a neural network model and converting the tensor data to converted tensor data. The tensor data may be converted from a floating point datatype to a second datatype that is an 8-bit datatype. The instructions further cause the one or more processors to generate an output tensor based on the converted tensor data and the per-layer scale factor.

Abstract: A non-linear activation function may be approximated by linear functions. The input range of the activation function may be divided into input segments. One or more input segments may be selected based on statistical analysis of input data elements in the input range. A parameter of a first linear function that approximates the activation function for at least part of a selected input segment may be stored in a first portion of a first look-up table (LUT). The first portion of the first LUT is dedicated to a first group of post processing engines (PPEs). A parameter of a second linear function that approximates the activation function for at least part of an unselected input segment may be stored in a shared pool of LUT entries, which includes a second portion of the first LUT and a portion of a second LUT and is shared by multiple groups of PPEs.

Abstract: Computer computation of correctly rounded floating point summation is described. An example of apparatus includes a first circuit to sort multiple floating point (FP) values based on an exponent of each FP value and store the sorted FP values in a buffer, and to provide the plurality of FP values for summation sequentially in a sorted order starting with a FP value having a smallest exponent; a second circuit to iteratively sum the FP values and store an accumulated value, generate and store a residual value representing fully resolved bits from the accumulator, and generate an intermediate output including the residual value; and a third circuit to perform final rounding of the output, the final rounded output being a correctly rounded summation of the maximum floating point values.

Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.

Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.

Abstract: Embodiments of a microelectronic assembly includes: an interposer comprising a first portion in contact along an interface with a second portion; a first integrated circuit (IC) die embedded in a dielectric material in the first portion of the interposer; and a second IC die coupled to the first portion of the interposer opposite to the second portion, wherein: the second portion comprises a glass substrate with a channel within the glass substrate, a portion of the channel has an opening at the interface, a conductive pad in the first portion is exposed in the opening, and the conductive pad is coupled to a circuit in at least one of the first IC die or the second IC die.

Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: an array of channel regions, including a first channel region and an adjacent second channel region; a first source/drain region proximate to the first channel region; a second source/drain region proximate to the second channel region; and an insulating material region at least partially between the first source/drain region and the second source/drain region.

Abstract: An apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. The apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources; a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources; and a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources.

Abstract: Embodiments of a package substrate includes: a conductive via in a first layer, the first layer comprising a positive-type photo-imageable dielectric; a conductive trace in a second layer, the second layer comprising a negative-type photo-imageable dielectric; and an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers. The conductive via is directly attached to the conductive trace through the insulative material, the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation.

Abstract: Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.

Abstract: A computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (IPU), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of micro service s cluster.

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

Abstract: Described herein is a truncated modified Booth squarer that is commutative and accurate to 1 unit in the last place. In various embodiments, the truncated Booth squarer is a radix-4 Booth squarer or a radix-8 Booth squarer. The truncated Booth squarer can be included within integer, floating-point, or fixed-point units within a graphics processor or compute accelerator, including matrix accelerator units or tensor processors.