Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Abstract: Various embodiments of the present disclosure may be used to determine how activation downlink control information (DCI), release DCI, and dynamic retransmission DCI are distinguished for DCI formats 3_0/3_1 for Mode-1 sidelink resource allocation. Furthermore, in case of asynchronous downlink (DL) and sidelink (SL) carriers, embodiments of the present disclosure may be used to determine how a user equipment (UE) determines transmission slots with respect to system frame number (SFN) or direct frame number (DFN) when activated with Type 1 configured scheduling.

Abstract: An embodiment of a latch apparatus for a circuit board comprises a first latch body with a retention mechanism for the circuit board, a second latch body with a coupling mechanism for a connector, and a spring mechanism mechanically coupled between the first latch body and the second latch body. Other embodiments are disclosed and claimed.

Abstract: An apparatus comprises an input register comprising a state register and a parity field, a first round secure hash algorithm (SHA) datapath communicatively coupled to the state register, comprising a first section to perform a ? step of a SHA calculation, a second section to perform a ? step and a ? step of the SHA calculation, a third section to perform a ? step of the SHA calculation and a fourth section to perform a ? step of the SHA calculation.

Abstract: Methods, systems, and storage media are described for the prioritization of services for control and data transmission for new radio (NR) systems. In particular, some embodiments may be directed to the prioritization of hybrid automatic repeat request-acknowledgment (HARQ-ACK) transmissions. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface of the storage element, and a second electrode over a second surface of the storage element.

Abstract: Various embodiments herein provide techniques for minimum mean-square error interference rejection combining (MMSE-IRC) processing of a received signal, distributed between a baseband unit (BBU) and a remote radio unit (RRU). The RRU may perform a first phase of processing based on an extended channel that includes a channel of one or more user equipments (UEs) served by the RRU and interference samples that correspond to other cells or additive noise. The first phase may include scaling the interference samples by a scaling coefficient to obtain a modified extended channel, and performing maximum ratio combining (MRC) on the modified extended channel to obtain a processed signal. The RRU may send the processed signal to the BBU for the second phase of processing. The second phase of processing may include regularized zero forcing to remove interference. Other embodiments may be described and claimed.

Abstract: An extension device is positioned within a point-to-point link to connect two devices, where the extension device includes error detection circuitry to detect a set of errors at the extension device. The extension device further includes memory to store an event register, where the extension device is to write data to the event register to describe detection of an error by the error detection circuitry. The extension device further includes a transmitter to transmit a notification signal to indicate the detection of the error and presence of the data in the event register associated with the error.

Abstract: An embodiment of an integrated circuit may comprise circuitry communicatively coupled to two or more sub-non-uniform memory access clusters (SNCs) to allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space. An embodiment of an apparatus may comprise decode circuitry to decode a single instruction, the single instruction to include a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to provide an indicated SNC memory allocation policy (e.g., a SNC policy hint). Other embodiments are disclosed and claimed.

Abstract: This disclosure describes systems, methods, and devices related to multi-link device (MLD) device resetup and transition. A device may perform an initial association with a first transition peer. The device may initiate a fast multi-link device (MLD) transition from the first transition peer to a second transition peer, wherein the MLD is configured to use authentication keys, and wherein at least one of the first transition peer or the second transition peer it is an access point (AP) MLD having a plurality of links associated with a plurality of APs within the AP MLD. The device may include an MLD link identification (ID) within a fast basic service set transition element (FTE) of a reassociation request or reassociation response frame, wherein the MLD link ID identifies an individual link of the plurality of links. The device may perform a second association with the second transition peer.

Abstract: In one embodiment, a method of training an autoencoder neural network includes determining autoencoder design parameters for the autoencoder neural network, including an input image size for an input image, a compression ratio for compression of the input image into a latent vector, and a latent vector size for the latent vector. The input image size is determined based on a resolution of training images and a size of target features to be detected. The compression ratio is determined based on entropy of the training images. The latent vector size is determined based on the compression ratio. The method further includes training the autoencoder neural network based on the autoencoder design parameters and the training dataset, and then saving the trained autoencoder neural network on a storage device.

Abstract: An apparatus to facilitate permissions at a computing system platform is disclosed. The apparatus includes a plurality of agents, each including a non-volatile memory storing firmware executed to perform a function associated with the agent and attestation hardware to detect an update at the computing system platform, generate a cryptographic key associated with each of the plurality of agents, perform an attestation with a relying party using the generated cryptographic keys and receive a tuple associated with each of the plurality of agents, wherein a tuple includes one or more permissions indicating platform resources an agent is permitted to access.

Abstract: An apparatus of an edge computing node, a method, and a machine-readable storage medium. The apparatus is to decode messages from a plurality of clients within the edge computing network, the messages including respective coded data for respective ones of the plurality of clients; computing estimates of metrics related to a global model for federated learning using the coded data, the metrics including a gradient on the coded data; use the metrics to update the global model to generate an updated global model, wherein the edge computing node is to update the global model by calculating the gradient on the coded data based on a linear fit of the global model to estimated labels from the federated learning; and send a message including the updated global model for transmission to at least some of the clients.

Abstract: An embodiment of an integrated circuit may comprise first circuitry to manage a memory in accordance with a page size and a channel interleave granularity, and second circuitry coupled to the first circuitry, the second circuitry to store data in a primary region of the memory at a primary address, and manage a mirror of the data in a secondary region of the memory at a secondary address at a regional granularity on demand at run time. Other embodiments are disclosed and claimed.

Abstract: A device comprises a first comparator to generate a first clock signal based on a reference voltage and a first voltage at an output of a switched-capacitor power converter (SCPC), and a second comparator to generate a first control signal based on the first voltage and a threshold voltage. A sensor is to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal. A frequency divider circuit is to generate a second clock signal based on the first control signal and the second control signal, and in some embodiments, further based on one of the first clock signal or a third clock signal. Controller circuitry is to operate switch circuitry of the SCPC based on the first clock signal.

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a PPDU including a training field. For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station may be configured to determine one or more Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences in a frequency domain based on a count of one or more 2.16 Gigahertz (GHz) channels in a channel bandwidth for transmission of an EDMG PPDU including a TRN field; generate one or more OFDM TRN waveforms in a time domain based on the one or more OFDM TRN sequences, respectively, and based on an OFDM TRN mapping matrix, which is based on a count of the one or more transmit chains; and transmit an OFDM mode transmission of the EDMG PPDU over the channel bandwidth, the OFDM mode transmission comprising transmission of the TRN field based on the one or more OFDM TRN waveforms.

Abstract: Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory structure that is limitless in size.

Abstract: Computer computation of exact floating point addition is described. An example of an apparatus includes a first circuit to add first and second floating point inputs, including sorting the inputs to identify a larger input and a smaller input, adding bits in an upper portion of the smaller input to bits of the larger input, generating a high intermediate value based on the sum, and a generating a low intermediate value based on a lower portion of the lower input; and a second circuit to generate first and second outputs based on the high and low intermediate values, wherein the first output plus the second output exactly equals the first input plus the second input.

Abstract: A method, system, and article is directed to automatic content-dependent image processing algorithm selection.

Abstract: Embodiments are generally directed to selective packing of patches for immersive video. An embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. The system is select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. The system is to encode the patches into one or more coded pictures according to the selection of the patches.

Abstract: A long-term object tracker employs a continuous learning framework to overcome drift in the tracking position of a tracked object. The continuous learning framework consists of a continuous learning module that accumulates samples of the tracked object to improve the accuracy of object tracking over extended periods of time. The continuous learning module can include a sample pre-processor to refine a location of a candidate object found during object tracking, and a cropper to crop a portion of a frame containing a tracked object as a sample and to insert the sample into a continuous learning database to support future tracking.

Abstract: A method and system of image processing of omnidirectional images with a viewpoint shift.

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.

Abstract: Disclosed embodiments are related to distinguishing between listen-before talk (LBT) failure and LBT success, reducing the effect of invalid out-of-sync (OOS) indications and preventing false declaration of radio link failures (RLFs). Other embodiments may be described and/or claimed.

Abstract: Disclosed herein are methods for manufacturing IC components using bottom-up fill of openings with a dielectric material. In one aspect, an exemplary method includes, first, depositing a solid dielectric liner on the inner surfaces of the openings using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process. Such a combination method may maximize the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks. Assemblies and devices manufactured using such methods are disclosed as well.

Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.

Abstract: A method, system, and computer program product, the method comprising: obtaining a data path representing flow of data in processing a service request within a network computing environment having system resources; analyzing the data path to identify usage of the system resources required by the service request processing; determining, based on the usage of the system resources, an optimization action expected to improve the usage of the system resources; and implementing the optimization action in accordance with the data path, thereby modifying operation of the cloud computing environment in handling future service requests.

Abstract: Methods, systems, and storage media are described for new radio downlink positioning reference signal (NR DL PRS) resource allocation and configuration. In particular, some embodiments relate to some embodiments relate to NR DL PRS resource configurations such as comb size, number of symbols, DL PRS resource time configuration (e.g., initial start time and periodicity), and providing formulas for calculation of seed for DL PRS sequence generation. Other embodiments may be described and/or claimed.

Abstract: Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.

Abstract: Systems and methods of re-configuring PCI values for a NR cell and performing mobility robustness optimization are described. To reconfigure the PCI values. The NRM data and the PCI of candidate cells measurements are analyzed to detect a potential PCI collision or PCI confusion among NR cells. In response to detection of the potential PCI collision or confusion, a new PCI value for at least one NR cell is determined and instructions to re-configure the at least one NR cell with the new PCI value are sent to a producer of provisioning MnS. For MRO, a NF provisioning MnS with modifyMOIAttributes operation to configure MRO targets for an MRO function and to enable the MRO function for a NR cell are consumed, as is a performance assurance MnS with a notifyFileReady or reportStreamData operation to collect MRO-related performance measurements. The measurements are analyzed to evaluate MRO performance.

Abstract: A performance monitoring unit of a processor includes one or more performance monitoring counters, and a behavioral detector to sample data from a set of the one or more performance monitoring counters, analyze the sampled data, and identify a type of workload of a software process being executed by the processor.

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

Abstract: Embodiments disclosed herein include temperature control systems. In an embodiment, a temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber, and where the fluid reservoir is between the vacuum source and the spray chamber.

Abstract: For example, an apparatus may be configured to generate, transmit, receive and/or process a frame including a multiple Basic Service Set Identifier (BSSID) element corresponding to a multiple BSSID set including a reporting AP, the BSSID element including one or more non-transmitted BSSID profile elements corresponding to one or more other APs belonging to the multiple BSSID set, wherein a non-transmitted BSSID profile element corresponding to an other AP includes one or more elements of information corresponding to the other AP, and a multi-link element, the multi-link element including one or more profile subelements for one or more reported APs of an other MLD including the other AP, respectively, wherein a profile subelement corresponding to a reported AP includes one or more elements of information corresponding to the reported AP.

Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that implement an automatically evolving code recommendation engine. In one example, the apparatus collects a user code snippet. The apparatus then determines a structured representation of the user code snippet. Next, the apparatus generates a recommended code snippet using the structured representation of the user code snippet. Then the apparatus obtains user-determined code snippet feedback comparing the user code snippet to the recommended code snippet, the user-determined code snippet feedback indicating one of a match, no match, or uncertain. Finally, the apparatus stores a code snippet training pair in a training database, the code snippet training pair including the user code snippet and the recommended code snippet.

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon guardianship are disclosed.

Abstract: An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Abstract: Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

Abstract: Embodiments are directed to immutable watermarking for authenticating and verifying artificial intelligence (AI)-generated output. An embodiment of a system includes a processor of a monitoring system, wherein the processor is to: receive first content from an edge device and second content from an adversary system, wherein the first content comprises output of a machine learning (ML) model as applied to captured content at the edge device; receive a digital signature corresponding to the first content; process the digital signature to extract a global unique identifier (GUID) of the ML model that generated the first content; verify the extracted GUID against data obtained from a shared registry; in response to successfully verifying the extracted GUID, provide the first content for consumption at a monitoring consumption application; and in response to determining that the second content is not associated with a verifiable GUID, refuse the second content at the monitoring consumption application.

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

Abstract: Various embodiments herein include techniques to indicate a reference subcarrier spacing (SCS) in a soft resource availability configuration for an integrated access and backhaul (IAB) distributed unit (DU)/mobile terminal (MT). For example, the reference SCS may be included in soft resource availability radio resource control (RRC) configuration AvailabilityCombinationsPerCell. Additionally, embodiments include mechanisms for dynamic soft availability indication with paired spectrum operation (e.g., frequency division duplex (FDD) operation). Other embodiments may be described and claimed.

Abstract: Digital holographic microscopy and related image processing techniques are described. A hologram captured in an image frame is split into different depths while a new hologram is being captured. Image slices of the hologram are determined and using free space impulse responses that are pre-calculated at a different precision than processing operations using the holographic data. Each computation is calculated in parallel based on the number of available processing cores and threads. The image slices are combined into a 2D array or 3D array to permit further processing of the combined array to count and size particles in the image frame. The reconstructed hologram is displayed at a subsequent image frame than that used to capture the hologram.

Abstract: An apparatus includes a non-planar semiconductor body; and a contact for the semiconductor body. The contact includes an epitaxial material that is formed on and contacts the semiconductor body. The contact includes a second material that is formed on and contacts the epitaxial material; and the second material at least partially conforms to an undercut of the epitaxial material.

Abstract: A disclosed example includes a plurality of display pixels; timing controller circuitry; driver circuitry on a same integrated circuit as the timing controller circuitry, the driver circuitry to drive the display pixels; and de-multiplexer circuitry to de-multiplex pixel data to send to the plurality of display pixels.

Abstract: Systems and techniques for information centric network (ICN) interworking are described herein. For example, a request may be received at a convergence layer of a node. Here, the request originates from an application on the node. A network protocol, from several available to the node, may be determined to transmit the request. The node then transmits the request via the selected network protocol.