Abstract: A method performed by an electronic apparatus, includes: determining a local frame sequence from a video; obtaining a feature map sequence of the local frame sequence by encoding the local frame sequence; determining a feature flow sequence of the local frame sequence based on the feature map sequence of the local frame sequence and a mask image sequence regarding an object to be removed, the mask image sequence being corresponding to the feature map sequence; obtaining an updated feature map sequence of the local frame sequence, by performing, based on the feature flow sequence, feature fusion between adjacent feature maps in the feature map sequence; and obtaining a processed local frame sequence, by decoding the updated feature map sequence of the local frame sequence.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.

Abstract: In an embodiment of the present disclosure, among a plurality of crystal grains included in first electrode layers, crystal grains disposed on an end of the dielectric layer in the second direction and in contact with the second electrode layers are defined as first crystal grains and crystal grains disposed on ends of the internal electrodes in the second direction and in contact with the second electrode layers are defined as second crystal grains, and a growth direction of the first crystal grains and a growth direction of the second crystal grains may be adjusted, so that bonding force between the first electrode layers and the body may be improved.

Abstract: A multilayer ceramic capacitor includes a body including a capacitance region in which at least one first internal electrode and at least one second internal electrode are alternately stacked in a first direction with at least one dielectric layer interposed therebetween; and first and second external electrodes disposed on the body to be spaced apart from each other with the capacitance region interposed therebetween in a second direction, different from the first direction, and respectively connected to the at least one first internal electrode and the at least one second internal electrode, wherein the body further includes a plurality of margin regions disposed with the capacitance region interposed therebetween in a third direction, different from the first and second directions, wherein each of the plurality of margin regions includes a second margin region and a first margin region disposed between the second margin region and the capacitance region, and wherein a size of a crystal grain in the second

Abstract: A coil component includes: a body having a first surface and a second surface opposing each other; a support member disposed in the body, and having one surface and the other surface opposing each other; a coil including first and second coil portions disposed on the one surface and the other surface of the support member and having at least one turn, respectively, and a via connecting the first and second coil portions; and first and second external electrodes respectively disposed on the first and second surfaces of the body and connected to the coil, wherein the via includes an upper surface in contact with the first coil portion and a lower surface in contact with the second coil portion, and a ratio VDU/VDL of a diameter VDU of the upper surface to a diameter VDL of the lower surface is 1.06 or more and 1.64 or less.

Abstract: A method performed by one or more processors includes: obtaining an original intensity map including original elements having respective signal intensities with respect to a road surface, the signal intensities based on sensing of a vision sensor arranged on a moving object that is moving on a road including the road surface, wherein each of the original elements has a respective local neighborhood of neighboring original elements; generating a local intensity map by determining local values respectively corresponding to the original elements of the original intensity map, wherein the local values are determined based on the original elements in the respectively corresponding local neighborhoods; generating a normalized intensity map by normalizing the original intensity map based on the local intensity map; and recognizing the road surface based on the normalized intensity map.

Abstract: A coil component includes a body, a support member disposed within the body, a first coil disposed on one surface of the support member, a second coil disposed on the other surface of the support member, a first pad connected to one end of the first coil, a second pad connected to one end of the second coil, a plurality of conductive vias connecting the first pad and the second pad, a first external electrode disposed on the body and connected to the other end of the first coil, and a second external electrode disposed on the body and connected to the other end of the second coil.

Abstract: An apparatus includes a static random access memory (SRAM) cell including a first inverter and a second inverter, and a third inverter including a first inverter transistor and a second inverter transistor. An output terminal of the first inverter is connected to a source terminal of the second inverter transistor.

Abstract: A multilayer electronic component includes: a body including dielectric layers and having first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction; side margin portions disposed on the fifth and sixth surfaces, respectively; and external electrodes disposed on the third and fourth surfaces, respectively. The body includes an active portion including internal electrodes disposed alternately with the dielectric layers in the first direction, one of the internal electrodes includes a central portion and an interface portion disposed between the central portion and one of the dielectric layers, and the interface portion and one of the side margin portions include Sn.

Abstract: A communication device includes a first antenna and a second antenna, a first front-end module configured to provide a transmission path associated with a first network or a first reception path associated with the first network, and a diplexer electrically configured to provide a second reception path associated with the first network and a first reception path associated with a second network, and processing circuitry configured to electrically connect the first front-end module to the first antenna in a first state, electrically connect the diplexer to the second antenna in the first state, electrically connect the first front-end module to the second antenna in a second state, and electrically disconnect the diplexer from the second antenna in the second state.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate including a cell disposing region and a first block border region, a plurality of gate electrodes on the cell disposing region and extending to the first block border region in a first direction to be parallel to each other, the gate electrodes including a first and second gate electrode, which are adjacent to each other, and a first connection structure on the first block border region, wherein the first connection structure is configured to physically connect the first and second gate electrodes to each other.

Abstract: A semiconductor device may include a first electrode and a second electrode on a substrate and arranged perpendicular to a surface of the substrate, a plurality of channel layers between the first electrode and the second electrode, and a gate electrode surrounding the plurality of channel layers. The plurality of channel layers may be inclined with respect to a direction from the first electrode to the second electrode. An electronic device may include the semiconductor device.

Abstract: A dielectric slurry composition according to an embodiment of the present disclosure includes: a first solution including a hydrophobic solvent and dielectric particles; and a second solution containing a hydrophilic solvent, a hydrophilic dispersant, and a hydrophilic binder, wherein at least a portion of the first solution has an emulsion structure in the second solution.

Abstract: A chip wet-transferring device includes a chamber, a support member provided in the chamber and configured to support a transfer substrate, the transfer substrate including a plurality of grooves and on which a plurality of micro-semiconductor chips are disposed, and a magnetic field generator configured to remove a first micro-semiconductor chip from among the plurality of micro-semiconductor chips that is disposed on the transfer substrate and at least partially outside of the plurality of grooves on the transfer substrate by generating a magnetic field that moves the first micro-semiconductor chip in a direction substantially parallel with an upper surface of the transfer substrate.

Abstract: A semiconductor device may include a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional semiconductor material, a gate dielectric layer on a first area of the channel layer, a gate electrode on the gate dielectric layer, and source and drain electrodes in a second area of the channel layer. The gate dielectric layer may include a high-k dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer may be between the high-k dielectric layer and the channel layer. A dielectric constant of the intermediate dielectric layer may be less than a dielectric constant of the high-k dielectric layer.

Abstract: A system for obtaining output images having a quality index selectable by a user includes an electronic device including at least one processor and a memory storing input images and a set of generative artificial neural networks (GANs), the at least one processor being configured to perform artificial neural network operations. Each GAN is selectable by the user from the set of GANs stored in the memory, for obtaining an image with predefined quality index, each GAN is pre-trained and includes a plurality of Earlier Exit branches each of which is connected after each calculating module, each Earlier Exit branch contains as many calculating modules as remain in the backbone from a connection point of that Earlier Exit branch to a backbone exit, and each calculating module of each Earlier Exit branch performs a same function as a corresponding remaining calculating module in the backbone.

Abstract: Provided are a crystalline InZnO oxide semiconductor, a method of forming the same, and a semiconductor device including the crystalline InZnO oxide semiconductor. The crystalline InZnO oxide semiconductor includes an oxide including In and Zn, wherein in Inductively Coupled Plasma-Mass Spectrometry (ICP-MS) analysis, a content of In among In and Zn is about 30 at % or more and about 75 at % or less, and the crystalline InZnO oxide semiconductor has a peak showing crystallinity at a 2-theta value between about 32.3 degrees and about 33.3 degrees in X-ray diffraction (XRD) analysis.

Abstract: An interconnect structure may include a first dielectric layer including a trench, a first conductive layer in the trench and including a plurality of first graphene layers stacked in a direction from an inner surface of the trench toward a center of the trench, a second dielectric layer on the first dielectric layer and including a through hole extending to the trench, and a second conductive layer in the through hole.

Abstract: A display device includes a first electrode, a second electrode spaced apart from the first electrode and facing the first electrode, a first insulating layer disposed to at least partially cover the first electrode and the second electrode, a second insulating layer disposed on at least a part of the first insulating layer, and a light-emitting element disposed on the second insulating layer between the first electrode and the second electrode, wherein at least a part of a lower surface of the light-emitting element is chemically bonded to the second insulating layer.

Abstract: A display device includes a substrate, a pixel circuit layer disposed on the substrate and including at least one thin film transistor, and a pixel electrode disposed on the pixel circuit layer and electrically connected to the at least one thin film transistor, wherein the pixel electrode includes a lower layer including aluminum, an intermediate layer disposed on the lower layer and including a tungsten oxide, and an upper layer disposed on the intermediate layer and including a transparent conductive oxide.

Abstract: A circuit board includes: a first insulating layer; a second insulating layer positioned on the first insulating layer; and a first pad portion and a second pad portion which are partially buried in the first insulating layer, protrude from the second insulating layer, and have different thicknesses. The first pad portion and the second pad portion each include a first layer and a second layer positioned on the first layer, and heights of the first layer of the first pad portion and the first layer of the second pad portion are lower than a height of the first insulating layer.

Abstract: An image sensor device includes a first pixel that is located at a first row and a first column and comprising a first select transistor and is configured to output a first pixel signal through a first column line, and a second pixel that is located at a second row different from the first row and the first column and comprising a second select transistor and is configured to output a second pixel signal through a second column line. During a first time period, the first select transistor is turned on and the first pixel signal is output, and during a second time period, the second select transistor is turned on, and a first voltage is applied to the second column line through the second select transistor, the second time period including the first time period.

Abstract: Semiconductor packages and methods of fabricating the same are provided. The semiconductor package includes a first package substrate including a first area, a first semiconductor chip mounted on the first area, a second package substrate disposed on an upper surface of the first semiconductor chip and including a second area and a first hole penetrating through the second area, a second semiconductor chip mounted on the second area, a connection member electrically connecting the first package substrate and the second package substrate and between the first package substrate and the second package substrate, and a mold film covering the second semiconductor chip on the second package substrate, filling the first hole, and covering the first semiconductor chip and the connection member on the first package substrate.

Abstract: A dielectric waveguide filter includes a dielectric body including a first and a second surfaces. The dielectric waveguide filter includes a metal plating covering an outer surface of the dielectric body. The dielectric waveguide filter includes a coupling structure formed a portion of the second surface. The coupling structure includes a coupling groove extending from the second surface into the dielectric body and including a coupling surface parallel to the second surface. The coupling structure includes an inner conductor at an annular center of the coupling groove that surrounds the inner conductor and separates the dielectric body into the inner conductor and an outer conductor. The inner conductor in the coupling groove includes a metal surface on the second surface. A distance between the coupling surface and the second surface is related to a coupling degree of the coupling structure.

Abstract: A semiconductor chip including a semiconductor substrate having an active surface and a non-active surface opposite to each other, a plurality of through electrodes passing through the semiconductor substrate, a plurality of wiring structures on the active surface and electrically connected to the plurality of through electrodes, an inter-wire insulating layer surrounding the plurality of wiring structures, a plurality of front chip connection pads electrically connected to the plurality of wiring structures, a front insulating layer surrounding the plurality of front chip connection pads, on the inter-wire insulating layer, a plurality of rear chip connection pads disposed on the non-active surface and electrically connected to the plurality of through electrodes, and a rear insulating layer surrounding the plurality of rear chip connection pads, on the non-active surface, wherein the front insulating layer includes a cover insulating portion covering a side surface of the inter-wire insulating layer may be

Abstract: An electronic device for preventing or reducing damage to a radio frequency front end (RFFE). The electronic device including a memory device configured to store operating state information of a RFFE and a damage prevention condition of the RFFE, the RFFE providing a signal path for delivering a first transmission (TX) signal to an antenna, and a TX signal controller configured to generate a TX signal control signal in response to determining that the operating state information does not satisfy the damage prevention condition, the TX signal control signal causing the first TX signal to be blocked or a magnitude of the first TX signal to be reduced.

Abstract: A semiconductor device includes a substrate, a P-well region, a first N-type metal oxide semiconductor (NMOS) transistor provided in the P-well region, a second NMOS transistor provided on the substrate, and a common body bias region provided between the first NMOS transistor and the second NMOS transistor and contacting both the P-well region and the substrate.

Abstract: According to an aspect of an embodiment, provided is a micro semiconductor chip transferring substrate including: a mold including a plurality of recesses formed to be recessed in a certain depth from an upper surface; and a surface energy reduction pattern formed in region between the plurality of recesses, on the upper surface, the surface energy reduction pattern including a plurality of uneven patterns. When the micro semiconductor chips are aligned by a wet alignment method, by such surface energy reduction pattern, sliding of the micro semiconductor chips toward the inside of the recesses may be improved.

Abstract: A coil component includes a body including a first surface and a second surface opposing each other, a coil disposed in the body and having a concave portion disposed in a portion of a surface of the coil, an external electrode disposed on the first surface of the body, and a connecting conductor connecting the coil and the external electrode. The connecting conductor includes a filling region disposed in at least a portion of the concave portion of the coil and a tapered region having a side surface inclined with respect to the first surface.

Abstract: A device includes: a processor configured to execute instructions in a memory, wherein, the instructions are configured to cause the processor to: select a first network group from among network groups, wherein the first network group is selected from among the network groups based on numbers of global links connecting the network groups, respectively; obtain a first list of network groups, among the network groups, that are not connected to the first network group; select a second network group and a third network group from among the network groups in the first list based on connections between the network groups in the first list; and based on the selecting of the first, second, and third network groups, form a topology including global links connecting the first network group, the second network group, and the third network group each to each other.

Abstract: An integrated circuit device includes a middle insulating structure on a substrate, a first contact structure passing through the middle insulating structure and extending by a first vertical length from a top surface of the middle insulating structure toward the substrate, and a second contact structure passing through the middle insulating structure. The middle insulating structure may have a top surface extending in a lateral direction at a first vertical level. The second contact structure may extend by a second vertical length greater than the first vertical length from the top surface of the middle insulating structure toward the substrate. The first contact structure may have a first top surface extending planar along an extension line of the top surface of the middle insulating structure. The second contact structure may have a second top surface, which may be convex in a direction away from the substrate.

Abstract: An image sensor includes: a light filter; and a light detector that includes a plurality of pixels disposed on a lower portion of the light filter, the light detector being configured to detect light transmitted through the light filter. The light filter includes: a color filter that includes a plurality of red filters, a plurality of green filters, and a plurality of blue filters. The light filter includes: a plurality of multi-spectral filters disposed adjacent to and coplanar with the color filter, each of the plurality of multispectral filters including a plurality of band filters configured to transmit light in different wavelength bands. Each of the plurality of band filters is configured to transmit light in a band filter wavelength range that is narrower than a wavelength range of the plurality of red filters, the plurality of green filters and the plurality of blue filters.

Abstract: A NAND flash device may include a peripheral circuit including a transistor, a substrate, and a device isolation region defining an active region of the substrate. The transistor may include a first gate structure on the active region. The transistor may include source and drain regions extending in a first direction in the active region on both sides of the first gate structure, which may include a first lightly-doped source and drain region adjacent to the first gate structure and a second lightly-doped source and drain region integrally connected thereto. The second lightly-doped source and drain region may be arranged farther from the first gate structure than the first lightly-doped source and drain region. The second lightly-doped source and drain region may have a smaller width in the second direction than a width of the first lightly-doped source and drain region in the second direction.

Abstract: The inventive concepts provide a three-layered stacked image sensor in which misalignment between a through electrode and a pad is reduced and coupling noise between adjacent pads is reduced, and methods of manufacturing the same. The three-layered stacked image sensor includes an upper chip including pixels arranged in a two-dimensional array structure and a first wiring layer, each of pixels including a photodiode, a transfer gate, and a floating diffusion region, an intermediate chip including a source follower gate, a select gate, and a reset gate corresponding to each of pixels, a first silicon layer, and a second wiring layer, and a lower chip including an image sensor processor, a third wiring layer, and a second silicon layer, a cross-section of an upper portion of a through electrode extending from the second wiring layer through the first silicon layer having an inverted trapezoidal structure.

Abstract: A display device includes a display area and a peripheral area surrounding the display area, a pixel disposed in the display area on a substrate, an insulating layer disposed on the substrate and having a valley part along a periphery of the display area in the peripheral area, and an emission driver disposed in the peripheral area on the substrate, providing an emission signal to the pixel through an emission line, and overlapping both a first inner surface and a second inner surface of the insulating layer of the valley part in a plan view.

Abstract: A display apparatus includes a substrate including a display area in which a plurality of pixels are arranged and a non-display area disposed adjacent to the display area, a pixel electrode disposed on the display area of the substrate, a metal bank layer disposed in the display area and the non-display area and defining a pixel opening exposing a portion of the pixel electrode and a hole spaced apart from the pixel opening and extending in a first direction, and a horizontal voltage line disposed in the display area inside the hole in a plan view.

Abstract: A solid oxide cell includes a fuel electrode, an air electrode, and an electrolyte disposed between the fuel electrode and the air electrode. The fuel electrode may include a porous metal body having pores and a barrier portion disposed in the pores of the porous metal body, and the barrier portion has a shape of at least one of a sheet shape and a flake shape.

Abstract: In one embodiment, an image sensor includes unit pixels, each of the unit pixel including a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel in a plan view of the image sensor; and a lens array including a first sub-lens area on the first sub-pixel of each unit pixel and a second sub-lens area on the second sub-pixel of each unit pixel. The first sub-lens area may include a first micro lens, and the second sub-lens area includes a second micro lens. In addition, the first micro lens may include a depression defined in a central area thereof.

Abstract: A semiconductor memory system includes a memory device including plural banks, and a memory controller that generates an offset address for a first bank among the plural banks and a command indicating the offset address, based on a first request. The memory device generates a first address by adding the offset address to a base address for the first bank, according to the command, and performs a memory operation on the first address of the first bank according to the command.

Abstract: A solid oxide cell includes a fuel electrode, an air electrode, and an electrolyte disposed between the fuel electrode and the air electrode and including a plurality of rods. At least one of the fuel electrode or the air electrode is disposed along surfaces of the plurality of rods.

Abstract: A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory devide, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input/output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing.

Abstract: A solid oxide cell stack includes first and second interconnects, a solid oxide cell disposed between the first and second interconnects, and a porous metal foam between the first interconnect and the solid oxide cell, wherein the porous metal foam includes a carbon nanostructure formed on a surface thereof.

Abstract: Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

Abstract: A solid oxide cell includes a fuel electrode, an air electrode, and an electrolyte disposed between the fuel electrode and the air electrode, wherein the air electrode includes an ion-electron conductor and an ion conductor, and the ion-electron conductor comprises a compound represented by ABO3, where A includes La, and B includes Sc and at least one of Fe, Mn or Co.

Abstract: The present disclosure provides a method performed by an electronic device and an apparatus. A method performed by an electronic device may include: obtaining an audio signal comprising a speech signal uttered by at least one sound source; determining a target audio segment of the audio signal, wherein the target audio segment is determined based on a speech quality of at least one audio segment, wherein the at least audio segment is divided from the audio signal; and performing speech separation on the audio signal based on the target audio segment to obtain at least one separated speech signal corresponding to the at least one sound source.

Abstract: The present disclosure relates to a printed circuit board. The printed circuit board includes a plurality of insulating layers each having a plurality of concave portions; a plurality of conductor pattern layers disposed in a plurality of concave portions of each of the plurality of insulating layers; first and second via holes connected to one of the plurality of concave portions independently of each other and penetrating through at least two of the plurality of insulating layers independently of each other; and first and second via conductors disposed in the first and second via holes, respectively, and connecting two of the plurality of conductor pattern layers independently of each other. An average width of the first via conductor is greater than that of the second via conductor on a cross-section.

Abstract: A manufacturing method of a solid oxide cell including a fuel electrode, an air electrode and an electrolyte disposed therebetween is disclosed. Forming at least one of the fuel electrode and the air electrode, includes forming a first paste including electron conductor particles and a first solvent, forming a second paste including ion conductor particles and a second solvent, forming a paste for an electrode layer by mixing the first paste and the second paste, and sintering the paste for the electrode layer.

Abstract: An electronic device includes an injection mold including a mounting part and a wiring groove, a plated wiring plated on the wiring groove, and an electronic element mounted on the mounting part and electrically connected to the plated wiring, wherein the plated wiring is plated on an outer region of the injection mold, and the electronic element mounted on the injection mold dispensed on the plated wiring.

Abstract: An electronic device is provided. The electronic device includes: a first transistor configured to connect an input voltage node to a switching node; a second transistor configured to connect the switching node to a ground node; a latch circuit configured to generate a first signal having a first frequency and to control the first frequency based on a level of a load current; a switching modulation circuit configured to generate a second signal having a second frequency which is 1/N (where N is a natural number) times the first frequency; and a controller configured to control each of the first transistor and the second transistor, based on the second signal.

Abstract: An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.