Abstract: It is one object of the present disclosure to provide measures for securing scalability of the queue depth of cache schedulers by utilizing a plurality of cache schedulers. To this end, a cache memory device in accordance with one embodiment of the present disclosure comprises: a request reception unit configured to receive input transactions; a traffic monitoring module configured to monitor traffic of the input transactions; N cache schedulers, wherein N is an integer greater than or equal to 2; a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein input transactions are transferred via an input transaction region set in each cache scheduler; and an access execution unit configured to perform cache memory accesses to input transactions scheduled by the N cache schedulers.

Abstract: Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.

Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a data security indicator, and a controller. The controller is configured to selectively control access of the host computer system to the user data based on security configuration data of the data storage device. The controller is further configured to respond to the occurrence of one or more operations, the operations being any of: (i) a data access operation requested or performed, by the host computer system, on the data storage device to access the storage medium via the data port; and (ii) a security control operation requested or performed, by an external device, on the data storage device to store, retrieve or update the security configuration data of the data storage device.

Abstract: In a management node that manages a distributed file and object storage that accessibly manages a file used by an application, the distributed file and object storage is accessible to a file managed by a storage of another site, and a management node includes a processor, and the processor is configured to specify an access circumstance relating to a file by an application, and control caching by the distributed file and object storage of the own site with respect to the file managed by the storage of the other site used by the application, before the application is executed, based on the access circumstance.

Abstract: An approach allows concurrent execution of near-memory processing commands, referred to herein as “PIM commands,” and host memory commands. A memory controller determines and issues a plurality of register-only PIM commands that do not reference memory with host memory commands to allow concurrent execution of the register-only PIM commands and the host memory commands. The approach allows concurrent execution of register-only PIM commands and host memory commands without interference, even when the register-only PIM commands and the host memory commands are interleaved, and even for the same memory module, which improves resource utilization and performance. Further improvement of resource utilization and performance is achieved by extending a register-only phase by reordering register-only PIM commands before non-register-only PIM commands, subject to dependency constraints, and using shadow row buffers to provide local working copies of data from memory to near-memory compute elements.

Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.

Abstract: Purging resources from a cache in a distributed networked system is described. A first data center of the distributed networked system receives a purge request to purge a resource from cache. If the purge request does not include a cache key, the first data center determines whether the purge request is valid, and if valid, purges the resource from cache of the first data center, generates a cache key for the resource, and causes the purge request that includes the generated cache key to be sent to other data centers of the distributed networked system for purging the resource from cache. If the purge request includes a cache key, the first data center skips determining whether the purge request is valid and purges the resource from cache based on the cache key.

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Abstract: A data storage system includes a plurality of data storage drives, and a system controller coupled to each data storage drive of the plurality of data storage drives. The system controller is configured to store internal drive management data for each data storage drive of the plurality of data storage drives.

Abstract: According to some embodiments of the present invention, there is provided a hybrid cache memory for a processing device having a host processor, the hybrid cache memory comprising: a high bandwidth memory (HBM) configured to store host data; a non-volatile memory (NVM) physically integrated with the HBM in a same package and configured to store a copy of the host data at the HBM; and a cache controller configured to be in bi-directional communication with the host processor, and to manage data transfer between the HBM and NVM and, in response to a command received from the host processor, to manage data transfer between the hybrid cache memory and the host processor.

Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.

Abstract: A method and system are provided for limiting unnecessary data traffic on the data busses connecting the various levels of system memory. Some embodiments may include processing an invalidation command associated with a system or network operation requiring temporary storage of data in a local memory area. The invalidation command may comprise a memory location indicator capable of identifying the physical addresses of the associated data in the local memory area. Some embodiments may preclude the data associated with the system or network operation from being written to a main memory by invalidating the memory locations holding the temporary data once the system or network operation has finished utilizing the local memory area.

Abstract: A data storage device is disclosed comprising a head actuated over a disk, a first semiconductor memory (SM) having a first endurance, and a second SM having a second endurance lower than the first endurance. A write command is received from a host including write data. When a size of the write command is less than a threshold, the write data is stored in a first SM write cache in the first SM, and when the size of the write command is greater than the threshold, the write data is stored in a second SM write cache in the second SM.

Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

Abstract: Configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system is disclosed. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. In response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.

Abstract: A chip includes a power pin, a ground pin, a plurality of input/output (I/O) pins, a readable/writable memory, a switching circuit, and a control circuit. The I/O pins include a plurality of mapping pins and a control pin. The readable/writable memory includes a clock port, a plurality of I/O ports, and an enable port. The control circuit selectively activates or does not activate the switching circuit according to the control pin. When the switching circuit is activated, the switching circuit electrically couples the clock port, the I/O ports, and the enable port to the mapping pins respectively.

Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

Abstract: Methods and apparatus relating to cryptographic protection of memory attached over interconnects are described. In an embodiment, memory stores data and a processor having execution circuitry executes an instruction to program an inline memory expansion logic and a host memory encryption logic with one or more cryptographic keys. The inline memory expansion logic encrypts the data to be written to the memory and decrypts encrypted data to be read from the memory. The memory is coupled to the processor via an interconnect endpoint of a system fabric. Other embodiments are also disclosed and claimed.

Abstract: Embodiments are directed to memory protection with hidden inline metadata to indicate data type and capabilities. An embodiment of a processor includes a processor core and cache memory. The processor core is to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata hidden at a linear address level, hidden from software, the hidden inline metadata to indicate data type or capabilities for the associated data stored on the same cacheline.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.