Abstract: A method of forming an integrated circuit capacitor is disclosed comprising the steps of providing a substrate, forming a conductive region at the substrate, and forming an insulating layer on the conductive region and the substrate. The method further comprises the steps of removing selective portions of the insulating layer to expose a selective area of the conductive region thereby forming a storage node contact window and forming a first conductive layer on the insulating layer and within the storage node contact window wherein the first conductive layer is in electrical communication with the conductive region. Next a cavity is formed in the first conductive layer. Subsequently, selected portions of the first conductive layer are removed leaving at least a remaining portion of the first conductive layer in which the cavity is formed thereby isolating the remaining portion of the first conductive layer from surrounding circuit elements.

Abstract: A process for fabricating a deep submicron MOSFET device gas been developed, preparing a narrow local threshold voltage adjust region in a semiconductor substrate, with the narrow local threshold voltage adjust region self aligned to an overlying, narrow polysilicon gate structure. The process consists of forming a narrow hole opening in an insulator layer, followed by an ion implantation procedure used to place the threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening, A polysilicon deposition, followed by an oxidation process, converts the unwanted polysilicon to a silicon oxide layer, while leaving unconverted polysilicon in the narrow hole opening, Removal of the oxidized polysilcon regions results in a narrow polysilicon gate structure, in the narrow hole opening, self aligned to the threshold voltage adjust region.

Abstract: A method comprising the steps of forming an insulating film on a semiconductor substrate in which a certain infrastructure is built, forming a series of conductive wirings on the insulating film, forming a blanket interlayer insulating film over the resulting structure, forming first photoresist film patterns on the interlayer insulating film, the side walls of said patterns each being located above the conductive wirings, forming sacrificial film spacers at the side walls of the first photoresist film patterns, forming second photoresist film patterns on the interlayer insulating film between the sacrificial film spacers, and forming contact holes to expose areas of the conductive wirings by sequentially removing the sacrificial spacers and the thus exposed areas of the interlayer insulating film, which results in an improvement in the operating reliability of semiconductor devices and the production yield as well as the high integration of devices.

Abstract: After forming a silicon oxide layer and an amorphous silicon layer on a GaAs substrate in stacking manner, a gate electrode forming opening portion is formed by RIE etching. Then, by selectively removing only the amorphous silicon layer at the portion contacting with the opening portion at the side of the source electrode, a WSi.cndot.TiN.cndot.Pt layer is formed within the opening portion. Subsequently, after applying an organic photoresist layer, an entire surface is etched back to remove at least the WSi.cndot.TiN.cndot.Pt layer above the amorphous silicon layer. Then, by using the WSi.cndot.TiN.cndot.Pt layer remaining in the opening portion as a plating electrode, an Au layer is plated to form a reversed L-shaped gate electrode with an overhanging portion only extending toward the source electrode.

Abstract: A method for the manufacture of integrated circuits where it is desired to produce narrow conducting grids separated by a narrow gap and uses the lifting-up of silicon nitride (bird's bill) which is formed during a thick localized oxidation. A localized oxidation step is carried out and the oxide formed is totally removed. The edges (20, 22) of a nitride layer (14) stay overhanging. A conforming polycrystalline-silicon deposition enables silicon to be deposited uniformly, including beneath these edges. Finally, vertical anisotropic etching removes the silicon everywhere except beneath the overhanging edges, so that two silicon lines (28, 30) remain. An ion implantation (34) may be performed between the two lines. The method will find particular application for making anti-dazzle systems for photosensitive charge-coupled devices.

Abstract: When a semiconductor is manufactured by a resist mask process while using photolithography techniques, the gate wiring width is increased without increasing the cell area by providing a sidewall on the gate mask and using the sidewall as a mask. The sidewall is produced by applying a CVD oxide film to the mask and removing the oxide film by anisotropic etching. This provides a minimum gate line width of 0.7.mu. and a minimum space width of 0.3.mu..

Abstract: The disclosure is directed to a method of forming a CCD with two sets of gate electrodes in a single layer of a conductive material. The method comprises forming a channel region in a body of a semiconductor material along a surface thereof and forming a layer of conductive material over and insulated from the surface of the body. A first masking layer is formed on the conductive layer and spaced strips of polycrystalline silicon are formed on the first masking layer. Using a portion of the spaces between the strips as a mask, impurities of a conductivity type opposite that of the channel region are embedded in the channel region to form spaced barrier regions along the channel region. A layer of silicon dioxide is formed over each of the strips and the spaces between the strips are filled with polycrystalline silicon. The portion of the silicon dioxide layer at one end of each of the strips is etched away to expose a portion of the first masking layer.

Abstract: A charge coupled device (CCD) has a single level electrode of single crystalline silicon on an insulating layer over a surface of a body of single crystalline silicon. The CCD is made by forming a layer of insulating material on a surface of a body of single crystalline silicon with a portion of the surface being exposed. A layer of single crystalline silicon is then epitaxially grown by epitaxial lateral overgrowth on the exposed surface of the body and over the insulating material layer. The layer of single crystalline silicon is removed from the surface of the body to insulate the single crystalline silicon layer from the body by the insulating material layer. Portions of the layer of single crystalline silicon are removed to form a plurality of separate gate electrodes.

Abstract: Method for producing a non-volatile memory cell and obtained memory cell.

Abstract: An improved process is provided for fabricating short channel complementary metal oxide semiconductor devices. The devices comprise source and drain regions separated by gate regions. The process comprises forming a shallow channel doping region (12') beneath the surface of a semiconductor (10) and forming source-drain regions (20') of opposite conductivity type (formerly known as lightly doped drain structures) on either side of the shallow doping region. A gate oxide (16) is formed on the surface of the semiconductor above the shallow channel doping region and a gate electrode (18) is formed to the gate oxide subsequent to the formation of the shallow channel doping region. The process permits spacing of the channel doping from the source-drain doping with self-alignment. Further, the doping of the source-drain regions is not constrained to the values of the lightly-doped structures of the prior art.

Abstract: Along the outline of a first doped region, a first mask is formed. The mask is made up of a dielectric opposed to the oxygen diffusion. Another mask is created within this first mask, using a process of selective thermal oxidation. The second mask is used to implant dopant in a second region which will only be defined along the outlines of the first region.

Abstract: Nanometer thick vertical metallic structures are fabricated on a substrate by depositing a metallic layer on a substrate surface on which one or more buttresses are formed, etching the metallic layer to expose the horizontal surfaces of the substrate and the buttresses, and etching the substrate to remove the buttresses, thereby producing vertical structures on the substrate. The metallic layer is formed by thermal decomposition of a volatile metal-containing precursor gas in the presence of a carrier gas at low pressure, unlike that in conventional CVD reactors. The metallic layer thus formed has a grain size which is fraction of the thickness of the vertical structure.

Abstract: Fine featured devices are produced by a series of fabrication steps including exposing selective surface regions to irradiation, e.g. to an ion beam, generally to result in removal of masking material within irradiated regions. In most instances, subsequent etching is under conditions such that bared material is preferentially removed. Etch-removal and irradiation are such that overgrown material is of device quality at least in etched regions. The inventive process is of particular value in the fabrication of integrated circuits, e.g. circuits performing electronic and/or optical functions. The inventive process is expediently used in the fabrication of structures having minimum feature size of 1 micrometer and smaller. Patterning is dependent upon masking material of a maximum thickness of 100 .ANG..

Abstract: An EEPROM design featuring narrow linear electrodes including a source, a drain, a thin oxide, channel and floating gate. A pair of linear, opposed field oxide barrier walls form widthwise boundaries of the active structure which can be very closely spaced. The drain electrode, implanted in the substrate, abuts both opposed field oxide lateral walls, but does not extend under either wall. The source, drain and channel are formed in a single implant followed by diffusion after the field oxide barrier walls are formed, but prior to formation of the floating gate. All but opposed field oxide walls in a stripe design. A control gate is disposed over the floating gate. The combination of opposed field oxide barrier walls, a stripe electrode design, and single step implant for electrode formation results in a very compact cell, utilizing a simplified EEPROM process.

Abstract: A semiconductor device including a substrate having a low substrate surface formed in the substrate with a first gentle slope from the substrate surface; a single crystalline layer formed on the low substrate surface nearly level with the substrate surface and having a gentle slope facing the first gentle slope; an optical semiconductor element is constructed using the single crystalline layer. An electronic semiconductor element is constructed using the substrate surface. A wiring layer connects electrodes of the optical semiconductor element and the electronic semiconductor element through the first and the second gentle slopes.

Abstract: A T-shaped gate of an FET is formed by utilizing the image reverse photolithography process, which includes coating of a semiconductor substrate with a positive resist, initial exposure of an resist outside region, reversal baking, flood exposure of the entire resist layer, and development of the resist layer. The image reverse photolithography process is performed after a dummy gate is formed on the semiconductor substrate. By properly adjusting a light quantity of the flood exposure, a resist pattern can be obtained which has a center hole whose boundary surface is inclined inwardly, and whose bottom surface defines a bottom resist layer thinner than the dummy gate. After removing the dummy gate, a gate material is deposited and then the resist pattern is removed to leave the T-shaped gate.

Abstract: Methods for reducing linewidths of Field Effect Transistors (FETs) and making FETs with 0.5 to 0.15 .mu.m effective gate lengths are used separately or in a combined process sequence, that combines enhancement/depletion mode and microwave Metal-Semiconductors FETs (MESFETs) on the same GaAs chip. Photoresist linewidths are used to form dummy or substitutional gates using optical lithography with no deliberate overexposures. The dummy gate may be used as a mask for N+ implantation. The photoresist linewidth is then reduced in its lateral basewidth while preserving its height to basewidth aspect ratio in an isotropic oxygen plasma etch. A nonconformal dielectric film of silicon monoxide is deposited over the photoresist linewidth patterns. Dielectric reverse liftoff of the SiO pattern transfer dielectric provides a self-aligned stencil mask with respect to the N+/N- interfaces. The SiO stencil is also a dielectric spacer with respect to the N+/N- interfaces.

Abstract: A production method for a semiconductor device (e.g. MESFET) includes a metal pattern production process for producing a plurality of metal patterns e.g. gate, source, drain electrodes on a semiconductor substrate having an active layer. The metal pattern production process includes disposing dummy metal patterns (2a/2b) of silicon nitride at a plurality of metal pattern production regions on the semiconductor substrate using a resist mask (3), disposing a resist pattern (4) on the entire surface of the substrate with gaps between the metal pattern production regions, filling the gaps between said dummy metal patterns and the resist pattern with resist by reflowing the resist pattern (4), removing the dummy metal patterns (2a), depositing a metal layer over the entire surface of the partially completed device, and lifting off unwanted metal to produce a desired metal pattern of source/drain electrodes (5).

Abstract: A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.

Abstract: A triangular ring laser utilizing total internal reflection at two angled facets and a preselected amount of reflection at a third angled facet is disclosed. Partial transmission occurs through the third facet to reduce the threshold current required for achieving stimulated emission. The facets are at three corners of the triangular laser, and are formed by chemically assisted ion beam etching in which SiO.sub.2 is used as a mask, whereby smooth vertical walls are produced to form facets having reflective characteristics equivalent to those formed by cleaving.

Abstract: A process for forming sidewalls for use in the fabrication of semiconductor structures, where the thin, vertical sidewalls are "image transferred" to define sub-micron lateral dimensions.First, a patterned resist profile with substantially vertical edges is formed on a substrate on which the sidewalls are to be created. Then, the profile is soaked in a reactive organometallic silylation agent to silylate the top and the vertical edges of the resist to a predetermined depth, thereby rendering the profile surfaces highly oxygen etch resistant. In a subsequent anisotropic RIE process, the horizontal surfaces of the silylated profile and the unsilylated resist are removed, leaving the silylated vertical edges, that provide the desired free-standing sidewalls, essentially unaffected.

Abstract: A method of electrolytic deposition of metal is used to decrease the minimum size pattern that can be obtained using photolithography. In the manufacture of integrated circuits, a layer of metal and then photoresist is deposited on the dielectric layer of the substrate prior to masking to define the gate apertures. After masking and etching through to the dielectric, metal is electrodeposited on the metal edges that abut the gate aperture, thus decreasing the aperture size. After that decreased gate dimension is etched into the dielectric to define the gate lengths of the semiconductor devices, the wafer is stripped and the subsequent manufacture proceeds in the conventional manner.

Abstract: A two mask process for forming dielectrically filled planarized trenches of arbitrary width in a semiconductor substrate, the masks being of such character that they are amenable to computerized generation. The first mask defines the active regions and subdivides the trench isolation regions into a succession of trench and plateau regions, where the widths of the trench and plateau regions fall within in a dimensional range constrained by photolithographic precision of the masks and the ability to conformally deposit dielectric material into the trenches. With the first etch mask in place, the semiconductor is anisotropically etched to formed the first trench regions. A conformal deposition of dielectric follows, and by virtue of the dimensional constraints ensures substantially void free trench dielectric and a concluding substantially planar topology of the dielectric on the substrate surface.

Abstract: In order to fabricate gates for an integrated circuit formed on a semiconductor substrate of silicon covered with at least one layer of oxide, one layer of polycrystalline silicon and if necessary one layer of silicide, an initial step consists in successive deposition of a silicon nitride layer and a silicon oxide layer, openings in these two layers being then formed by photoetching in a second step. In a third step, the silicon oxide layer is partly removed by deoxidation in order to bare the nitride layer over a certain distance which determines the spacing between two consecutive gates, oxide being then grown within the openings formed during the second step. The final step consists in removing the nitride regions uncovered during the third step as well as the subjacent silicide layer if this latter is provided and the subjacent polycrystalline silicon layer.

Abstract: Junction field effect transistor and method of fabrication. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. A layer of silicon dioxide is grown on the surface of the epitaxial layer and selectively removed to expose silicon in a pattern of a plurality of parallel surface areas with parallel strips of silicon dioxide in between. A second epitaxial layer is deposited over the exposed surface areas and the strips of silicon dioxide. Barriers of silicon dioxide are formed in the second epitaxial layer extending from the surface to adjacent to but spaced from the edges of the buried strips. P-type conductivity imparting material is implanted and then diffused into the zones of the second epitaxial layer defined by adjacent barriers and overlying the buried strips to form gate regions.

Abstract: Edge conduction in a silicon-on-sapphire transistor is minimized by a process which permits precise doping of the edge channel regions of the transistor. The silicon island (19) containing the transistor (24) is precisely doped around its edges by ion implanting an epitaxial silicon layer (13) on a sapphire substrate (11), with an oxide mask (29) covering, with the exception of a narrow peripheral edge (37), the portion of the silicon which is eventually to form the island (19') on which the transistor is to be constructed. The mask (29) is then expanded by the addition of a sleeve (43) to cover the additional peripheral edge region (37) in the silicon. When the silicon is subsequently etched using the expanded oxide pattern 45 as a mask, the periphery of the remaining silicon will be doped to a predetermined depth (37) corresponding to the width of the sleeve (43).

Abstract: A process is described for fabricating self-aligned buried doped regions in semiconductor devices and integrated circuits which avoids any need for delineation of the buried doped regions in the active portions of the device. Avoiding delineation improves the quality of the epitaxial layer used to cover the buried doped regions thereby improving overall performance and yield. Multiple mask layers are used in connection with a single mask pattern to achieve self-alignment. One mask layer consists of a material with a modifiable etch rate, e.g. polysilicon. A portion of the single crystal substrate is rendered non-single crystal and used as an alignment key which is propagated through the epitaxial layer grown over the undelineated buried doped regions. The dimensions and separations of the self-aligned buried doped regions can be precisely controlled.

Abstract: A semiconductor device which is provided with a surface channel type or bulk channel type MIS FET. The MIS FET comprises at least a semiconductor substrate of a first conductivity type, a layer member formed in a predetermined pattern on the major surface of the substrate and having an insulating side surface; an insulating layer formed on the major surface of the substrate to extend from the insulating side surface in a direction opposite from the layer member; a conductive layer formed on the major surface of the insulating layer in contact with the insulating side surface of the layer member; and a first semiconductor region of a second conductivity type formed in the semiconductor substrate having a marginal edge corresponding to that of the conductive layer.