Abstract: A monitor wafer used to determine the cleanliness of a wafer fabrication environment requires a surface having a minimum of light scattering anomalies so that contamination deposited by the environment is not confused with light scattering anomalies initially on the monitor wafers. In the present invention, ingots of a single-crystal semiconductor are grown at a reduced pull rate and wafers produced from the ingot are annealed within a preferred temperature range that varies with the pull rate to produce wafers having reduced light-scattering anomalies on their surfaces. The number of light-scattering anomalies increases at a slower rate upon repetitive cleaning cycles than does the number of light-scattering anomalies of prior art wafers.

Abstract: A method of controlling a misfit dislocation in a process of producing an epitaxial semiconductor wafer comprising a semiconductor substrate and an epitaxial layer deposited on the semiconductor substrate, an impurity concentration of the epitaxial layer differing from that of the semiconductor substrate, has the step of controlling the amount of an extrinsic strain caused on the back surface of the semiconductor substrate prior to the step of depositing the epitaxial layer, thereby controlling an occurrence of misfit dislocation caused in and near the interface between the semiconductor substrate and the epitaxial layer.

Abstract: A new method of forming a tapered polysilicon etching profile in the manufacture of a thin film transistor integrated circuit is described. A layer of polysilicon is deposited over the surface of a semiconductor substrate. Ions are implanted into the polysilicon layer whereby the upper half of the polysilicon layer is damaged by the presence of the ions within the layer. The polysilicon layer is anisotropically etched. The polysilicon layer is isotropically etched whereby the damaged upper portion of the layer is etched faster than is the undamaged lower portion resulting in a tapered polysilicon layer. A layer of gate oxide is deposited over the surface of the tapered polysilicon layer. Then the thin film transistor body is formed. A layer of amorphous silicon is deposited over the surface of the gate oxide layer. The amorphous silicon layer is recrystallized to yield larger grain sizes.

Abstract: A thin Silicon film On Insulator (SOI) material fabricating method which is capable of providing a very high thickness uniformity of the silicon film, a process simplification and a considerable reduction of processing cost is disclosed, in which a silicon oxide film is formed on one or both of a p-type silicon bond wafer and a silicon base wafer, then the two wafers are bonded together through the silicon oxide film, subsequently a fixed positive charge is induced in the silicon oxide film to form a n-type inversion layer in the p-type silicon bond wafer adjacent to an interface between the p-type silicon bond wafer and the silicon oxide film layer, and thereafter a chemical etching is effected while applying a positive voltage to the p-type silicon bond wafer so that an etch-stop is made at an interface between a depletion layer including the n-type inversion layer and the p-type layer.

Abstract: This is a method of forming a semiconductor integrated circuit with isolation regions, (possibly wide and narrow) comprising of a thin oxide film and deposited anisotropic oxide. It uses an inorganic layer (e.g. noncrystalline silicon) to mask what will be active areas and allows for the growth of a thermal oxide film in the trenches reducing the parasitic channel formation along the trenches. The use of anisotropic oxide to fill the trenches allows for wide and narrow trenches to be simultaneously filled to the desired depth. The removing of inorganic layer and the use of anisotropic oxide to fill the trenches produces a flat planar surface and finer isolation regions.

Abstract: The present invention relates to a semiconductor device e.g., a CMOS, comprising a denuded region and a bulk-defect region, as well as a process for producing, e.g., CMOS. In a conventional CMOS, the distance (dp) between the bulk-defect region and p.sup.+ -type source or drain region (dp) is greater than the distance (dn) between the bulk-defect region and the p well (dn). As a result, a leakage current can be generated in the PN junction. In order to eliminate the problems caused due to dp>dn, the present invention forms in a semiconductor substrate a bulk-defect region having a depth which is nonuniform in accordance with the nonuniform depth of the semiconductor elements.

Abstract: A semiconductor substrate and process for making are disclosed. The substrate is suitable for use in manufacturing large scale integrated circuits. The process comprises the steps of heating a semiconductor substrate at a temperature not lower than 1100.degree. C., implanting electrically inert impurities into the major surface of the substrate, heating the substrate at a temperature ranging from 600.degree. to 900.degree. C. and providing a single crystal semiconductor layer.

Abstract: Disclosed is a method of stabilizing and standardizing semiconductor wafers obtained from a plurality of vendor sources for use in both unipolar and bipolar device manufacturing lines. Based on measured initial oxygen concentration, the as-received wafers are grouped into lots. Next, based on measured oxygen precipitation rate of each lot, the wafer lots are grouped into classes, regardless of their vendor origin. Typically, the grouping consists of three classes corresponding to low, intermediate and high oxgen precipitation rate.The wafers of each class are then subjected to a thermal adaptation cycle tailored to the class to generate in each wafer clusters of a concentration corresponding to a predetermined cluster concentration range and a defect-free zone corresponding to a predetermined defect-free zone range. The thermal adaptation cycle is different from class to class, but identical for wafers of a given class.

Abstract: A method of manufacturing a semiconductor substrate having dielectric regions is disclosed. The method comprises steps of forming an amorphous silicon layer on the surface of a monocrystalline silicon substrate, annealing a selected surface of said amorphous silicon layer to form a crystallized region intended as an active region, subjecting the obtained structure to a thermal oxidation process to form said dielectric isolation regions, and removing an oxide coating formed on the surface of said crystallized region.