Abstract: A semiconductor photodetector is disclosed which comprises a pn junction formed in a semiconductor substrate and a pair of electrodes for applying a reverse bias to the pn junction, in which at least a part of the junction plane of the pn junction has been metamorphosed by enhanced diffusion. Hence the pn junction from an outer peripheral portion and a central portion is made smooth.

Abstract: Series resistance in the low impurity portion of a high breakdown PN junction of a three or four layer device is reduced by providing an increased inpurity region at the junction of the same conductivity type as the low impurity portion and having an impurity profile such that the increased impurity region is depleted under reverse biasing before critical field is reached therein. The three layer devices include insulated gate field effect transistors and bipolar devices and the four layer device is a semiconductor controlled rectifier (SCR).

Abstract: The present invention relates to a method of producing a metal-oxide semiconductor device with improved capacity for preventing an actuation of a parasitic bipolar transistor. In the present invention, a metal-oxide seminconductor device is produced through a process in which a single conductive semiconductor region with low-impurity density, on top of which region a gate electrode is provided via a gate-insulating film, consists of two sub-layers with different specific resistance. The upper sub-layer of the region has a significantly lower specific resistance than the lower sub-layer of the region. When a lifetime-reducing agent for reducing the reverse-recovery time of a built-in diode is diffused into the single conductive semiconductor region with low-impurity density, the lifetime-reducing agent concentrates in the upper sub-layer of the region, thereby increasing the specific resistance of the upper sub-layer.

Abstract: A method of fabricating a lateral semiconductor structure includes providing a semiconductor substrate and forming wells therein. Following formation of a dielectric layer on the substrate, field region openings are formed through which field regions are implanted into the substrate. The self-aligned formation of field oxidation regions to the field region openings then occurs and is followed by the formation of field plates on the field oxidation regions. A first active device region is then formed in said substrate, the formation of which is self-aligned to the field plates. This is followed by the formation of a second active device region in the first active device region which is also self-aligned to the field plates. The resulting structure allows for high speed devices that maintain consistently high current gain without sacrificing Early or breakdown voltages.

Abstract: A method for selectively depositing amorphous or polycrystalline silicon wherein a wafer having exposed silicon regions thereon is placed into a CVD reactor and subjected to a silicon containing gas and a halogen containing gas, at least one of which flows into the reactor with a hydrogen carrier gas. Amorphous silicon may be selectively deposited in the range of approximately 200 to 550 degrees centigrade while polycrystalline silicon may be selectively deposited in the range of approximately 550 to 750 degrees centigrade. It is also possible to deposit polycrystalline silicon at temperatures in the range of approximately 750 to 1000 degrees centigrade by employing another embodiment of the present invention.