Gas Flow Control Patents (Class 148/DIG57)
  • Patent number: 5296088
    Abstract: A compound semiconductor crystal growing method includes the steps of (a) setting a substrate having a substrate surface in a reaction chamber, and (b) supplying a material gas of a compound semiconductor which is to be grown in the form of a crystal on the substrate surface within the reaction chamber and a control gas to the reaction chamber under a predetermined condition, and controlling the supply of the control gas to control an adsorption rate of the material gas on the substrate surface. The control gas makes competitive adsorption with the material gas on the substrate surface but makes no chemical reaction such that no continual accumulation on the substrate surface occurs under the predetermined condition. The competitive adsorption is defined as a phenomenon in which the material gas and the control gas compete and become adsorped on the substrate surface.
    Type: Grant
    Filed: August 4, 1992
    Date of Patent: March 22, 1994
    Assignee: Fujitsu Limited
    Inventors: Kunihiko Kodama, Nobuyuki Ohtsuka, Masashi Ozeki, Yoshiki Sakuma
  • Patent number: 5180684
    Abstract: A semiconductor growth process wherein a plurality of layers, each consisting of a different king of semiconductor material, are grown, includes the steps of: heating a substrate to a first growth starting temperature at which a growth of a first semiconductor layer can be started, supplying a first material gas to the surface of the substrate to cause a growth of the first semiconductor layer, lowering the temperature of the substrate to below first growth starting temperature, and at the same time, stopping the supply of the first material gas, to stop the growth of the first semiconductor layer, heating the substrate to a second growth starting temperature at which a growth of a second semiconductor layer can be started, and supplying a second material gas to the surface of the substrate to cause a growth of the semiconductor layer.
    Type: Grant
    Filed: March 6, 1990
    Date of Patent: January 19, 1993
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Fujioka
  • Patent number: 5168077
    Abstract: A p-type GaAs or AlGaAs thin film is formed by a MOCVD method. In the growing step of the thin film, the thin film is doped with a high concentration of carbon atoms forming an acceptor level such that the carrier concentration of the thin film falls within the range of between 1.times.10.sup.18 cm.sup.-3 and 1.times.10.sup.20 cm.sup.-3. At least one of trimethyl gallium and trimethyl aluminum is used as a raw material gaseous compound of III-group element, and arsine is used as a raw material gaseous compound of V-group element. The thin film is formed by an epitaxial growth under the molar ratio V/III of the V-group element supply rate to the III-group element supply rate, which is set at such a small value as 0.3 to 2.5, the temperature of 450 to 700.degree. and the pressure of 1 to 400 Torr. The thin film formed under these conditions exhibits a mirror-like smooth surface, and the film-growth rate is dependent on the supply rate of the V-group element.
    Type: Grant
    Filed: March 29, 1990
    Date of Patent: December 1, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ashizawa, Takao Noda, Mitsuhiro Kushibe, Masahisa Funemizu, Kazuhiro Eguchi, Yasuo Ohba, Yoshihiro Kokubun
  • Patent number: 5106453
    Abstract: In an MOCVD reactor, gases are channeled around the periphery of a baffle plate (15) so as to flow radially inwardly along a slotted injection plate (16). The slots (22) in the injection plate extend radially and are of non-uniform width so as to compensate for a non-uniform rate of deposition. The resultant flow over a rotating heated substrate (17) gives a more uniform deposit of epitaxially grown material.
    Type: Grant
    Filed: January 29, 1990
    Date of Patent: April 21, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: John W. Benko, Jerome Levkoff, Daniel C. Sutryn, Montri Viriyayuthakorn
  • Patent number: 5037775
    Abstract: An alternating cyclic (A.C.) method for selectively depositing single element semiconductor materials, on the surface of a substrate without depositing the material on an adjacent mask layer. A gas of a reducible compound of the material and a reducing gas, preferably hydrogen, are simultaneously flowed through a reaction chamber to deposit the material on the substrate surface and to a lesser extent on the mask layer. Then, the flow of reducing gas is interrupted to cause the reducible compound gas to etch the material which forms on the mask layer in a disproportionation reaction. The deposition and etch steps are repeated in an alternating cyclic fashion until the requisite thickness is deposited. The process may take place in a single reaction chamber, using only the reducible compound gas and pulsed flow of the reducing gas.
    Type: Grant
    Filed: September 5, 1989
    Date of Patent: August 6, 1991
    Assignee: MCNC
    Inventor: Arnold Reisman
  • Patent number: 4916089
    Abstract: In order, in the epitaxial production of semiconductor products and of articles provided with a layer, to be able to make the junction between the layers applied to the substrates atomically sharp, it is important to be able to change the gas mixture, to be introduced into a pulsed reactor or MBE reactor, rapidly, accurately and without losses in respect of quantity and of composition. To this purpose, each of the gases to be introduced into the reactor is conveyed to a separate gas pipette and thereafter the content of the gas pipette is cyclically passed, by means of a pressure differential, into the pulse reactor, with the composition of the mixture being changed per one or more cycles.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: April 10, 1990
    Assignee: Stichting Katholieke Universiteit
    Inventors: Jaap Van Suchtelen, Lodevicus J. Giling, Josephus E. M. Hogenkamp
  • Patent number: 4910163
    Abstract: Silicon epitaxial layers are grown on oriented silicon substrates using an open-tube Si-I.sub.2 chemical vapor deposition (CVD) reactor in the temperature range of 650.degree.-740.degree. C. Hydrogen and inert gases such as helium and argon are used as carrier gases, and the iodine/carrier gas mixture contacts the silicon source to produce silicon iodide which disproportionates to deposit pure silicon epitaxial layers on the substrate.
    Type: Grant
    Filed: June 9, 1988
    Date of Patent: March 20, 1990
    Assignee: University of Connecticut
    Inventor: Faquir C. Jain
  • Patent number: 4885258
    Abstract: There is provided an improved thin-film transistor of which a principal semiconducting layer comprises a layer composed of an amorphous material prepared by (a) introducing (i) a gaseous substance containing atoms capable of becoming constituents for said layer into a film forming chamber having a substrate for thin-film transistor through a transporting conduit for the gaseous substance and (ii) a gaseous halogen series substance having a property to oxidize the gaseous substance into the film forming chamber through a transporting conduit for the gaseous halogen series oxidizing agent, (b) chemically reacting the gaseous substance and the gaseous halogen series agent in the film forming chamber in the absence of a plasma to generate plural kinds of precursors containing exited precursors and (c) forming said layer on the substrate with utilizing at least one kind of those precursors as a supplier.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: December 5, 1989
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunichi Ishihara, Hirokazu Ootoshi, Masaaki Hirooka, Junichi Hanna, Isamu Shimizu
  • Patent number: 4883769
    Abstract: Multidimensional quantum-well arrays are made by electron-beam lithographic atterning, followed by solid-state diffusion.
    Type: Grant
    Filed: August 18, 1988
    Date of Patent: November 28, 1989
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Thomas R. Au Coin, Walter D. Braddock IV, Gerald J. Iafrate
  • Patent number: 4859625
    Abstract: A method for epitaxial growth of compound semiconductor containing three component elements, two component elements thereof being the same group elements, in which three kinds of compound gases each containing different one of the three component elements are cyclically introudced, under a predetermined pressure for a predetermined period respectively, onto a substrate enclosed in an evacuated crystal growth vessel so that a single crystal thin film of the compound semiconductor is formed on the substrate.
    Type: Grant
    Filed: November 20, 1987
    Date of Patent: August 22, 1989
    Assignee: Research Development Corporation of Japan, Junichi Nishizawa and Oki Electric Industry Co., Ltd.
    Inventor: Fumio Matsumoto
  • Patent number: 4829021
    Abstract: An injection block having a plurality of geometrically arranged injection sources for gaseous Group III metal organic compounds is oriented substantially perpendicular to the placement of at least one semiconductor wafer substrate within a vacuum reaction chamber. The injector sources are sized to provide disbursing flow of the compounds capable of depositing a layer of about 5% uniform thickness or less over substantially the entire semiconductor wafer. An injection source of Group V compounds is located centrally within the geometrically arranged injection sources for the Group III compounds. The Group V injection source is sized to supply an excess of the Group V compounds required to react with the Group III compounds in order to form Group III-V semiconductor layers on the substrate and partition the Group III sources into groups having substantially equal numbers of injection sources. An excess of Group V comounds is injected.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: May 9, 1989
    Assignee: Daido Sanso K.K.
    Inventors: Lewis M. Fraas, Paul S. McLeod, John A. Cape
  • Patent number: 4826784
    Abstract: A method of OMCVD heteroepitaxy of III/V (GaAs) material on a patterned Si substrate is described wherein heteroepitaxy deposition occurs only on the exposed Si surfaces and nowhere else.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: May 2, 1989
    Assignee: Kopin Corporation
    Inventors: Jack P. Salerno, Jhang W. Lee, Richard E. McCullough
  • Patent number: 4808551
    Abstract: In an epitaxial growth method of this invention, a first gas consisting of a hydrogen diluted gas containing a Group V element is continuously flowed on a monocrystalline substrate that is placed in a reaction chamber, the monocrystalline substrate is arranged in a gas mixing region where the first gas and a second gas containing a halogenide of a Group III element are mixed adjacent to the monocrystalline substrate, and a Group III-V compound semiconductor is grown on the monocrystalline substrate.
    Type: Grant
    Filed: August 30, 1988
    Date of Patent: February 28, 1989
    Assignee: Nippon Telegraph & Telephone Corporation
    Inventors: Hidefumi Mori, Nobuyori Tsuzuki, Mitsuo Yamamoto
  • Patent number: 4801557
    Abstract: Chemical vapor deposition of III-V and II-VI binary, ternary and quaternary compounds is facilitated by maintaining a relatively high flow rate of reactants and modulating the rate of flow by alternately directing the flow at the high rate into a reactor for use and then directing the flow to a vent. Growth rates of the order of 25 Angstroms per minute were achieved in the epitaxial growth of indium phosphide by flow-rate modulation. This produced crystals of device quality having measured carrier mobilities of 2850-3600. In the case of epitaxial growth of ternary and quaternary compounds, improved control of deposition rates is achieved by applying flow-rate modulation to the compound carriers of each of the Group V and VI elements.
    Type: Grant
    Filed: June 23, 1987
    Date of Patent: January 31, 1989
    Assignee: Northwestern University
    Inventors: Bruce W. Wessels, Pei-Jih Wang
  • Patent number: 4800173
    Abstract: Process for producing a valence electron controlled functional crystalline film by introducing (i) a film forming gaseous raw material, (ii) a halogen series gaseous oxidizing agent to oxidize the raw material (i), and (iii) a gaseous raw material to impart a valence electron controlling agent separtely into a reaction region of a film deposition space and chemically reacting them to generate plural kinds of precursors containing excited precursors and to let at least one kind of said precursors to act as a film forming supplier whereby said crystalline film is formed on a selected substrate being kept at a predetermined temperature in the film deposition space.
    Type: Grant
    Filed: February 18, 1987
    Date of Patent: January 24, 1989
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Kanai, Junichi Hanna, Isamu Shimizu
  • Patent number: 4748135
    Abstract: A method of manufacturing a semiconductor device including the step of depositing from the vapor layers on a substrate in the chamber of a reactor in which a vector gas and a reactant gas are introduced, characterized in that the vector gas and the reactant gas are introduced into the chamber of the reactor by means of a system of three coaxial tubes, the first of which (the inner tube) has a diameter smaller than that of the second tube (the intermediate tube), which in turn has a diameter smaller than that of the third tube (the outer tube), the first ends of these tube being independent, but the second ends thereof situated in the proximity of each other cooperating with each other so as to form a valve controlling the introduction of the reactant gas into the hot zone of the chamber of the reactor mixed with a vector gas, these tubes being disposed in such a manner that: the said second end of the inner tube merges into the intermediate tube, the said second end of the intermediate tube provided with a re
    Type: Grant
    Filed: May 27, 1987
    Date of Patent: May 31, 1988
    Assignee: U.S. Philips Corp.
    Inventor: Peter M. Frijlink
  • Patent number: 4745088
    Abstract: The vapor phase growth on semiconductor wafers is carried out by an apparatus in which a multiplicity of semiconductor wafers are held by a holder so that the semiconductor wafers lie one over another in a vertical direction, and are rotated together with the holder, the holder is placed in a heater disposed in a reaction vessel, a raw material gas supply nozzle and a raw material gas exhaust nozzle are provided within the heater so that the semiconductor wafers are interposed between the gas supply nozzle and the gas discharge nozzle, and the gas supply nozzle and the gas discharge nozzle have gas supply holes and gas discharge holes, respectively, so that a raw material gas can flow on each semiconductor wafer in horizontal directions. When the temperature of the heater is raised by a heating source to heat the semiconductor wafers, the raw material gas is supplied from the gas supply holes to each semiconductor wafer, and thus a uniform layer is grown on each semiconductor wafer from the raw material gas.
    Type: Grant
    Filed: February 19, 1986
    Date of Patent: May 17, 1988
    Assignees: Hitachi, Ltd., Kokusai Elect. Co. Ltd.
    Inventors: Yosuke Inoue, Takaya Suzuki, Masahiro Okamura, Noboru Akiyama, Masato Fujita, Hiroo Tochikubo, Shinya Iida
  • Patent number: 4704786
    Abstract: A lateral bipolar transistor is described incorporating at least two grooves extending from the upper surface and spaced apart by a predetermined amount from which impurities are introduced to form an emitter region extending from the sidewall of one groove and a collector region extending from the sidewall of an adjacent groove with the base being the substrate material between the two regions. A plurality of grooves may be utilized to form a plurality of transistors with the grooves staggered to facilitate access to the ends of the grooves functioning as emitters and those functioning as collectors. The large vertical junction area formed by the side walls relative to the horizontal junction area at the bottom of the grooves and the uniform base width result in a high current gain lateral transistor.
    Type: Grant
    Filed: September 23, 1985
    Date of Patent: November 10, 1987
    Assignee: Westinghouse Electric Corp.
    Inventor: Francis J. Kub