Abstract: A semiconductor body main include a III-V compound semiconductor material having a p-conductive region doped with a p-dopant. The p-conductive region may include at least one first section, one second section, and one third section. The second section may be arranged between the first and third sections. The second section may directly adjoin the first and third sections. An indium concentration of at least one of the sections differs from an indium concentration of the other two sections.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

Abstract: A semiconductor device includes: a first semiconductor layer; a second semiconductor layer including a first dopant of a first conductivity type and a second dopant of a second conductivity type, wherein the first dopant has a doping concentration, and the first conductivity type is different from the second conductivity type; a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer includes a third dopant including a doping concentration higher than the doping concentration of the first dopant; and an active region between the first semiconductor layer and the second semiconductor layer; wherein the second semiconductor layer includes a bottom surface facing the active region, and the active region includes a top surface facing the second semiconductor layer, and a distance between the bottom surface of the second semiconductor layer and the top surface of the active region is not less than 2 nm.

Abstract: Photodetectors and methods for dual band photo detection are disclosed. The photodetector includes a stack of semiconductor layers defining first and second unipolar photosensitive modules (UPMs) of respectively opposite doping polarities, and a contact layer including at least one of metal and semiconductor materials having doping polarity opposite to that of the second UPM. The first and second UPMs are adapted for sensing radiation of different respective first and second wavelengths ranges. The second UPM is located upon the first UPM thereby forming a first diode junction between the first and second UPMs. The contact layer is located on the second UPM thereby forming a second diode junction between the second UPM and the contact layer. The first and second diode junctions are configured to have respectively opposite conduction directions, enabling selective sensing of electrical signals associated with the first and second wavelengths ranges.

Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer. The p-type semiconductor layer includes a first p-side layer, a second p-side layer, and a third p-side layer. A concentration profile of Mg of a p-side region includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion and a seventh portion. The p-side region includes the light emitting layer, the second p-side layer, and the third p-side layer. A Mg concentration of the sixth portion is not less than 1×1020 cm?3 and not more than 3×1020 cm?3. The Al concentration is 1/100 of the maximum value at a second position. A Mg concentration at the second position is not less than 2×1018 cm?3.

Abstract: High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a source electrode, a gate electrode, a drain electrode, a channel formation layer including at least a 2-dimensional electron gas (2DEG) channel, a channel supplying layer for forming the 2DEG channel in the channel formation layer, a portion of the channel supplying layer including a first oxygen treated region. The channel supplying layer may include a second oxygen treated region that extends from the first oxygen treated region towards the drain electrode, and the depth and concentration of oxygen of the second oxygen treated region may be less than those of the first oxygen treated region.

Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a bather layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

Abstract: A transistor with source and drain electrodes formed in contact with an active region and a gate between the source and drain electrodes and in contact with the active region. A first spacer layer is on at least part of the active region surface between the gate and drain electrodes and between the gate and source electrodes. The gate comprises a generally t-shaped top portion that extends toward the source and drain electrodes. A field plate is on the spacer layer and under the overhang of at least one section of the gate top portion. The field plate is at least partially covered by a second spacer layer that is on at least part of the first active layer surface and between the gate and drain and between the gate and source. At least one conductive path electrically connects the field plate to the source electrode or the gate.

Abstract: According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer.

Abstract: A semiconductor device includes a first semiconductor layer formed on a substrate, the first semiconductor containing an impurity element; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; and a gate electrode, a source electrode and a drain electrode that are formed on the third semiconductor layer. In the semiconductor device, the second semiconductor layer includes an impurity diffusion region in which an impurity element contained in the first semiconductor layer is diffused, the impurity diffusion region being located directly beneath the gate electrode and being in contact with the first semiconductor layer, and the impurity element causes the impurity diffusion region to be a p-type impurity diffusion region.

Abstract: Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.

Abstract: Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer to surround the fluorescent layer; and a lens disposed on the light emitting device and supported by the substrate, wherein the lens includes a lens body having a first recess formed at a center of a top surface of the lens body and a second recess formed at a center of a bottom surface of the lens body, and a lens supporter provided at the bottom surface of the lens body to support the lens body such that the lens body is spaced apart from the substrate.

Abstract: Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.

Abstract: Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.

Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide.

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.

Abstract: Semiconductor regions are alternately arranged in a parallel pn layer in which an n-type region and a p-type region are alternately arranged parallel to the main surface of a semiconductor substrate. Pitch between n drift region and p partition region of a second parallel pn layer in an edge termination region is two thirds of pitch between n drift region and p partition region of a first parallel pn layer in an active region. At boundaries between main SJ cells and fine SJ cells at four corners of the semiconductor substrate having rectangular shape in plan view, ends of two pitches of main SJ cells face the ends of three pitches of fine SJ cells. In this way, it is possible to reduce the influence of a process variation and thus reduce mutual diffusion between n drift region and p partition region of the fine SJ cell.

Abstract: A semiconductor light emitting device (10) comprises a semiconductor structure (12) comprising a first body (14) of a first semiconductor material (in this case Ge) comprising a first region of a first doping kind (in this case n) and a second body (18) of a second semiconductor material (in this case Si) comprising a first region of a second doping kind (in this case p). The structure comprises a junction region (15) comprising a first heterojunction (16) formed between the first body (14) and the second body (18) and a pn junction (17) formed between regions of the structure of the first and second doping kinds respectively. A biasing arrangement (20) is connected to the structure for, in use, reverse biasing the pn junction, thereby to cause emission of light.

Abstract: Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

Abstract: A high operating temperature split-off band infrared (SPIP) detector having a double and/or graded barrier on either side of the emitter is provided. The photodetector may include a first and second barrier and an emitter disposed between the first and second barriers so as to form a heterojunction at each interface between the emitter and the first and second barriers, respectively. The emitter may be of a first semiconductor material having a split-off response to optical signals, while one of the first or the second barriers may include a double barrier having a light-hole energy band level that is aligned with the split-off band energy level of the emitter. In addition, the remaining barrier may be graded.

Abstract: A semiconductor device may include a semiconductor buffer layer having a first conductivity type and a semiconductor mesa having the first conductivity type on a surface of the buffer layer. In addition, a current shifting region having a second conductivity type may be provided adjacent a corner between the semiconductor mesa and the semiconductor buffer layer, and the first and second conductivity types may be different conductivity types. Related methods are also discussed.

Abstract: A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.

Abstract: The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.

Abstract: A field-effect transistor according to the present invention includes a silicon substrate that has a resistivity of not more than 0.02 ?·cm, a channel layer that is formed on the silicon substrate and has a thickness of at least 5 ?m, a barrier layer that is formed on the channel layer and supplies the channel layer with electrons, a two dimensional electron gas layer that is formed by a hetero junction between the channel layer and the barrier layer, a source electrode and a drain electrode that each form an ohmic contact with the barrier layer, and a gate electrode that is formed between the source electrode and the drain electrode, and forms a Schottky barrier junction with the barrier layer.

Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

Abstract: A nitride semiconductor device has a nitride semiconductor layer structure. The structure includes an active layer of a quantum well structure containing an indium-containing nitride semiconductor. A first nitride semiconductor layer having a band gap energy larger than that of the active layer is provided in contact with the active layer. A second nitride semiconductor layer having a band gap energy smaller than that of the first layer is provided over the first layer. Further, a third nitride semiconductor layer having a band gap energy larger than that of the second layer is provided over the second layer.

Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.

Abstract: The present invention relates to a light-emitting device using a clad layer consisting of asymmetric units, wherein the clad layer is provided by repeatedly stacking a unit having an asymmetric energy bandgap on upper and lower portions of an active layer, and the inflow of both electrons and holes into the active layer is arbitrarily controlled through the clad layer, so that the internal quantum efficiency can be improved. The light-emitting device using the clad layer consisting of the asymmetric units according to the present invention is characterized in that the clad layer is provided on at least one of the upper and lower portions of the active layer and consists of one or plural units, wherein the unit has a structure in which the first to nth unit layers (n is a natural number equal to or greater than three) having different energy bandgaps are sequentially stacked and has an asymmetric energy band diagram.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a buffer layer over a substrate, the buffer layer containing a first compound semiconductor that includes elements from one of: III-V families of a periodic table; and II-VI families of the periodic table. The method includes forming a channel layer over the buffer layer. The channel layer contains a second compound semiconductor that includes elements from the III-V families of the periodic table. The method includes forming a gate over the channel layer. The method includes depositing impurities on regions of the channel layer on either side of the gate. The method includes performing an annealing process to activate the impurities in the channel layer.

Abstract: A transistor comprising an active region, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region. A first spacer layer is on at least part of the surface of the active region between the gate and the drain electrode and between the gate and the source electrode. The gate comprises a generally t-shaped top portion that extends toward the source and drain electrodes. A field plate is on the spacer layer and under the overhand of at least one section of the gate top portion. The field plate is at least partially covered by a second spacer layer, with the second spacer layer on at least part of the surface of the first active layer and between the gate and the drain and between the gate and the source. At least one conductive path electrically connects the field plate to the source electrode or the gate.

Abstract: Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.

Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.

Abstract: A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.

Abstract: To provide a nitride semiconductor crystal, comprising: laminated homogeneous nitride semiconductor layers, with a thickness of 2 mm or more, wherein the laminated homogeneous nitride semiconductor layers are constituted so that a nitride semiconductor layer with low dopant concentration and a nitride semiconductor layer with high dopant concentration are alternately laminated by two cycles or more.

Abstract: Disclosed are methods for manufacturing semiconductor devices and the devices thus obtained. In one embodiment, the method comprises obtaining a semiconductor substrate comprising a germanium region doped with n-type dopants at a first doping level and forming an interfacial silicon layer overlying the germanium region, where the interfacial silicon layer is doped with n-type dopants at a second doping level and has a thickness higher than a critical thickness of silicon on germanium, such that the interfacial layer is at least partially relaxed. The method further includes forming over the interfacial silicon layer a layer of material having an electrical resistivity smaller than 1×10?2 ?cm, thereby forming an electrical contact between the germanium region and the layer of material, wherein the electrical contact has a specific contact resistivity below 10?4 ?cm2.

Abstract: In a MOS-type semiconductor device in which, on a Si substrate (201), a SiGe layer (202) having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer and a mobility larger than a mobility of the first semiconductor layer, a Si cap layer (203), and an insulating layer (204) are sequentially laminated, the problem of the shift of the absolute value of the threshold voltage toward a smaller value caused by negative fixed charges formed in or near the interface between the Si cap layer (203) and the insulting film (204) by diffusion of Ge is overcome by neutralizing the negative fixed charges by positive charges induced in and near the interface between the Si cap layer and the insulating film along with addition of nitrogen atoms to the semiconductor device surface by NO gas annealing and thereby shifting the threshold voltage toward a larger value.

Abstract: A nitride semiconductor device includes: a semiconductor base layer made of a conductive group III nitride semiconductor having a principal plane defined by a nonpolar plane or a semipolar plane; an insulating layer formed on the principal plane of the semiconductor base layer with an aperture partially exposing the principal plane; a nitride semiconductor multilayer structure portion, formed on a region extending onto the insulating layer from the aperture, having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a +c-axis side first inclined surface and a ?c-axis side second inclined surface inclined with respect to the principal plane of the semiconductor base layer and including two types of group III nitride semiconductor layers at least having different lattice constants; a gate electrode formed to be opposed to the second inclined surface; a source electrode arranged to be electrically connected with the group III nitride semiconductor layers; and a drain ele

Abstract: A power transistor includes a first terminal, a second terminal and a control terminal. A support layer is formed of a first material having a first bandgap. An active region is formed of a second material having a second bandgap wider than the first bandgap, and is disposed on the support layer. The active region is arranged to form part of a current path between the first and second terminal in a forward mode of operation. The active region includes at least one pn-junction.

Abstract: There is provided a high-performance compound semiconductor epitaxial wafer that has an improved linearity of the voltage-current characteristic, a producing method thereof, and a judging method thereof. Provided is a semiconductor wafer including a compound semiconductor that produces a two-dimensional carrier gas, a carrier supply semiconductor that supplies a carrier to the compound semiconductor, and a mobility lowering semiconductor that is disposed between the compound semiconductor and the carrier supply semiconductor and that has a mobility lowering factor that makes the mobility of the carrier in the mobility lowering semiconductor lower than the mobility of the carrier in the compound semiconductor.

Abstract: A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer.

Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.

Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

Abstract: A photodetector for detecting infrared light in a wavelength range of 3-25 ?m is disclosed. The photodetector has a mesa structure formed from semiconductor layers which include a type-II superlattice formed of alternating layers of InAs and InxGa1-xSb with 0?x?0.5. Impurity doped regions are formed on sidewalls of the mesa structure to provide for a lateral conduction of photo-generated carriers which can provide an increased carrier mobility and a reduced surface recombination. An optional bias electrode can be used in the photodetector to control and vary a cut-off wavelength or a depletion width therein. The photodetector can be formed as a single-color or multi-color device, and can also be used to form a focal plane array which is compatible with conventional read-out integrated circuits.

Abstract: A GaN heterojunction FET has an AlxGa1-xN first graded layer and an AlyGa1-yN second graded layer, which are formed sequentially on a channel layer. The Al mole fraction x of the first graded layer decreases linearly from, for example, 0.2 at an interface of the first graded layer with the channel layer to 0.1 at an interface thereof with the second graded layer. The Al mole fraction y of the second graded layer increases from, for example, 0.1 at an interface of the second graded layer with the first graded layer to 0.35 at a surface located on the opposite side from the first graded layer. Because the intrinsic polarization of AlGaN depends on the Al mole fraction, fixed negative charge is generated in the AlxGa1-xN first graded layer, and fixed positive charge is generated in the AlyGa1-yN second graded layer.

Abstract: A photo-detector with a reduced G-R noise comprises two n-type narrow bandgap layers surrounding a middle barrier layer having an energy bandgap at least equal to the sum of the bandgaps of the two narrow bandgap layers. Under the flat band conditions the conduction band edge of each narrow bandgap layer lies below the conduction band edge of the barrier layer by at least the bandgap energy of the other narrow bandgap layer. When biased with an externally applied voltage, the more negatively biased narrow bandgap layer is the contact layer and the more positively biased narrow bandgap layer is the photon absorbing layer.

Abstract: A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

Abstract: A light-emitting diode device (LED) device and manufacturing methods thereof are provided, wherein the LED device comprises a substrate, a first n-type semiconductor layer, an n-type three-dimensional electron cloud structure, a second n-type semiconductor layer, an active layer and a p-type semiconductor layer. The first n-type semiconductor layer, the n-type three-dimensional electron cloud structure, the second n-type semiconductor layer, the active layer and the p-type semiconductor layer are subsequently grown on the substrate.