Abstract: A method of manufacturing a mask, includes forming an organic material layer on a mask substrate and patterning a hard mask on the organic material layer, etching the organic material layer to form a mask sheet including through holes, removing the hard mask on the mask sheet, forming a conductive material layer on the mask sheet, and etching the conductive material layer to form a conductive layer.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device including a semiconductor region over a bulk oxide, which is over a semiconductor substrate. Above the bulk oxide is a lower source region that is laterally spaced from a lower drain region by a lower portion of the semiconductor region. An upper source region is laterally spaced from an upper drain region by an upper portion of the semiconductor region and is vertically spaced from the lower source region and the lower drain region. The upper source region is coupled to the lower source region, and the upper drain region is coupled to the lower drain region. A gate electrode, coupled to the semiconductor substrate and over a gate oxide, is above the upper portion of the semiconductor region. The lower and upper portions of the semiconductor region respectively include a first channel region and a second channel region.

Abstract: A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.

Abstract: Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings.

Abstract: A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: Various embodiments provide a method for processing a carrier, the method including changing the three-dimensional structure of a mask layer arranged over the carrier so that at least two mask layer regions are formed having different mask layer thicknesses; and applying an ion implantation process to the at least two mask layer regions to form at least two implanted regions in the carrier having different implantation depth profiles.

Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.

Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.

Abstract: According to the embodiment, a storage device includes row lines arranged parallel to one another, column lines arranged parallel to one another to intersect with the row lines, and a memory cell disposed at each of intersections of the row lines and the column lines and including a resistance-change element and a diode connected in series to the resistance-change element. The diode includes a stack of a first semiconductor region containing an impurity of a first conductivity type, a second semiconductor region containing an impurity of the first conductivity type lower in concentration than in the first semiconductor region, and a third semiconductor region containing an impurity of a second conductivity type. An impurity concentration in the second semiconductor region of the diode in a first adjacent portion adjacent to the first semiconductor region is higher than that in a second adjacent portion adjacent to the third semiconductor region.

Abstract: A method of fabricating a semiconductor device includes the following steps. At first, a semiconductor substrate is provided. A gate stack layer is formed on the semiconductor substrate, and the gate stack layer further includes a cap layer disposed thereon. Furthermore, two first spacers surrounding sidewalls of the gate stack layer is further formed. Subsequently, the cap layer is removed, and two second spacers are formed on a part of the gate stack layer. Afterwards, a part of the first spacers and the gate stack layer not overlapped with the two second spacers are removed to form two gate stack structures.

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.

Abstract: A compound semiconductor device includes a substrate; and a compound semiconductor layer disposed over the substrate, wherein the compound semiconductor layer includes a first region having first conductivity-type carriers generated by activating a first impurity and also includes a second region having carriers at lower concentration as compared to the first region, the carriers being generated by activating a second impurity which is the same type as the first impurity.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A power semiconductor component having a pn junction, a body with a first basic conductivity, a well-like region with a second conductivity which is arranged horizontally centrally in the body, has a first two-level doping profile and has a first penetration depth from the first main surface into the body. In addition, this power semiconductor component has an edge structure which is arranged between the well-like region and the edge of the power semiconductor component and which comprises a plurality of field rings with a single-level doping profile, a second conductivity and a second penetration depth, wherein the first penetration depth is no more than about 50% of the second penetration depth.

Abstract: A diode includes a first region having a first conductive type impurity and formed in a first well having the first conductive type impurity, a second region formed in the first well and having a second conductive type impurity, and a semiconductor pattern disposed above the first well and including a first portion having the first conductive type impurity and a second portion having the second conductive type impurity. The first region and the first portion are coupled with an anode, and the second region and the second portion are coupled with a cathode.

Abstract: A semiconductor device with a number of integrated coils is disclosed. In one embodiment, a first coil portion and a second coil portion are at least in part overlapping each other. Another embodiment provides a process for manufacturing a semiconductor device having at least the processes of generating a first coil portion, generating a second coil portion, wherein at least a part of the first coil portion and a part of the second coil portion are overlapping each other.

Abstract: In order to provide an adhesive composition for electronic components that is excellent in adhesion durability under long-term high temperature conditions, thermal cyclability, and insulation reliability, designed is an adhesive composition for electronic components containing a thermoplastic resin (a), an epoxy resin (b), a hardener (c), and an organopolysiloxane (d), wherein the glass transition temperature (Tg) after curing is ?10° C. to 50° C. and the rate of change of Tg after heat-treating the composition at 175° C. for 1000 hours is 15% or less.

Abstract: A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.

Abstract: Provided are a display device in which variation in output characteristics of the photodiode is suppressed, and a method for manufacturing the display device. The display device is provided with the active matrix substrate (2) and photodiode (6). First, on a substrate of glass (12), a silicon film (8) and an interlayer insulation film (15) for covering the silicon film (8) are formed in this order. Then, a metal film is formed, and metal lines (10, 11) traversing the silicon film (8) are formed by etching the metal film. Then, p-type impurity ions are implanted by using a mask that has an opening (24a) that exposes a portion that overlaps a region where a p-layer (9a) is to be formed, a part of the opening (24a) being formed with the metal line (10). Furthermore, n-type impurity ions are implanted by using a mask that has an opening (25b) that exposes a portion that overlaps a region where an n-layer (9c) is to be formed, a part of the opening (25a) being formed with the metal line (11).

Abstract: A power semiconductor component having a pn junction, a body with a first basic conductivity, a well-like region with a second conductivity which is arranged horizontally centrally in the body, has a first two-level doping profile and has a first penetration depth from the first main surface into the body. In addition, this power semiconductor component has an edge structure which is arranged between the well-like region and the edge of the power semiconductor component and which comprises a plurality of field rings with a single-level doping profile, a second conductivity and a second penetration depth, wherein the first penetration depth is no more than about 50% of the second penetration depth.

Abstract: Provided is a semiconductor device with a high breakdown voltage yield of a bipolar transistor and a high bandwidth and quantum efficiency of a light receiving element. An optical semiconductor device includes monolithically integrated transistor and light receiving element. The light receiving element includes a p-type semiconductor layer, an n-type epitaxial layer formed on the p-type semiconductor layer, and an n-type diffusion layer formed on the n-type epitaxial layer. An n-type impurity concentration of the n-type diffusion layer is 3×1018 cm?3 or less at a depth of 0.12 ?m or more below a surface of the n-type diffusion layer, 1×1016 cm?3 or more at a depth of 0.4 ?m or less below the surface, and 1×1016 cm?3 or less at a depth of 0.8 ?m or more below the surface, and an interface between the p-type semiconductor layer and the n-type epitaxial layer is located at a depth of 0.9 ?m to 1.5 ?m below the surface.

Abstract: A semiconductor substrate, of GaAs with a semiconductor layer sequence applied on top of the substrate. The semiconductor layer sequence comprises a plurality of semiconductor layers of Al1-yGayAs1-xPx with 0?x?1 and 0?y?1. A number of the semiconductor layers respectively comprising a phosphorus component x which is greater than in a neighboring semiconductor layer lying thereunder in the direction of growth of the semiconductor layer sequence. Two semiconductor layers directly preceding the uppermost semiconductor layer of the semiconductor layer sequence have a smaller lattice constant than the uppermost layer.

Abstract: A semiconductor component has a first and a second contact-making region, and a semiconductor volume arranged between the first and the second contact-making region. Within the semiconductor volume, it is possible to generate a current flow that runs from the first contact-making region to the second contact-making region, or vice versa. The semiconductor volume and/or the contact-making regions are configured in such a way that the local flow cross-section of a locally elevated current flow, which is caused by current splitting, is enlarged at least in partial regions of the semiconductor volume.

Abstract: A thinned wafer having stress dispersion parts that make the wafer resistant to warpage and a method for manufacturing a semiconductor package using the same is described. The wafer includes a wafer body having a semiconductor chip forming zone and a peripheral zone located around the semiconductor chip forming zone; and the stress dispersion parts are located in the peripheral zone so as to disperse stress induced in the peripheral zone and the semiconductor chip forming zone.

Abstract: A semiconductor device includes a stepwise impurity layer provided at one of an anode portion and an cathode portion of the semiconductor device by introducing an impurity of a predetermined conduction type from a major surface of the semiconductor substrate through to a first depth to provide a first region of the semiconductor substrate having the impurity of the predetermined conduction type introduced therein. The predetermined conduction type is a same conduction type as a conduction type of the one of the anode portion and the cathode portion. The stepwise impurity layer is further provided by melting a second, predetermined region of the semiconductor substrate having a second depth deeper than the first depth and including the first region to make uniform the impurity of the predetermined conduction type in a concentration from the major surface through to the second depth to provide a uniform stepwise impurity concentration profile.

Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.

Abstract: A semiconductor device formed by decreasing thickness of a substrate by grinding, and performing ion implantation. In a diode in which a P anode layer and an anode electrode are formed at a side of a right face of an N? drift layer, and an N+ cathode layer and a cathode electrode are formed at a side of a back face of the N? drift layer, an N cathode buffer layer is formed thick compared with the N+-type cathode layer between the N?-type drift layer and the N+ cathode layer, the buffer layer being high in concentration compared with the N? drift layer, and low compared with the N+ cathode layer. When a reverse bias voltage is applied, a depletion layer is stopped in the middle of the N cathode buffer layer, and thus prevented from reaching the N+ cathode layer, so that the leakage current is suppressed.

Abstract: A vertical semiconductor device comprises a semiconductor body, a first contact and a second contact, wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of a second conductivity type are formed in the semiconductor body in a direction from the first contact to the second contact, wherein a basic doping density of the second semiconductor region is smaller than a doping density of the third semiconductor region, and wherein in the second semiconductor region a semiconductor zone of the second conductivity type is arranged in which the doping density is increased relative to the basic doping density of the second semiconductor region.

Abstract: A semiconductor diode has an anode, a cathode and a semiconductor volume provided between anode and cathode. A plurality of semiconductor zones are formed in the semiconductor volume, which semiconductor zones are inversely doped with respect to their immediate surroundings, spaced apart from one another and provided in the vicinity of the cathode. The semiconductor zones are spaced apart from the cathode.

Abstract: The present invention provides a constitution of n-type ohmic electrode suitable for n-type group III nitride semiconductor, and a forming method thereof for providing low contact resistivity. The n-type ohmic electrode is provided to comprise an alloy of aluminum and lanthanum or comprises lanthanum at the junction interface with the n-type group III nitride semiconductor. The method comprising forming a lanthanum-aluminum alloy layer at 300° C. or less to form an n-type ohmic electrode enriched in lanthanum at the junction interface.

Abstract: A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. The channel is formed near the interface between the channel layer and the carrier supply layer or depleted, the carrier supply layer has a band gap energy greater than that of the channel layer, and x in the formula AlxGa1-xN decreases monotonically with an increase in the distance from the interface. The channel layer may be crystalline of gallium nitride. The channel layer may be undoped. X of the formula AlxGa1-xN of the carrier supply layer is greater than or equal to 0.15 and less than or equal to 0.40 at the interface.

Abstract: A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold voltage control layer for controlling a threshold voltage formed in the portion of the well region which is located below the gate electrode and in which an impurity of the first conductivity type has a concentration peak at a position shallower than in the well region, an extension region having a second conductivity type and formed in the well region to be located between each of the respective portions of the well region which are located below the both end portions in the gate-length direction of the gate electrode and the threshold voltage control layer, and source and drain regions each having the second conductivity type and formed outside the extension layer in connected relation thereto.

Abstract: Disclosed herein is a method of manufacturing a flash memory device.

Abstract: A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in size by means of an etching method. In another embodiment, the semiconductor body is partially removed in a region outside the first semiconductor zone. At least one second semiconductor zone is then fabricated in the partially removed region.

Abstract: An over-voltage protection device includes a substrate including an upper surface and a lower surface; a first electrode provided on the upper surface of the substrate; a second electrode provided on the lower surface on the substrate; a first conductive layer overlying the lower surface of the substrate, the first conductive region being a conductive region of a first type; a plurality of first conductive regions provided proximate the upper surface of the substrate, the plurality of first conductive regions being conductive regions of the first type; and a plurality of second conductive region provided proximate the upper surface of the substrate, the plurality of second conductive region being conductive regions of a second type. The plurality of the first conductive regions are provided in an alternating manner with the plurality of second conductive regions. The first electrode is contacting the plurality of the first and second conductive regions.

Abstract: Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of the anode electrode and the cathode electrode. A ratio of the peak impurity concentration Np to an averaged impurity concentration Ndm in the n-drift layer is in the range of 1 to 5. This provides a diode and a manufacturing method thereof by which oscillations in voltage and current at reverse recovery are inhibited to achieve enhancement both in high speed and low-loss characteristics and in soft recovery characteristics.

Abstract: A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by a channel stop layer.

Abstract: Described is an electronic device comprising a junction formed between a first fullerene layer having a first doping concentration and a second fullerene layer having a second doping concentration different from the first doping concentration. The first doping concentration may be zero. The first and/or the second fullerene layer may be a monolayer. The second fullerene layer may comprise an electron donor. One example of such a device is a diode wherein the first fullerene layer is connected to an anode and the second fullerene layer is connected to a cathode. Another example is a field effect transistor wherein the first fullerene layer serves as a gate region and the second fullerene layer serves as a channel region. The second fullerene layer may alternatively comprise an electron acceptor. At least one of the first and second fullerene layers may be formed from C60, or may consist of a single bucky ball.

Abstract: A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Abstract: A semiconductor device includes a semiconductor chip, and a circuit substrate disposed such that the circuit substrate faces the semiconductor chip and is electrically connected to the semiconductor chip through a connection conductor. A pad electrode and a terminal electrode are formed on a surface of the semiconductor chip and a surface of the circuit substrate, respectively. The connection conductor is connected between the pad electrode and the terminal electrode. The surface of the semiconductor and the surface of the circuit substrate face each other. A conductive dummy pattern is formed on the facing surface of the semiconductor chip or the circuit substrate. A space between the facing surfaces is filled with nonconductive resin. With this arrangement, it is possible to make uniform the temperature distribution between the facing surfaces, thereby making the temperature and the viscosity of the nonconductive resin uniform to reduce attenuation of ultrasonic waves.

Abstract: In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate.

Abstract: A semiconductor system (200), particularly a diode, having a p-n junction is proposed, that is formed as a chip having an edge area, which includes a first layer (2) of a first conductivity type and a second layer (1, 3) of a second conductivity type; the second layer (1, 3) including at least two sublayers (1, 3); both sublayers (1, 3) forming a p-n junction with the first layer (2); the p-n junction of the first layer (2) with the first sublayer (3) being provided exclusively in the interior of the chip, and the p-n junction between the first layer (2) and the second sublayer (1) being provided in the edge area of the chip; for each cross-section of the chip area parallel to the chip plane, the first sublayer (3) corresponding only to a part of such a cross-section.

Abstract: A bipolar p-i-n diode has a first (1) and second (5) region of opposite conductivity type and an intermediate drift region (3) between the first and second regions. Trenched field relief regions (14) are arranged to deplete the intermediate drift region (3) when the diode is reverse biased, so permitting a higher doping (12) to be used for the intermediate drift region (3) for a given breakdown voltage. This improves both the turn-on and turn-off characteristics of the diode.

Abstract: An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

Abstract: Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies between different layers of a multiple layer device. In a preferred embodiment, the variations are such that the field strength is substantially constant along any horizontal or vertical cross section of the termination region.

Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

Abstract: A semiconductor device comprises a semiconductor element mounted on a first surface of a wiring substrate, and a plurality of conductive land portions formed and exposed at a second surface of the wiring substrate which is opposite to the first surface. A plurality of solder balls are respectively joined to the plurality of conductive land portions. A plurality of reinforcement resin film portions are formed to reinforce coupling between the solder balls and the conductive land portions. Each of the reinforcement resin film portions is formed around a portion of the solder ball joining to the conductive land portion. Each of the reinforcement resin film portions being bent to form a portion along the wiring substrate and a portion along the side surface of the solder ball. The coupling between the solder balls and the conductive land portions is reinforced by elastic force of the bent portions of the reinforcement resin film portions.