Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.

Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.

Abstract: Electrodeposited copper foils having adequate puncture strength to withstand both pressure application during consolidation with negative electrode active materials during manufacture, as well as expansion/contraction during repeated charge/discharging cycles when used in a rechargeable secondary battery are described. These copper foils find specific utility as current collectors in rechargeable secondary batteries, particularly in lithium secondary battery with high capacity. Methods of making the copper foils, methods of producing negative electrode for use in lithium secondary battery and lithium secondary battery of high capacity are also described.

Abstract: A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.

Abstract: A signal processing board includes a six-layer substrate in which six wiring layers are stacked, and a first semiconductor element and a second semiconductor element mounted on the outer surface of a first layer of the six wiring layers. A plurality of signal transmission patterns are formed in the first layer, a third layer, a fourth layer, and a sixth layer of the six wiring layers. A first ground pattern is formed in a second layer. A second ground pattern is formed in a fifth layer. A first power supply pattern is formed in one of the fourth layer, the fifth layer, and the sixth layer. A second power supply pattern is formed in one of the fourth layer, the fifth layer, and the sixth layer.

Abstract: A semiconductor chip is provided on a semiconductor circuit base on one surface of an insulating substrate. A reinforcement and balance base is provided on the one surface of the insulating substrate spaced to the semiconductor circuit base. The insulating substrate 4, the semiconductor circuit base, the semiconductor chip, and the reinforcement and balance base are sealed into a resin-molded sealing body. The sealing body has resin non-adhering portions.

Abstract: A semiconductor device includes: a single die pad made of a metal or metal alloy and having a first surface, a second surface that is an opposite side of the first surface, and a pair of ground leads protruding from an end edge in plan view; a signal lead arranged between the ground leads; a plurality of leads arranged around the die pad in plan view; a semiconductor chip mounted on the second surface; bonding wires connecting a signal pad of the chip and the signal lead and connecting a ground pad of the chip and the ground leads; and a mold resin covering the die pad, the signal lead, the plurality of leads, the chip, and the bonding wires; wherein an interval between the signal lead and each of the ground leads is narrower than an interval between the plurality of leads.

Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.

Abstract: A semiconductor device package includes a leadless leadframe, and a plurality of terminal pads extending to a periphery of the leadframe. At least two of the plurality of terminal pads are interior extending terminal pads that include an interior portion having a shape including at least one curved portion and an exterior portion that extends to the periphery of the leadframe. An integrated circuit (IC) die having at least a semiconductor surface includes circuitry configured for at least one function having nodes connected to bond pads on the leadframe. There is a bonding arrangement between the plurality of terminal pads and the bond pads. A mold compound is for encapsulation of the semiconductor device package.

Abstract: A package is disclosed. In one example, the package comprises a carrier, a semiconductor chip having a first connection area at which the semiconductor chip is mounted at a first vertical level on or above the carrier, and a connection body. The semiconductor chip is bent to thereby be connected at a second connection area of the semiconductor chip at a second vertical level, being different from the first vertical level, with the connection body.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.

Abstract: A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and a wire extending between the first electrode and the second electrode. The wire includes a first conductor in contact with the first electrode and the second electrode, and a second conductor that is provided inside the first conductor and has no contact with the first electrode and the second electrode.

Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

Abstract: A radio-frequency module including a mounting substrate that has mounting faces opposed to each other; a PA that is mounted on the mounting face, that is a radio-frequency component, and that has an emitter terminal; a through electrode that is connected to the emitter terminal of the PA and that passes through the mounting faces of the mounting substrate; and a ground terminal connected to the through electrode.

Abstract: This disclosure relates to a leadless packaged semiconductor device including a top and a bottom opposing major surfaces and sidewalls extending between the top and bottom surfaces, the leadless packaged semiconductor device further includes a lead frame structure including an array of two or more lead frame sub-structures each having a semiconductor die arranged thereon, and terminals and a track extended across the bottom surface of the semiconductor device. The track provides a region for interconnecting the semiconductor die and terminals, and the track is filled by an insulating material to isolate the lead frame sub-structures.

Abstract: A semiconductor module includes a semiconductor switching element, a multiple of bases, on at least one of which the semiconductor switching element is mounted, a molded resin that seals the semiconductor switching element and the multiple of bases, a multiple of terminals formed integrally with each one of the multiple of bases and provided extending from an outer periphery side face of the molded resin, and a recessed portion or a protruding portion having a depth or a height such that creepage distance between the multiple of terminals is secured, and formed so as to cross an interval between the multiple of terminals, in one portion of the outer periphery side face of the molded resin between the multiple of terminals.

Abstract: A semiconductor package includes a die pad having a die attach surface, a first laterally separated and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and comprising a first terminal on an upper surface of the semiconductor die, an interconnect clip that is electrically connected to the first terminal and to the first lead, and a heat spreader mounted on top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends past an outer edge side of the die pad. The heat spreader covers an area of the first planar section that is larger than an area of the semiconductor die. The heat spreader laterally extends past a first outer edge side of the die pad that faces the first lead.

Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.

Abstract: A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer.

Abstract: An electronic device includes a package structure, a first lead and a second lead. The first lead has a first portion extending outward from a side of the package structure and downward, and a second portion extending outward from the first portion away from the package side. The second lead has a first portion extending outward from the package side and downward, and a second portion extending inward from the first portion toward the package side, and a distal end of the second lead is spaced from the package side.

Abstract: A sintered member is provided between a semiconductor chip and a terminal. The sintered member is made of a sinter sheet by heating and pressing the same. The semiconductor chip is connected to the terminal via the sintered member. Convex portions are formed at a front-side surface of the semiconductor chip. Concave portions, each of which has such a shape corresponding to that of each convex portion of the semiconductor chip, are formed at a surface of the sintered member facing to the semiconductor chip.

Abstract: A method for manufacturing a stack structure comprises: providing a lead frame having a metal frame, at least two metal plate portions and a plurality of connection ribs, the connection ribs each comprises a first end, a second end and a connection portion; directly mounting electronic components for constructing two modules on the metal plate portions; packaging the electronic components of the first module, the first ends of the metal connection components which are electrically connected to the first module and the first ends of the part of the connection ribs which are electrically connected to the first module are packaged therein; removing the metal frame and part or whole of the connection ribs, the remaining connection ribs forms pins; and bending the metal connection component so that the two modules connected by the metal connection components are stacked one upon the other, to form the stack structure.

Abstract: A package structure includes a metal member and a resin member. The metal member has an obverse surface facing one side in a first direction. The resin member is disposed in contact with at least a portion of the obverse surface. The obverse surface has a roughened area. The roughened area includes a plurality of first trenches recessed from the obverse surface, each of the first trenches having a surface with a greater roughness than the obverse surface. The plurality of first trenches extend in a second direction perpendicular to the first direction and are next to each other in a third direction perpendicular to the first direction and the second direction. The plurality of first trenches are filled up with the resin member.

Abstract: An electronic device includes a semiconductor die, an enclosure, leads extending outwardly from the enclosure and electrically connected to the semiconductor die, and wherein the leads have a reduced cross-sectional area along a longitudinal length of the lead. The electronic device is designed to reduce the occurrence of crack formation between the leads and a printed circuit board.

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.

Abstract: A method of frame handling during semiconductor package production includes: providing a lead frame having leads secured to a periphery of the lead frame by first tie bars; providing a multi-gauge spacer frame having spacers secured to a periphery of the spacer frame by second tie bars, the spacers being thicker than the second tie bars; and aligning the multi-gauge spacer frame with the lead frame such that the spacers and the second tie bars of the multi-gauge spacer frame do not contact the leads of the lead frame. A power semiconductor module and a method of assembling a power semiconductor module are also described.

Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.

Abstract: A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.

Abstract: A leadframe for a semiconductor device includes an array of electrically-conductive leads. The electrically-conductive leads have mutually opposed lateral (vertical) surfaces. An electrically-insulating material is formed over the mutually lateral opposed surfaces to prevent short circuits between adjacent leads. The electrically-insulating material may further be provided at one or more of the opposed bottom and top surfaces of the electrically-conductive leads of the leadframe.

Abstract: A package includes an integrated circuit that includes at least one active area and at least one secondary device area, a support configured to support the integrated circuit, and a die attach material. The integrated circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.

Abstract: An optoelectronic semiconductor component may include a housing having a recess, and a chip carrier which is a part of the housing. The chip carrier may have a first fastening side and an upper side. The optoelectronic semiconductor chip may be mounted on the upper side in the recess. First electrical contact pads for external electrical contacting may be located on the first fastening side. Furthermore, second electrical contact pads for external electrical contacting may be located on a second fastening side, opposite to the first fastening side, of the housing. First and second electrical contact pads electrically assigned to one another may be electrically short-circuited so that the semiconductor component can be electrically contacted by the first or by the second fastening side.

Abstract: A radio-frequency module is capable of being connected to an external substrate and includes a mounting substrate having a main face and a main face, which are opposed to each other, multiple ground terminals with which the mounting substrate is electrically connected to the external substrate, a PA mounted on the main face, and an LNA mounted on the main face. A communication apparatus includes the radio-frequency module.

Abstract: A power module including a carrier assembly and a power device disposed on the carrier assembly is provided. The carrier assembly includes a bottom board, a circuit board, a lead frame, and a pad group. The circuit board is disposed on the bottom board and includes a device mounting portion and an extending portion protruding from a side of the device mounting portion. The lead frame disposed on the bottom board includes a first conductive portion and a second conductive portion insulated from each other. The extending portion of the circuit board is disposed between the first and second conductive portions, and an upper surface of the lead frame is flush with a top surface of the extending portion. A pad group includes a first pad disposed on the extending portion, a second pad and a third pad respectively disposed on the first and second conductive portions.

Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.

Abstract: A radio-frequency module including a mounting substrate that has mounting faces opposed to each other; a PA that is mounted on the mounting face, that is a radio-frequency component, and that has an emitter terminal; a through electrode that is connected to the emitter terminal of the PA and that passes through the mounting faces of the mounting substrate; and a ground terminal connected to the through electrode.

Abstract: A die package and method is disclosed. In one example, the die package includes a die having a first die contact on a first side and a second die contact on a second side opposite the first side, and insulating material laterally adjacent to the die. A metal structure substantially directly contacts the surface of the second die contact, wherein the metal structure is made of the same material as the second die contact. A first pad contact on the first side of the die electrically contacts the first die contact, and a second pad contact on the first side of the die electrically contacts the second die contact via the metal structure. The insulating material electrically insulates the metal structure from the first die contact.

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

Abstract: The light emitting device package disclosed in the embodiment includes first and second frames spaced apart from each other; a body disposed between the first and second frames; a light emitting device including a first bonding portion and a second bonding portion on a lower portion thereof; and a first resin disposed between the body and the light emitting device, wherein the first frame includes a first protruding portion facing the first bonding portion of the light emitting device, and the second frame includes a second protruding portion facing the second bonding portion of the light emitting device, and including a first conductive layer between the first bonding portion and the first protruding portion and a second conductive layer between the second bonding portion and the second protruding portion.

Abstract: The present application provides a method of bonding an integrated circuit chip to a display panel. The method includes forming a plurality of first bonding pads in a bonding region on a first side of the display panel; forming a plurality of vias extending through the display panel in the bonding region; subsequent to forming the plurality of vias, disposing an integrated circuit chip having a plurality of second bonding pads on a second side of the display panel substantially opposite to the first side, the plurality of second bonding pads being on a side of the integrated circuit chip proximal to the display panel; and electrically connecting the plurality of first bonding pads respectively with the plurality of second bonding pads by forming a plurality of connectors respectively in the plurality of vias.

Abstract: The disclosed technology includes an oil-filled pressure transducer assembly and an oil-filled compensating sensing element disposed near one another and attached to a common housing. The oil-filled pressure transducer assembly may receive and measure pressure media via a first oil-filled cavity and a protective diagram in communication with the pressure media. The compensating sensing element may be isolated from the pressure media. In certain example implementations, the compensating sensing element is configured to measure certain common error phenomena that are also measured by the oil-filled pressure transducer assembly, for example, due to acceleration, temperature, and/or vibration. In certain implementations, the signal measured by the compensating sensing element may be subtracted from the signal measured by the oil-filled pressure transducer assembly to provide a compensated output signal.

Abstract: An optoelectronic component comprising a laser diode is disclosed.

Abstract: A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.

Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.

Abstract: A microelectronic device includes a first conductor and a second conductor, separated by a lateral spacing. The first conductor has a low field contour facing the second conductor. The low field contour has offsets from a tangent line to the first conductor on the low field contour. Each of the offsets increases a separation of the high voltage conductor from the low voltage conductor. A first offset, located from an end of the high voltage conductor, at a first lateral distance of 25 percent of the minimum separation, is 19 percent to 28 percent of the minimum separation. A second offset, located at a second lateral distance of 50 percent of the minimum separation, is 9 percent to 14 percent of the minimum separation. A third offset, located at a third lateral distance of 75 percent of the minimum separation, is 4 percent to 6 percent of the minimum separation.

Abstract: A transistor chip (2) has an active region (7). A first seal material (5) covers a central portion of the active region (7) and does not cover a peripheral portion of the active region (7). A second seal material (6) covers the peripheral portion of the active region (7). Thermal conductivity of the first seal material (5) is higher than thermal conductivity of the second seal material (6). Permittivity of the second seal material (6) is lower than permittivity of the first seal material (5).

Abstract: A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin.

Abstract: A semiconductor device and a semiconductor module which can be reduced in size while ensuing insulation are provided. In the semiconductor device, a lead frame on which a circuit pattern is formed is provided on an insulation substrate; the circuit pattern of the lead frame is joined to the back-side electrode of a semiconductor chip via a solder layer, and the lead frame is electrically connected with the top-side electrode of the semiconductor chip via a wire; the lead frame 1 includes a terminal inside a mold-sealing resin and a terminal exposed to a space outside the mold-sealing resin, and the terminal is connected to a terminal block via a solder layer; and the lead frame, the insulation substrate, the semiconductor chip and the terminal block are integrally molded and sealed by the mold-sealing resin.

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.