With Desiccant, Getter, Or Gas Filling Patents (Class 257/682)
  • Patent number: 11101491
    Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chyi-Tsong Ni, I-Shi Wang, Yi Hsun Chiu, Ching-Hou Su
  • Patent number: 11000474
    Abstract: Electromechanical substance delivery devices are provided which implement low-power electromechanical release mechanisms for controlled delivery of substances such as drugs and medication. For example, an electromechanical device includes a substrate having a cavity formed in a surface of the substrate, a membrane disposed on the surface of the substrate covering an opening of the cavity, and a seal disposed between the membrane and the surface of the substrate. The seal surrounds the opening of the cavity, and the seal and membrane are configured to enclose the cavity and retain a substance within the cavity. An electrode structure is configured to locally heat a portion of the membrane in response to a control voltage applied to the electrode structure, and create a stress that causes a rupture in the locally heated portion of the membrane to release the substance from within the cavity.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 11, 2021
    Assignee: International Business Machines Corporation
    Inventors: S. Jay Chey, Bing Dang, John U. Knickerbocker, Kenneth F. Latzko, Joana Sofia Branquinho Teresa Maria, Lavanya Turlapati, Bucknell C. Webb, Steven L. Wright
  • Patent number: 10959342
    Abstract: A power semiconductor module has a base plate, a housing affixed to the base plate, a DC busbar affixed to the base plate and the housing, and AC busbar affixed to the base plate and the housing, control electronics positioned in an interior of the housing and connected to the AC and DC busbars, and a sealant material applied to seams between the base plate in the housing, to seams between the DC busbar and the housing, and to seams between the AC busbar in the housing. The sealant material is applied such that the control electronics of the power semiconductor modules are in an air-tight environment.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: March 23, 2021
    Inventor: Kevin R. Williams
  • Patent number: 10870575
    Abstract: A semiconductor device may include a stress decoupling structure to at least partially decouple a first region of the semiconductor device and a second region of the semiconductor device. The stress decoupling structure may include a set of trenches that are substantially perpendicular to a main surface of the semiconductor device. The first region may include a micro-electro-mechanical (MEMS) structure. The semiconductor device may include a sealing element to at least partially seal openings of the stress decoupling structure.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 22, 2020
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Horst Theuss, Bernhard Knott, Thoralf Kautzsch, Mirko Vogt, Maik Stegemann, Andre Roeth, Marco Haubold, Heiko Froehlich, Wolfram Langheinrich, Steffen Bieselt
  • Patent number: 10818615
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first seal ring disposed over the molding, and a second seal ring disposed below the molding. The semiconductor structure further includes a first interconnect structure disposed below the first surface of the die and a second interconnect structure disposed over the second surface and the molding. The first seal ring is disposed in the second interconnect structure and disposed over the molding, and the second seal ring is provided within the die and the first interconnect structure.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10763224
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first seal ring disposed over the molding, and a second seal ring disposed below the molding. The semiconductor structure further includes a first interconnect structure disposed below the first surface of the die and a second interconnect structure disposed over the second surface and the molding. The first seal ring is disposed in the second interconnect structure and disposed over the molding, and the second seal ring is provided within the die and the first interconnect structure.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10510691
    Abstract: A semiconductor structure includes a substrate, a die disposed over a first surface of the substrate, a RDL disposed over a second surface of the substrate, a conductive structure disposed within the RDL. The conductive structure is configured as a seal ring protecting the RDL and the substrate from damages caused by cracks, chippings or other contaminants during fabrication or singulation. As such, delamination of components or damages on the semiconductor structure during fabrication or singulation can be minimized or prevented.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzuan-Horng Liu, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10431955
    Abstract: Laser cores are provided having a header having a base with a stem extending therefrom; a terminal extending from a sealed opening in the base proximate to but separate from the stem; a conductive surface electrically connected to the laser and positioned between the stem and the terminal; and a conductive mass between the terminal and the conductive surface having a cross-sectional area that is based upon a size of an overlap area between the terminal and the conductive surface.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 1, 2019
    Assignee: LMD Power of Light Corp
    Inventor: Jeffrey P. Serbicki
  • Patent number: 10431512
    Abstract: Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a housing including a first compartment and a second compartment, the first and second compartments being divided from one another. The semiconductor package can also include an integrated device die disposed in the first compartment, and a radio frequency (RF) absorber disposed in the second compartment.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 1, 2019
    Assignee: Analog Devices, Inc.
    Inventor: David Frank Bolognia
  • Patent number: 9862596
    Abstract: A micromechanical component formed from, a substrate (100) having a first cavity (112) and a second cavity (113), a first micromechanical structure (117) arranged in the first cavity (112), and a second micromechanical structure (118) arranged in the second cavity (113). The first cavity (112) and the second cavities having respective first and second gas pressures having different values. The first gas pressure is provided by a closed configuration of the first cavity (112) and a first channel (115) opens into the second cavity (113), and the second gas pressure is adjustable via the first channel (115).
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: January 9, 2018
    Assignee: CONTINENTAL TEVES AG & CO. OHG
    Inventors: Stefan Günthner, Bernhard Schmid
  • Patent number: 9831186
    Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-hyun Park, Byoung-ho Kwon, Dong-chan Kim, Choong-seob Shin, Jong-su Kim, Bo-un Yoon
  • Patent number: 9816890
    Abstract: A pressure sensor includes: a pressure sensor element; a metal adapter integrally attached to the pressure sensor element and defining therein a hole through which a pressure of a fluid to be measured is introduced to the pressure sensor element; a metal fitting member provided with a housing recess receiving the adapter and connectable to a connected member; and an operation member pressing a valve provided to the connected member and defining a communicating path through which a flow path, in which the pressure of the fluid to be measured is introduced, is in communication with the hole of the adapter. The adapter and the fitting member are connected to each other by plastic deformation. The operation member is a synthetic resin member including: a contact portion brought into contact with the adapter; and a pressing portion provided on a side opposite to the contact portion to press the valve.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: November 14, 2017
    Assignee: NAGANO KEIKI CO., LTD.
    Inventor: Nobuaki Yamada
  • Patent number: 9718224
    Abstract: An injection-molded circuit carrier is provided that has an outside and an underside and an inner base region and a frame. The frame has an inside and a cover surface, so that the inner base region is enclosed in the manner of a frame, and multiple printed conductors are provided, which are spaced a distance apart. The printed conductors are guided at least partially from the inside to the underside via the cover surface and via the outside so that at least two metal surfaces are formed on the underside, which are each electrically connected to a printed conductor and are spaced a distance apart. The metal surfaces are designed to be significantly wider than the printed conductors for the purpose of forming a capacitive sensor.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 1, 2017
    Assignee: TDK-Micronas GmbH
    Inventors: Joerg Franke, Timo Kaufmann, Oliver Breitwieser, Klaus Heberle
  • Patent number: 9630835
    Abstract: A MEMS device is formed by applying a lower polymer film to top surfaces of a common substrate containing a plurality of MEMS devices, and patterning the lower polymer film to form a headspace wall surrounding components of each MEMS device. Subsequently an upper polymer dry film is applied to top surfaces of the headspace walls and patterned to form headspace caps which isolate the components of each MEMS device. Subsequently, the MEMS devices are singulated to provide separate MEMS devices.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Stuart M. Jacobsen, Wei-Yan Shih
  • Patent number: 9497875
    Abstract: A control device for a motor vehicle includes a housing having a housing cover and a housing base, a sealing device between the housing cover and the housing base, at least one circuit carrier having electrically conductive tracks, and at least one electronic component disposed on the circuit carrier. The control device further includes at least one conductor structure extending out of the interior of the housing, and at least one electrically conductive connecting line which connects the electronic component to the conductor structure. A getter layer is thermally sprayed on the inner face of the housing to protect the metal parts, which transmit current or data in the interior of the control device, against corrosive gases. The getter layer has a high specific surface area.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: November 15, 2016
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Juergen Henniger, Matthias Wieczorek, Thomas Urbanek, Marion Gebhardt, Bernhard Schuch, Andreas Reif, Stefan Gottschling
  • Patent number: 9385067
    Abstract: A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected to the semiconductor element and penetrating the semiconductor substrate from the first surface to the second surface, and a conductor, not electrically connected to the semiconductor element, penetrating the semiconductor substrate from the first surface to the second surface, where the through electrode and the conductor have different shapes in plan view.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: July 5, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Nobuyuki Nakamura
  • Patent number: 9359161
    Abstract: An interleaving element is adapted to interleave a roll of glass substrate. The glass substrate includes at least one active area, a plurality of spacing zones and two edge zones. The plurality of spacing zones and the edge zones define the active area. The interleaving element includes two elongated side elements and a plurality of bridging elements. The elongated side elements correspond to the two edge zones. Each of the plurality of bridging elements is connected with the elongated side elements. The plurality of bridging elements corresponds to the spacing zones.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 7, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Sheng Huang, Hsin-Yun Hsu, Jyun-Kai Ciou
  • Patent number: 9362378
    Abstract: Methods for fabricating a piezoelectric device are provided. The methods can include providing a substrate and forming a nanocrystalline diamond layer on a first surface of the substrate. The methods can also include depositing a piezoelectric layer on a first surface of the nanocrystalline diamond layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 7, 2016
    Assignee: Indian Institute of Technology Madras
    Inventors: Maneesh Chandran, M. S. Ramachandra Rao
  • Patent number: 9352956
    Abstract: An embodiment is MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
  • Patent number: 9337129
    Abstract: A semiconductor device includes: a semiconductor element having an electrode facing a first direction; a first lead having a conductive distal end surface facing the electrode, and a rising portion which is connected to the distal end surface to extend away from the electrode; a conductive bonding material bonding the electrode of the semiconductor element to the distal end surface of the first lead; and a sealing resin covering the semiconductor element, at least a portion of the first lead, and the conductive bonding material.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: May 10, 2016
    Assignee: Rohm Co., Ltd.
    Inventors: Koji Yasunaga, Shingo Takaki
  • Patent number: 9266714
    Abstract: A device includes a first substrate bonded with a second substrate structure. The second substrate structure includes an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the outgasing prevention structure.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Patent number: 9247664
    Abstract: An electronic device includes a substrate, a cover body which is placed on the substrate, a first cavity which is surrounded by the substrate and the cover body, and a second cavity which is surrounded by the substrate and the cover body, wherein an inner portion of the first cavity is sealed in a first air pressure atmosphere, and an inner portion of the second cavity is sealed in a second air pressure atmosphere which has a difference of air pressure with respect to the first air pressure atmosphere, a first through-hole, which communicates with the first cavity and is blocked by a seal member, is provided in at least one of the substrate and the cover body, and the first cavity and the second cavity are isolated from each other by a partition wall portion which is integrally provided to the cover body or the substrate.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: January 26, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Teruo Takizawa
  • Patent number: 9114976
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The cap wafer comprises a first spring structure and the MEMS wafer comprises a second spring structure. The first spring structure and the second spring structure relieve stress as portions of the semiconductor arrangement, such as a membrane and a poly layer, move. An ambient pressure chamber is formed between the CMOS wafer and the MEMS wafer as a thermal insulation air gap to protect the MEMS wafer from heat originating from the CMOS wafer. The ambient pressure chamber is connected to ambient air, such as for CMOS outgassing relief.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: August 25, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Yi-Chuan Teng
  • Patent number: 9041174
    Abstract: The structure comprises a closed cavity under a controlled atmosphere in which a monoblock getter with a first getter layer is arranged. The first getter layer presents at least first and second getter areas which have different activation temperatures. The second getter area is formed on an adjustment sub-layer of the getter material activation temperature.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: May 26, 2015
    Assignee: COMMISSARIAT A L'ENERGIES ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Xavier Baillin
  • Publication number: 20150130039
    Abstract: The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).
    Type: Application
    Filed: June 18, 2013
    Publication date: May 14, 2015
    Inventors: Vivek Chidambaram, Ling Xie, Ranganathan Nagarajan, Bangtao Chen, Beng Yeung Ho
  • Patent number: 9006877
    Abstract: A package for a micro-electromechanical device (MEMS package) includes an inner enclosure having an inner cavity defined therein, and a fill port channel communicating with the inner cavity and of sufficient length to allow a quantity of adhesive to enter the fill port channel while preventing the adhesive from entering the inner cavity.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: April 14, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Don Michael, Mari J. Rossman, Bradley Bower, Charles Craig Haluzak, John R. Sterner, Quan Qi, John Kane
  • Patent number: 9006905
    Abstract: A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected to the semiconductor element and penetrating the semiconductor substrate from the first surface to the second surface, and a conductor, not electrically connected to the semiconductor element, penetrating the semiconductor substrate from the first surface to the second surface, where the through electrode and the conductor have different shapes in plan view.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 14, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Nobuyuki Nakamura
  • Patent number: 8981544
    Abstract: A packaging structure including at least one cavity wherein at least one micro-device is provided, the cavity being bounded by at least a first substrate and at least a second substrate integral with the first substrate through at least one bonding interface consisting of at least one metal or dielectric material, wherein at least one main face of the second substrate provided facing the first substrate is covered with at least one layer of at least one getter material, the bonding interface being provided between the first substrate and the layer of getter material.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: March 17, 2015
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Xavier Baillin, Christine Ferrandon
  • Patent number: 8970022
    Abstract: The present invention relates to an organic light emitting device and a manufacturing method thereof. A manufacturing method of an organic light emitting device according to an exemplary embodiment of the present invention includes forming a thin film structure on a first substrate, forming a dehumidification buffer layer on a second substrate, combining the first substrate and the second substrate, and heat treating the dehumidification buffer layer to soften the dehumidification buffer layer.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung-Mi Choi, Hoon Kim
  • Patent number: 8912620
    Abstract: Getter structure comprising at least one getter portion arranged on a support and including at least two adjacent getter material parts arranged on the support one beside the other, with different thicknesses and of which the surface grain densities are different from one another.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: December 16, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Christine Ferrandon, Xavier Baillin
  • Publication number: 20140346657
    Abstract: A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.
    Type: Application
    Filed: December 17, 2012
    Publication date: November 27, 2014
    Applicant: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Niklas Svedin
  • Patent number: 8884331
    Abstract: An encapsulation structure including at least one hermetically sealed cavity in which a device, an electronic component produced on a first substrate, and a getter material layer covering the electronic component in order to block the gases capable of being degassed by the electronic component, are enclosed. A top surface of the device is free of contact with the getter material layer.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: November 11, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Xavier Baillin, Jean-Louis Pornin
  • Patent number: 8878349
    Abstract: A semiconductor chip includes a semiconductor substrate having one surface, an other surface which faces away from the one surface, and through holes which pass through the one surface and the other surface; through electrodes filled in the through holes; and a gettering layer formed of polysilicon interposed between the through electrodes and inner surfaces of the semiconductor substrate whose form is defined by the through holes.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 4, 2014
    Assignee: SK Hynix Inc.
    Inventors: Gyu Jei Lee, Kang Won Lee, Hyun Joo Kim
  • Publication number: 20140306312
    Abstract: A micro electro mechanical systems (MEMS sensor packaging includes a first wafer having a readout integrated circuit (ROIC) formed thereon., a second wafer disposed corresponding to the first wafer and having a concave portion on one side thereof and a MEMS sensor prepared on the concave portion, joint solders formed along a surrounding of the MEMS sensor and sealing the MEMS sensor jointing the first and second wafers, and pad solders formed to electrically connect the ROIC circuit of the first wafer and the MEMS sensor of the second wafer. According to the present disclosure, in joining and packaging a wafer having the ROIC formed thereon and a wafer having the MEMS sensor formed thereon, the size of a package can be reduced and an electric signal can be stably provided by forming internally pad solders for electrically connecting the ROIC and the MEMS sensor.
    Type: Application
    Filed: November 9, 2012
    Publication date: October 16, 2014
    Inventors: Yong Hee Han, Hyung Won Kim, Mi Sook Ahn
  • Patent number: 8854220
    Abstract: A night vision goggle system includes a housing, and an eyepiece forming a back end of the housing for viewing an object of interest. An optical field-of-view (FOV) is formed through the eyepiece, where the FOV is defined by a cone having an apex formed adjacent to an exit pupil at the eyepiece and tapering outwardly toward the object of interest. A desiccant is disposed within the housing, and located outside the FOV. The desiccant is visible through the eyepiece when viewed from outside the FOV. In addition, when the eye of a user is placed within the FOV, the desiccant is not visible through the eyepiece; and when the eye of the user is placed outside the FOV, the desiccant is visible through the eyepiece.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: October 7, 2014
    Assignee: Exelis, Inc.
    Inventors: William Allen Smith, Scott Joseph Adams, Jean Cathcart
  • Patent number: 8847373
    Abstract: An approach to obtain localized heat within a sealed vacuum cavity is disclosed. The approach uses an exothermic reaction between two reactants to generate heat in the vicinity of a structure, such as a getter material or a bondline that is heat activated. The exothermic reaction can be initiated by application of laser light, or application of current to a current-carrying conductor in the vicinity of the reactants.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: September 30, 2014
    Assignee: Innovative Micro Technology
    Inventors: Jeffery F. Summers, Christopher S. Gudeman, Jaquelin K. Spong
  • Patent number: 8823154
    Abstract: An article and method of using spacer layer regions is provided, containing a gas compound, to reduce gas permeation through barrier films overlying a substrate comprising creating a spacer layer between one or more of the barrier films, wherein the spacer layer comprises at least one inert gaseous compound. In another embodiment, an article and method is provided comprising creating alternating thin films of hybridized sol-gel spin-on glass and PDMS based and olefin based elastomers.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: September 2, 2014
    Assignee: The Regents of The University of California
    Inventors: Craig J. Hawker, Jimmy Granstrom, Luis M. Campos, Jeffrey A. Gerbec, Motoko Furukawa
  • Publication number: 20140203421
    Abstract: A device includes a first substrate bonded with a second substrate structure. The second substrate structure includes an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the outgasing prevention structure.
    Type: Application
    Filed: April 15, 2014
    Publication date: July 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Pao SHU, Chia-Ming HUNG, Wen-Chuan TAI, Hung-Sen WANG, Hsiang-Fu CHEN, Alex KALNITSKY
  • Patent number: 8786082
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: July 22, 2014
    Assignee: Chipmos Technologies Inc.
    Inventor: Geng-Shin Shen
  • Publication number: 20140175405
    Abstract: A package structure of an electronic device is provided. The substrate of such package structure has at least one embedded gas barrier structure, which protects the electronic device mounted thereon and offers good gas barrier capability so as to extend the life of the electronic device.
    Type: Application
    Filed: November 27, 2013
    Publication date: June 26, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Shu-Tang Yeh, Jia-Chong Ho
  • Patent number: 8730715
    Abstract: A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir may be configured to be damaged in response to attempted tampering with the MRAM die, such that at least some of the chemical is released from the reservoir when the at least one boundary of the reservoir is damaged. In some examples, at least some of the chemical is configured to contact and alter or damage at least a portion of the MRAM cell when the chemical is released from the reservoir.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: May 20, 2014
    Assignee: Honeywell International Inc.
    Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli
  • Patent number: 8722497
    Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 13, 2014
    Assignees: Nissan Motor Co., Ltd., Rohm Co., Ltd.
    Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
  • Patent number: 8716852
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Patent number: 8716762
    Abstract: Disclosed are: a biosensor kit in which a bionsensor utilizing a field effect transistor is not deteriorated during storage or transport; and a system for detecting a substance of interest, which is equipped with the biosensor chip. The biosensor kit comprises a biosensor chip which can measure a substance of interest quantitatively and a package which can hermetically seal the biosensor chip and is composed of a packaging material comprising a metal film. The biosensor chip can measure the substance quantitatively based on the value of a current generated in a field effect transistor when the substance is reacted with a molecule that can recognize the substance and is immobilized on a reaction field connected to the field effect transistor. The biosensor chip comprises the field effect transistor and a mounting substrate on which the field effect transistor is mounted.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: May 6, 2014
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Mitsuru Sakamoto, Hirohiko Urushiyama, Hiroaki Kikuchi, Tomoaki Yamabayashi
  • Patent number: 8710554
    Abstract: Disclosed are: a biosensor kit in which a biosensor utilizing a field effect transistor is not deteriorated during storage or transport; and a system for detecting a substance of interest, which is equipped with the biosensor chip. The biosensor kit comprises a biosensor chip which can measure a substance of interest quantitatively and a package which can hermetically seal the biosensor chip and is composed of a packaging material comprising a metal film. The biosensor chip can measure the substance quantitatively based on the value of a current generated in a field effect transistor when the substance is reacted with a molecule that can recognize the substance and is immobilized on a reaction field connected to the field effect transistor. The biosensor chip comprises the field effect transistor and a mounting substrate on which the field effect transistor is mounted.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 29, 2014
    Assignee: Mitsumi Electric, Co., Ltd.
    Inventors: Mitsuru Sakamoto, Hirohiko Urushiyama, Hiroaki Kikuchi, Tomoaki Yamabayashi
  • Patent number: 8698262
    Abstract: The present invention provides a new type wireless chip that can be used without being fixed on a product. Specifically, a wireless chip can have a new function by a sealing step. One feature of a wireless chip according to the present invention is to have a structure in which an integrated circuit is sealed by films. In particular, the films sealing the integrated circuit have a hollow structure; therefore the wireless chip can have a new function.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Tsurume, Koji Dairiki, Naoto Kusumoto
  • Patent number: 8698292
    Abstract: An environment-resistant module which provides both thermal and vibration isolation for a packaged micromachined or MEMS device is disclosed. A microplatform and a support structure for the microplatform provide the thermal and vibration isolation. The package is both hermetic and vacuum compatible and provides vertical feedthroughs for signal transfer. A micromachined or MEMS device transfer method is also disclosed that can handle a wide variety of individual micromachined or MEMS dies or wafers, in either a hybrid or integrated fashion. The module simultaneously provides both thermal and vibration isolation for the MEMS device using the microplatform and the support structure which may be fabricated from a thin glass wafer that is patterned to create crab-leg shaped suspension tethers or beams.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 15, 2014
    Assignee: The Regents of the University of Michigan
    Inventors: Khalil Najafi, Sang-Hyun Lee, Sang Woo Lee
  • Patent number: 8692384
    Abstract: A semiconductor device includes: a plurality of semiconductor chips stacked on each other, each of the plurality of semiconductor chips having a semiconductor substrate and a wiring layer; a through electrode penetrating the semiconductor substrate in a thickness direction and electrically connected to each other between the semiconductor chips adjacent to each other; a conductor penetrating the semiconductor substrate in the thickness direction and not electrically connected between the other semiconductor chips; and an insulating separator penetrating the semiconductor substrate in the thickness direction and formed in a shape of a ring surrounding the conductor.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: April 8, 2014
    Inventor: Nobuyuki Nakamura
  • Patent number: 8680664
    Abstract: A structure for encapsulating at least one electronic device, including at least one first cavity bounded by a support and at least one cap provided on the support and wherein the electronic device is encapsulated, at least one aperture passing through the cap and communicating the inside of the first cavity with at least one portion of getter material provided in at least one second cavity which is arranged on the support and adjacent to the first cavity, at least one part of said portion of getter material being provided on the support or against at least one outer side wall of the first cavity, the first cavity and the second cavity forming together a hermetically sealed volume.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 25, 2014
    Assignee: Commissariat à l′énergie atomique et aux énergies alternatives
    Inventors: Jean-Louis Pornin, Geoffroy Dumont
  • Patent number: 8670246
    Abstract: A computer including an undiced semiconductor wafer having a multitude of microchips. The computer also including an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least a portion of a surface of the internal sipe. The internal sipe has opposing surfaces that are separate from each other and therefore can move relative to each other, and at least a portion of the opposing surfaces are in contact with each other in a unloaded condition. The outer chamber including a Faraday Cage. The multitude of microchips on the wafer are configured to allow the microchip to function independently and including independent communication capabilities.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: March 11, 2014
    Inventor: Frampton E. Ellis