Abstract: A hermetically sealed package includes: a base substrate and a cover substrate which define at least part of the package, the base substrate and the cover substrate being hermetically sealed to one another by at least one laser bonding line, the at least one laser bonding line having a height perpendicular to its bonding plane, at least the cover substrate including a toughened layer at its surface, at least on a side opposite the at least one laser bonding line; and at least one functional area enclosed in the package.

Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract: A display apparatus includes a display panel having a display substrate on which a plurality of pad terminals is disposed, and a driving unit having a plurality of driving terminals electrically connected to the plurality of pad terminals. Each of the plurality of pad terminals includes a stepped groove that faces a corresponding driving terminal of the plurality of driving terminals or each of the plurality of pad terminals includes an opening hole that faces the corresponding driving terminal of the plurality of driving terminals.

Abstract: A semiconductor package including a semiconductor chip; a lower redistribution layer on a lower surface of the semiconductor chip; a lower passivation layer on a lower surface of the lower redistribution layer; a UBM pad on the lower passivation layer and including an upper pad and a lower pad connected to the upper pad, the upper pad having a greater horizontal length at an upper surface thereof than a horizontal length at a lower surface thereof; a seed layer between the lower passivation layer and the UBM pad; and an external connecting terminal on a lower surface of the UBM pad, wherein the seed layer includes a first seed part covering a side surface of the upper pad, a second seed part covering a portion of the lower surface of the upper pad, and a third seed part covering a portion of a side surface of the lower pad.

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

Abstract: A hermetically sealed package includes: at least one cover substrate and a substrate arranged so as to adjoin the at least one cover substrate, which together define at least part of the package, the at least one cover substrate being in a thermally prestressed state and bonded to the substrate adjoining the at least one cover substrate in a hermetically sealing manner by at least one laser bonding line, the at least one cover substrate being made of a material which has a different characteristic value of a coefficient of thermal expansion than the adjoining substrate and a thermal prestress is established in the package; and at least one functional area enclosed in the package.

Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.

Abstract: An inspection jig is used for inspection for an inspection target device including a flexible substrate having a flexible base material with external connection terminals formed thereon. The inspection jig is composed of an inspection device and an attraction part. The inspection device has inspection terminals, and the inspection terminals have vacuum attraction holes. The attraction part has an attraction surface. The external connection terminals have first through holes. In inspection, the attraction part is placed on the front surface of the flexible base material so that the first through holes and the vacuum attraction holes overlap each other and the attraction surface covers the first through holes, and the insides of the first through holes and the vacuum attraction holes are made into vacuum, whereby the attraction surface is attracted to the flexible base material and the external connection terminals are attracted to the inspection terminals.

Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Abstract: The present application discloses a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes a conductive line of an Nth metal layer, a first insulating layer, a dielectric layer, a second insulating layer, an interconnect base, and an interconnect body. The first insulating layer is on the conductive line and free from covering a portion of the conductive line. The dielectric layer is on the first insulating layer and free from covering the portion of the conductive line. The second insulating layer is on the dielectric layer and free from covering the portion of the conductive line. The interconnect base is laterally surrounded by the dielectric layer, the first insulating layer, and the second insulating layer. A top surface of the interconnect base and a top surface of the second insulating layer are coplanar.

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

Abstract: The present disclosure provides a double-layer stacked 3D fan-out packaging structure and a method making the structure. The structure includes: a first semiconductor chip, a packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, and an underfill layer under the second semiconductor chip. The formed double-layer stacked 3D fan-out packaging structure is capable to package two sets of fan-out wafers in the three-dimension. A single package stacked up after die-cutting has two sets of chips in the third direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, thus improving the package integration level and reducing the package volume.

Abstract: One embodiment is a microelectronic assembly including an assembly support structure; a first die including a pair of hot via comprising through-substrate-via (TSVs) extending through the first die between first and second sides thereof and a plurality of ground vias surrounding the pair of hot vias and extending through the first die between the first and second sides thereof. The first die further includes a pair of signal interconnect structures electrically connected to the pair of hot vias disposed on the second side of the first die. The assembly further includes a second die between the assembly support structure and the first die the pair of signal interconnect structures disposed on the first side thereof. The first die is connected to the second die via a signal die-to-die (DTD) interconnect structure including the signal interconnect structures of the first and second dies.

Abstract: Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.

Abstract: A method for forming a package structure is provided. The method includes etching a top surface of a substrate to form a cavity. The substrate includes thermal vias directly under a bottom surface of the cavity. The method also includes forming at least one first electronic device in the cavity of the substrate. The first electronic device is thermally coupled to the thermal vias. The method further includes forming an encapsulating material in the cavity, so that the encapsulating material extends along sidewalls of the first electronic device and covers a surface of the first electronic device opposite the bottom surface of the cavity. In Addition, the method includes forming an insulating layer having an RDL structure over the encapsulating material. The RDL structure is electrically connected to the first electronic device.

Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: A sintered material excellent in thermal stress and bonding strength; a connection structure containing the sintered material; a composition for bonding with which the sintered material can be produced; and a method for producing the sintered material. The sintered material has a base portion, buffer portions, and filling portions. The buffer portions and filling portions are dispersed in the base portion. The base portion is a metal sintered body, each buffer portion is formed from a pore and/or material that is not the same as the sintered body, and each filling portion is formed from particles and/or fibers. The sintered material satisfies A>B. A is the kurtosis of volume distribution of the base portions in a three-dimensional image of the sintered material. B is the kurtosis of volume distribution of the base portions in a three-dimensional image of the sintered material from which the filling portions are removed.

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

Abstract: In an implementation, a semiconductor chip includes a device layer, an interconnect layer fabricated on the device layer, the interconnect layer including a conductive pad, and a conductive pillar coupled to the conductive pad. The conductive pillar includes at least a first portion having a first width and a second portion having a second width, the first portion being disposed between the second portion and the conductive pad, wherein the first width of the first portion is greater than the second width of the second portion.

Abstract: An adhesive composition, containing an epoxy resin (A), an epoxy resin curing agent (B), a polymer component (C) and an inorganic filler (D), in which the inorganic filler (D) satisfies the condition (1) of (an average particle diameter (d50) is 0.1 to 3.5 ?m) and condition (2) of (a ratio of a particle diameter at 90% cumulative distribution frequency (d90) to the average particle diameter (d50) is 5.0 or less), and a proportion of the inorganic filler (D) in a total content of the epoxy resin (A), the epoxy resin curing agent (B), the polymer component (C) and the inorganic filler (D) is 20 to 70% by volume; a film-like adhesive and a production method thereof; and a semiconductor package and a production method thereof.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a carrier board. A plurality of first alignment solder parts are formed on a passive surface of the semiconductor device, and a plurality of corresponding second alignment solder parts are formed on the carrier board. The method further comprises forming a plurality of alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts whereby the semiconductor device is aligned and fixed to the carrier board; encapsulating the at least one semiconductor device to form a molded package body; sequentially forming a redistribution layer and external terminals on the molded package body so that the connection terminals are connected to the external terminal through the interconnection layer.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.

Abstract: A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.

Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.

Abstract: A light-emitting diode device includes an epitaxial structure that contains first-type and second-type semiconductor units and an active layer interposed therebetween, a light transmittable dielectric element that is disposed on the first-type semiconductor unit opposite to the active layer and is formed with a first through hole, an adhesive layer that is disposed on the dielectric element and is formed with a second through hole corresponding in position to the first through hole, and a metal contact element that is disposed on the adhesive layer. The adhesive layer has a thickness of at most one fifth of that of the dielectric element. The metal contact element extends into the first and second through holes, and electrically contacts the first-type semiconductor unit. A method for manufacturing the LED device is also disclosed.

Abstract: An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.

Abstract: A semiconductor device may include a seed structure on a complex structure. The seed structure may include a first barrier layer, a first seed layer on the first barrier layer, a second barrier layer on the first seed layer, and a second seed layer on the second barrier layer. The second barrier layer may contact a side surface of at least one of the first barrier layer and the first seed layer. An electrode layer may be disposed on the seed structure.

Abstract: A wafer level package comprises a functional wafer with a first surface, device structures connected to device pads arranged on the first surface. A cap wafer, having an inner and an outer surface, is bonded with the inner surface to the first surface of the functional wafer. A frame structure surrounding the device structures is arranged between functional wafer and cap wafer. Connection posts are connecting the device pads on the first surface to inner cap pads on the inner surface. Electrically conducting vias are guided through the cap wafer connecting inner cap pads on the inner surface and package pads on the outer surface of the cap wafer.

Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

Abstract: A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Abstract: A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

Abstract: Embodiments disclosed herein include wire bonds and tools for forming wire bonds. In an embodiment, a wire bond may comprise a first attachment ball, and a first wire having a first portion contacting the first attachment ball and a second portion. In an embodiment, the wire bond may further comprise a second attachment ball, and a second wire having a first portion contacting the second attachment ball and a second portion. In an embodiment, the second portion of the first wire is connected to the second portion of the second wire.

Abstract: A packaged radio-frequency device can include a packaging substrate configured to receive one or more components, the packaging substrate including a first side and a second side. The packaging substrate may include a first component mounted on the first side and a first overmold structure implemented on the first side, the first overmold structure substantially encapsulating the first component. The packaging substrate may further include a set of through-mold connections implemented on the second side of the packaging substrate, the set of through-mold connections including signal pins and ground pins, a second component mounted on the second side of the packaging substrate, the second component being located in an area of the second side configured to implement a redundant ground pad or a redundant portion of a ground pad, and a second overmold structure substantially encapsulating one or more of the second component or the set of through-mold connections.

Abstract: A fan-out semiconductor package including a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer.

Abstract: A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion. The first portion is between the neck portion and the conductive pad. The neck portion is narrower than the first portion and narrower than the second portion.