Abstract: A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: Provided is an electronic module including a housing case for housing a relay, a heat transfer sheet placed on an inner surface of a bottom plate of the housing case, a terminal provided on one surface of the relay opposing a bottom plate, and a crank portion in which a first flat plate portion electrically connected to the terminal and a second flat plate portion that is in contact with the heat transfer sheet are coupled in a crank shape.

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

Abstract: A method is disclosed of mounting a heat sink through a printed circuit board to reach a component on the opposite side of a board. The heat sink is passed through a window in the board to contact a component at a predetermined pressure optimized for thermal performance at minimum stress. The heat sink is affixed in place on the printed circuit board using through-hole pins which can be soldered to maintain the heat sink's position and the predetermined pressure.

Abstract: A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the

Abstract: A power conversion apparatus, comprising: a semiconductor component for power conversion; a heat transfer member to which the semiconductor component is fixed such that the heat transfer member is thermally connected to a heat dissipation surface formed on at least one surface of the semiconductor component; and a housing, wherein the housing includes a heat dissipation wall portion, a fitting portion that fits to the heat transfer member is formed on the heat dissipation wall portion at an inside of the housing space, an area of contact between the fitting portion and the heat transfer member is greater than an area of the heat dissipation surface of the semiconductor component, and an occupied area of the fitting portion as seen in plan view is smaller than an area of the at least one surface of the semiconductor component on which the heat dissipation surface is formed.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

Abstract: An electronic module comprises a substrate including a first surface and a second surface on a side opposite to the first surface, the second surface including a first region and a second region surrounding the first region, an electronic device attached to the first surface, a component attached to the first region of the second surface, a lid member positioned to face the electronic device, and a frame member attached to the substrate to support the lid member. A first member and a second member having a higher thermal conductivity than the first member are disposed at least on the second surface. At least a part of the second member is positioned to face the second region. At least a part of the first member is positioned between the second member and the component.

Abstract: An electric working machine includes: a motor; a semiconductor element that is provided in a current path to the motor and completes or interrupts the current path; a circuit board on which the semiconductor element is mounted, a control circuit that turns on and off the semiconductor element to control energization to the motor being assembled to the circuit board; and a heat sink for dissipating heat from the semiconductor element. The semiconductor element is attached to the heat sink via a metal-based board.

Abstract: Stacked semiconductor die assemblies with heat sinks and associated methods and systems are disclosed. In some embodiments, a controller carrying one or more memory dies may be attached to a front side of a substrate. The substrate may include a heat sink formed on its back side such that the heat sink can establish a thermal contact with the controller. Further, the heat sink may be coupled to a thermally conductive pad of a printed circuit board (PCB) that carries the substrate. In this manner, the controller may be provided with a heat path toward the PCB to dissipate thermal energy generated during operation. In some cases, the substrate may include a set of thermal vias extending from the heat sink toward the controller to enhance the thermal contact between the controller and the heat sink.

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

Abstract: A heat shrink component includes a heat shrink layer and a heating unit in thermal contact with at least a part of the heat shrink layer and heating the heat shrink layer to a heat shrink temperature. The heat shrink component has a first dimension in an expanded state and a second dimension in a shrunk state after heating, the first dimension is larger than the second dimension. The heating unit includes an electrically conductive lead heated by an electrical current flowing through the electrically conductive lead and a heat spreading layer arranged in thermal contact with the electrically conductive lead and distributing a heat generated by the electrically conductive lead.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: A semiconductor module includes: a case; a semiconductor chip provided inside the case; a seal material injected to inside of the case and sealing the semiconductor chip; and a lid provided inside the case and contacting an upper surface of the seal material, wherein a tapered portion is provided at an end portion of the lid on an upper surface side, a gap is provided between a side surface of the end portion of the lid and an inner side surface of the case, and the seal material crawls up to the tapered portion through the gap.

Abstract: A heatsink, a light-emitting diode (LED) module and a corresponding method of manufacture are described. A heatsink includes an electrically conductive heatsink core and an electrically insulating layer covering at least the first surface of the electrically conductive heatsink core. The electrically conductive heatsink core has a first pin that is integral with the electrically conductive heatsink core and protrudes from a first surface of the heatsink core. At least the first surface of the heatsink core is covered by an electrically insulating layer, which leaves at least portions of a lateral surface of the first pin exposed from the electrically insulating layer.

Abstract: A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.

Abstract: A power conversion apparatus includes a case having a heat-dissipation property, and including a housing part formed to surround a predetermined space, a resin material having a thermal conductivity, the resin material being provided in the predetermined space, a coil disposed in the predetermined space, a coil case having a shape that fits with the housing part, the coil case being configured to house the coil, and a power semiconductor device disposed along a side wall of the coil case. The power semiconductor device is pressed and fixed between a side wall of the housing part and the side wall of the coil case in a state where a heat dissipation surface is in contact with the side wall of the housing part.

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

Abstract: A semiconductor module includes: a case; a semiconductor chip provided inside the case; a seal material injected to inside of the case and sealing the semiconductor chip; and a lid provided inside the case and contacting an upper surface of the seal material, wherein a tapered portion is provided at an end portion of the lid on an upper surface side, a gap is provided between a side surface of the end portion of the lid and an inner side surface of the case, and the seal material crawls up to the tapered portion through the gap.

Abstract: A semiconductor device has a substrate panel with a substrate having a first substrate area and a second substrate area outside a footprint of the first substrate area. A plurality of semiconductor die or discrete IPDs is disposed over the first substrate area. Substrate area 102a has electrical interconnect for the semiconductor die. A molding compound is disposed over the semiconductor die and first substrate area using a transfer mold process, which leaves mold culls and mold gates disposed over the second substrate area. A substrate edge is formed in the second substrate area under the mold gates. The substrate edge extends into the first substrate area under the molding compound to reinforce the mold gates and reduce cracking during mold degating. The substrate edge can have a variety of forms such as parallel bars, diagonal bars, orthogonal bars, and combinations thereof.

Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

Abstract: Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.

Abstract: A semiconductor package is provided. The semiconductor package includes a first package comprising a first substrate and a first semiconductor chip, a second package arranged on the first package, and the second package comprising a second substrate and a second semiconductor chip, a first solder ball and a supporter layer arranged between the first package and the second package, and a dam arranged between the first package and the second package, the dam being in contact with a sidewall of the supporter layer, and the dam completely surrounding the sidewall of the supporter layer.

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.

Abstract: In a described example, an integrated circuit (IC) package includes: an IC chip bonded to a chip mount pad on a lead frame; low modulus molding compound surrounding the IC chip; and IC package molding compound covering the IC chip, and at least a portion of the low modulus molding compound.

Abstract: An electronic module comprises a substrate 11, 21, an other-side electronic component 18, 23 provided on the other side of the substrate 11, 21, a one-side electronic component 13, 28 provided on one side of the substrate 11, 21 and a connecting terminal 115, 125 having an other-side extending part 119a, 129a extending to circumferential outside of the substrate 11, 21 on the other side of the substrate 11, 21, a one-side extending part 119b, 129b extending to circumferential outside of the substrate 11, 21 on one side of the substrate 11, 21, and a connecting part 118, 128 connecting the other-side extending part 119a, 129a with the one-side extending part 119b, 129b at the circumferential outside of the substrate 11, 21.

Abstract: A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.

Abstract: A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively.

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

Abstract: The semiconductor device includes a multi-layered substrate having an insulating plate and a circuit plate, a semiconductor chip having a front surface attached with a main electrode and a control electrode formed thereon, and a back surface fixed to the circuit plate, a first wiring substrate which includes a first conductive member and is placed so as to face the main electrode connected electrically to first conductive member, a second wiring substrate which includes a second conductive member, is placed so as to face the control electrode, and has an opening, and a conductive post having one end and another end, the one end being connected electrically and mechanically to the control electrode, and the other end being connected electrically and mechanically to the second conductive member. The first conductive member is thicker than the second conductive member, and the first wiring substrate is disposed within the opening.

Abstract: Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip. The mold layer may have a top surface substantially coplanar with the top surface of the semiconductor chip, and the top surfaces of the semiconductor chip and the mold layer may have a difference in surface roughness from each other.

Abstract: A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die, and a conductive feature in the package layer. The chip package further includes a first heat-spreading layer over the first side of the first semiconductor die and a first cap layer on the first heat-spreading layer.

Abstract: A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability.

Abstract: An electronic component housing unit includes: a substrate including a mounting region on which an electronic component is mounted; a connection conductor extending from a top face to a bottom face of the substrate, the connection conductor being electrically connected to the electronic component; a wiring conductor disposed on the bottom face of the substrate, one end of the wiring conductor being electrically connected to the connection conductor, another end of the wiring conductor being drawn out from a side face of the substrate; and a ground conductor disposed on the bottom face of the substrate, the ground conductor forming a coplanar line along with the wiring conductor. A bottom face of the wiring conductor is located above a bottom face of the ground conductor.

Abstract: An integrated circuit (IC) package having a packaging substrate, an IC disposed onto the packaging substrate, and a rigid support member attached to the substrate layer through an adhesive spacer is provided. The packaging substrate includes multiple decoupling capacitors positioned thereon around the IC. A heat sink is placed over the IC. The rigid support member provides enhanced structural support for the IC packaging and there is ample space between a bottom surface of the rigid support member and the packaging substrate to allow the placement of the decoupling capacitors underneath the rigid support member.

Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

Abstract: A semiconductor device includes a semiconductor element having a substrate of GaAs, InP, or GaN, and an element securing member bonded to the semiconductor element by solder. The element securing member is a composite material of Cu and carbon or a composite of Al and carbon. A stem is connected to the element securing member, and a cap is secured to the stem. The cap covers the semiconductor element and the element securing member. The stem and the element securing member are made of the same material.

Abstract: A heat dissipation device of a light engine for a projector has a housing, a fan module, a light engine and a heat sink. The light engine is positioned in the housing and connected to the heat sink. The heat sink is positioned out of the housing. The housing has a fan-enclosed flow channel attached on an outer surface of the housing. The fan module is guided by the fan-enclosed flow channel to the heat sink to enhance heat dissipation efficiency of the light engine for the projector.

Abstract: The light-emitting device having an equivalent circuit, includes at least four terminals, numbered from first terminal to fourth terminal, for electrical power feeding; a first light-emitting diode, arranged between the first terminal and the second terminal, configured to not emit light when a voltage is applied between the second terminal and one of the third terminal and the fourth terminal, and configured to emit light when a. voltage is applied between the first terminal and one of the third terminal and the four the terminal; and a second light-emitting diode, arranged between the third terminal and the fourth terminal, and configured to not emit light when the voltage is applied between the third terminal and one of the first terminal and the second terminal and configured to emit light when a voltage is applied between the fourth terminal and one of the first terminal and the second terminal.

Abstract: A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module substrate. The through wire interconnect includes a via, a wire in the via having a first end bonded to a substrate contact on the semiconductor substrate and a polymer layer at least partially encapsulating the wire. The semiconductor module system can also include a second substrate stacked on the semiconductor substrate having a second through wire interconnect in electrical contact with the through wire interconnect.

Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.

Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.

Abstract: A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.