Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Abstract: A system includes a calibration plate with fiducial markers, a device under test interface, an alignment stage with a rotary sub-stage and a linear sub-stage, and a camera on the alignment stage.

Abstract: A display device includes a substrate including a display area and a non-display area. The display device further includes a plurality of pixels in the display area of the substrate. The display device additionally includes a plurality of gate lines and a plurality of data lines respectively connected to the plurality of pixels. The display device further includes a plurality of insulative step portions disposed in the non-display area of the substrate and arranged in a first direction parallel to sides of the display area. The display device further includes a crack detection line in the non-display area and extending primarily in the first direction. The crack detection line includes a first portion which does not overlap the plurality of insulative step portions, and a second portion overlapping each of the insulative step portions.

Abstract: A multiple-stage RF amplifier and a packaged amplifier device include driver and final-stage transistors, each having a control terminal, a first current-carrying terminal, and a second current-carrying terminal. The control terminal of the final-stage transistor is electrically coupled to the first current-carrying terminal of the driver transistor. The amplifier further includes an inter-stage circuit coupled between the first current carrying terminal of the driver transistor and a voltage reference node. The inter-stage circuit includes a first inductance, a first capacitor, and a second capacitor. The first inductance and the first capacitor are coupled in series between the first current carrying terminal and the voltage reference node, with an intermediate node between the first inductance and the first capacitor. The second capacitor has a first terminal electrically coupled to the intermediate node and a second terminal electrically coupled to the voltage reference node.

Abstract: A mounting apparatus is provided which includes a frame having a table, a support member disposed on the table to support a substrate, and a feeder mounted on a feeder mount unit disposed in the frame at one side of the table. The feeder provides an element to be attached to the substrate. An element value measuring unit is disposed adjacent one side of the frame and directly measures an element value of the element. A head unit picks up the element from the feeder, inputs the element into the element value measuring unit, and/or attaches the element to the substrate. A control device controls operations of the feeder and the head unit.

Abstract: Methods and systems for determining a position of output generated by an inspection subsystem in design data space are provided. One method includes selecting one or more alignment targets from a design for a specimen. At least a portion of the one or more alignment targets include built in targets included in the design for a purpose other than alignment of inspection results to design data space. At least the portion of the one or more alignment targets does not include one or more individual device features. One or more images for the alignment target(s) and output generated by the inspection subsystem at the position(s) of the alignment target(s) may then be used to determine design data space positions of other output generated by the inspection subsystem in a variety of ways described herein.

Abstract: A method for intelligent inline metrology is a provided. A parameter of a workpiece is measured at a first set of inspection sites on the workpiece. A determination is made as to whether a first specification is met using the measurements at the first set of inspection sites. In response to the first specification being met, the parameter is estimated at a second set of inspection sites on the workpiece. In response to the first specification being unmet, the parameter is measured at the second set of inspection sites and a determination is made as to whether a second specification is met using the measurements at the second set of inspection sites. A system for intelligent inline metrology is also provided.

Abstract: An embodiment of a method of manufacturing semiconductor wafers comprises determining at least one material characteristic for at least two positions of a semiconductor ingot. A notch or a flat is formed in a semiconductor ingot extending along an axial direction. A plurality of markings is formed in the semiconductor ingot. At least some of the plurality of markings at different positions along the axial direction are distinguishable from each other by a characteristic feature set depending on the at least one material characteristic. The semiconductor ingot is then sliced into semiconductor wafers.

Abstract: A surface mount device is disclosed. The surface mount device can include an electronic component operable in an electronic circuit. The surface mount device can also include a heat transfer component thermally coupled to the electronic component. The heat transfer component can have a heat transfer surface configured to interface with a heat sink. In addition, the surface mount device can include a resiliently flexible lead to electrically couple the electronic component to a circuit board. The resiliently flexible lead can be configured to resiliently deflect to facilitate a variable distance of the heat transfer surface from the circuit board, to enable the heat transfer surface and a planar heat transfer surface of another similarly configured surface mount device to be substantially aligned for interfacing with the heat sink.

Abstract: A method for producing a substrate having an irregular concave and convex surface for scattering light includes: manufacturing a substrate having the irregular concave and convex surface; irradiating the concave and convex surface of the manufactured substrate with inspection light from a direction oblique to a normal direction and detecting returning light of the inspection light returned from the concave and convex surface by a light-receiving element provided in the normal direction of the concave and convex surface; and judging unevenness of luminance of the concave and convex surface by an image processing device based on light intensity of the returning light received. An organic EL element which includes a diffraction-grating substrate having an irregular concave and convex surface is produced with a high throughput.

Abstract: Disclosed herein are mono-functional silylating compounds that may exhibit enhanced silylating capabilities. Also disclosed are method of synthesizing and using these compounds. Finally methods to determine effective silylation are also disclosed.

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.

Abstract: A method of testing a device includes setting a potential of a cap terminal of the device to a first voltage, setting a potential of a self test plate of the device to a testing voltage, and detecting a first displacement of a proof mass of the device when the cap terminal is set to the first voltage and the self test plate is set to the testing voltage. The method includes setting a potential of the cap terminal of the device to a second voltage, detecting a second displacement of the proof mass of the device when the cap terminal is set to the second voltage and the self test plate is set to the testing voltage, and comparing the first displacement and the second displacement to evaluate an electrical connection between the cap terminal and a cap of the device.

Abstract: A pressure sensor system comprising a pressure sensor chip is disclosed. The pressure sensor chip comprises a sensing side where pressure sensing is performed and one or more interconnections where electrical connections are made at the other side of the chip. The pressure sensor comprising an integrated circuit (1) forming a substrate, the substrate comprising a membrane shaped portion adapted for being exposed to the pressure, the integrated circuit (1) comprising both pressure signal sensing components and pressure signal processing components.

Abstract: Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range.

Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.

Abstract: The present invention provides an organic light-emitting diode, which includes a light-transmitting substrate, an anode arranged on the light-transmitting substrate, a hole transporting layer arranged on the anode, a light emission layer arranged on the hole transporting layer, an electron transporting layer arranged on the light emission layer, and a cathode arranged on the electron transporting layer. The light emission layer includes a color light emission layer and an ultraviolet light emission layer spaced from the color light emission layer. The present invention integrates functions of color displaying and ultraviolet source together to allow the color displaying and the ultraviolet source to be simultaneously or individually activated.

Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.

Abstract: A semiconductor device has a substrate and conductive layer over the substrate. A resistive element is formed between first and second portions of the conductive layer. A plurality of semiconductor die each with first and second bumps is mounted to the substrate with the first and second bumps electrically connected to the first and second portions of the conductive layer. A test current is routed in sequence through the first portion of the conductive layer, through the first and second bumps, and through the second portion of the conductive layer until continuity failure of the second bump. The test current originates from a single power supply. The test current continues to flow through the resistive element after the continuity failure of the second bump. The continuity failure can be detected by sensing an increase in voltage across the second bump.

Abstract: A micro-channel structure having variable depths includes a substrate and a cured layer formed on the substrate. At least first and second micro-channels are embossed in the cured layer. The first micro-channel has a bottom surface defining a first depth and the second micro-channel has a bottom surface defining a second depth different from the first depth. A cured electrical conductor is making a micro-wire is formed in each of the first and second micro-channels over their respective bottom surfaces.

Abstract: A control method of a multi-chip package memory device includes the steps of applying stack signals to stack pads of memory dies, applying a repair signal to repair pads of the respective memory dies, setting one or more repaired memory dies for replacing a failed memory die among the memory dies, based on the repair signal applied to the respective memory dies, and setting stack states indicating a logical access order of the other memory dies excluding the repaired memory die, based on the stack signals applied to the other memory dies.

Abstract: An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad.

Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.

Abstract: A sensor array for detecting particles, the sensor array comprising a substrate having a plurality of holes, a plurality of electronic sensor chips each having a sensor active region being sensitive to the presence of particles to be detected, and an electric contacting structure adapted for electrically contacting the plurality of electronic sensor chips, wherein the plurality of electronic sensor chips and/or the electric contacting structure are connected to the substrate in such a manner that the plurality of holes in combination with the plurality of electronic sensor chips and/or the electric contacting structure form a plurality of wells with integrated particle sensors.

Abstract: Provided is a TFT board for a liquid crystal display device including: a circuit layer formed on a substrate, the circuit layer including a thin film transistor including a semiconductor layer, a gate electrode, a drain electrode, and a source electrode; and a color filter layer formed on the circuit layer. The color filter layer has a through hole formed therein above the semiconductor layer in a region between the source electrode and the drain electrode.

Abstract: Provided is a method of manufacturing a semiconductor device, which includes the steps of: (a) preparing a processing target including a wafer (21) and a protective member (24) formed on the wafer (21); (b) measuring a thickness of the protective member (24) at a plurality of points; and (c) setting a desired value of a total thickness of the wafer (21) and the protective member (24) based on measurement results at the plurality of points to grind the wafer (21) in accordance with the desired value.

Abstract: A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer.

Abstract: A method for producing at least one semiconductor component group, in particular a SiC semiconductor component group, includes the step of producing a number of semiconductor components on a substrate, particularly on a wafer. The individual semiconductor components are tested for detecting operative semiconductor components. At least one semiconductor component group is assembled, which is formed of a number of operative semiconductor components and which forms a coherent flat structure. The operative semiconductor components of the semiconductor component group are electrically connecting in parallel.

Abstract: A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer.

Abstract: A method for alignment of a first substrate coupled to a second substrate includes determining an inclination angle for the first substrate or the second substrate due to warpage. The method includes determining a joint height difference based on the inclination angle and configuring a size for one or more bond pads based on the joint height difference.

Abstract: Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing.

Abstract: A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.

Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Abstract: A method for manufacturing an electronic multi-chip module that involves stacking at least six tested devices to form the module. These devices may be individually tested prior to assembling the electronic module. After individually testing the devices, the devices may be stacked one on top of the other to form an electronic multi-chip module having at least six stacked devices. Other embodiments may be described and claimed.

Abstract: A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip.

Abstract: An apparatus for performing metrology of a wafer. The apparatus may include a substrate with a plurality of microprobes. A plurality of light sources may direct light onto each of the microprobes. Light reflected from the microprobes may be detected by a plurality of photodetectors thereby generating a detection signal associated with each of the microprobes. A controller may send a driving signal to each of the plurality of microprobes and determine a height profile and a surface charge profile of the wafer based on each of the detection signals.

Abstract: A structure and method for fabricating finFETs of varying effective device widths is disclosed. Groups of fins are shortened by a predetermined amount to achieve an effective device width that is equivalent to a real (non-integer) number of full-sized fins. The bottom of each group of fins is coplanar, while the tops of the fins from the different groups of fins may be at different levels.

Abstract: According to an embodiment, a method for measuring an impurity concentration profile uses a wafer including a semiconductor layer. The method includes measuring an impurity concentration profile in a depth direction from each surface of a plurality of first portions, each of the first portions being included in any one of a plurality of first regions provided in the semiconductor layer. Each of the first regions has a different size and is surrounded by a second region including a second portion having a different structure from the first portion. The method includes determining a change between the impurity concentration profiles measured in the first regions.

Abstract: An electronic package implemented in an electronic device may include a damaged connection that restricts electrical communication between components in the electronic package. For example, the damaged connection may restrict communication between a silicon unit, such as a processor die for example, and a printed circuit board. The damaged connection may be repaired without damaging other components in the electronic package by using a repair apparatus that includes a heating element and a cooling element. The heating element may be activated to transfer heat to the electronic package for reforming the damaged connection between components to enable effective electrical communication. The cooling element may be activated for cooling components in the electronic package to prevent damage due to the transfer of the heat from the heating element. The heating element and/or the cooling element may be activated in a predetermined pattern to facilitate the repair of the damaged connection.

Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.

Abstract: When forming critical threshold adjusting semiconductor alloys and/or strain-inducing embedded semiconductor materials in sophisticated semiconductor devices, at least the corresponding etch processes may be monitored efficiently on the basis of mechanically gathered profile measurement data by providing an appropriately designed test structure. Consequently, sophisticated process sequences performed on bulk semiconductor devices may be efficiently monitored and/or controlled by means of the mechanically obtained profile measurement data without significant delay. For example, superior uniformity upon providing a threshold adjusting semiconductor alloy in sophisticated high-k metal gate electrode structures for non-SOI devices may be achieved.

Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.

Abstract: A display device capable of suppressing decrease in capacitance and capable of reducing area even when a capacitor unit is repaired is provided. A capacitor unit in a display device includes: a capacitor element having a first capacitor electrode connected to a power line and provided in an SD electrode layer and a second capacitor electrode provided in a GM electrode layer; a backup capacitor electrode provided in the TM electrode layer; a disconnect-able portion at which a connection between the first capacitor electrode and the power line can be disconnected; and a connectable portion at which the backup capacitor electrode and the power line can be connected, and the disconnect-able portion and the connectable portion overlap in a stacking direction.

Abstract: A microelectronic package assembly comprises a lead frame having a holding bar (16) and a microelectronic package (14). The microelectronic package (14) comprises a package body (22) and a connecting element (24) for connecting the package body (22) to the holding bar (16) of the lead frame (12). The connecting element (24) extends from an outer surface (26) of the package body (22) and is engaged with an ending part (28) of the holding bar (16).

Abstract: A semiconductor device includes a plurality of first data input/output terminals, a plurality of second data input/output terminals, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a plurality of first data input/output pads connected with the first data input/output terminals, a first test circuit, and a first memory portion. The first test circuit generates a first test result in response to a data output from the first memory portion at a test operation. The second semiconductor chip includes a plurality of second data input/output pads connected with the second data input/output terminals, a second and a third test circuits, and a second memory portion.

Abstract: Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

Abstract: Embodiments relate to measurement of temperature and current in semiconductor devices. In particular, embodiments relate to monolithic semiconductor, such as power semiconductor, and sensor, such as a current or temperature sensor, device. In embodiments, temperature and/or current sensing features are monolithically integrated within semiconductor devices. These embodiments thereby can provide direct measurement of temperature and current, in contrast with conventional solutions that provide temperature and current sensing near or alongside but not integrated within the actual semiconductor device. For example, in one embodiment an additional layer structure is applied to a power semiconductor stack in backend processing. This monolithic integration provides for localized measurement of temperature and/or current, an advantage over conventional side-by-side configurations.

Abstract: In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.

Abstract: A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.

Abstract: A technique for testing the compatibility of an encapsulation material and a wire bond included at an unencapsulated assembly. The technique includes immersing the assembly in an encapsulating compound extract. The assembly includes a semiconductor die and a bonding wire affixed to a metalized pad of the semiconductor die by the wire bond. After the immersing, a mechanical strength of the wire bond is determined.