Characterized By Current Path (epo) Patents (Class 257/E39.004)
  • Patent number: 7888243
    Abstract: An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: February 15, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Kouta Takahashi, Susumu Iwamoto