Abstract: Disclosed are a readout circuit, an offset voltage eliminating method and device, a computer device, and a non-transitory computer-readable storage medium. The readout circuit includes an object quantizer and an offset voltage elimination circuit. The offset voltage elimination circuit includes a correction circuit and a calibration circuit, an input of the correction circuit is connected to an output of the object quantizer, a compensation input of the calibration circuit is connected to an output of the current compensator, and a reference input of the calibration circuit is connected to the output of the object quantizer.

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

Abstract: The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains.

Abstract: A method for controlling a semiconductor bridge of an electrically operable motor, the semiconductor bridge being controlled depending on a pulse width modulation signal by a first controllable semiconductor switch and a separate second controllable semiconductor switch for supplying the electrically operable motor with electrical energy, a ramp signal with a predeterminable ramp slope for controlling one of the two controllable semiconductor switches being generated by a ramp generator, depending on the pulse width modulation signal. The invention also relates to a control device and to an arrangement.

Abstract: A data transmission apparatus includes lanes, a first clock generation circuit, a second clock generation circuit, a first circuit, and a second circuit. The first clock generation circuit can generate a first clock as a reference for data transmission in a first lane. The second clock generation circuit can generate a second clock as a reference for data transmission in a second lane. The first circuit can determine a shift amount by notification of a first delay amount of the first lane and a second delay amount of the second lane to cause a delay amount of one of the first clock and the second clock to match a delay amount of the other of the first clock and the second clock. The second circuit can shift the first delay amount or the second delay amount based on the determined shift amount.

Abstract: Provided is a current generation circuit including a first terminal to be connected to a first external circuit; a second terminal to be connected to a second external circuit; a first resistor in which a potential is generated by the first external circuit connected through the first terminal; a second resistor in which a potential is generated by the second external circuit connected through the second terminal; a first amplifier circuit including a first positive input terminal to which the potential generated in the first resistor is supplied, and a first negative input terminal to which the potential generated in the second resistor is supplied; and a first MOS transistor having a gate connected to an output terminal of the first amplifier circuit, a source connected to the first negative input terminal, and a drain connected to a first differential current terminal.

Abstract: A GOA unit, a GOA circuit and a display panel are provided. The GOA unit includes a pull-up module, a pull-up holding module, a converting module, a pull-down holding module, and a pull-down module. Each module can be implemented with N-type TFTs. The GOA unit could generate a negative impulse waveform for internal feedback mechanism.

Abstract: Apparatus and associated methods relate to quasi-adiabatic logic gates in which at least one supply terminal receives sinusoidal power. The quasi-adiabatic logic gate is configured to perform a specific logic function operative upon one or more input signals. When the quasi-adiabatic logic gate switches the output from one logic state to another logic state, the transient switching portion of the output signal substantially tracks the sinusoidal supply signal. Such a sinusoidal transient switching portion of the signal has lower frequency components than have traditional CMOS logic gate transients. Some embodiments include an inductor through which the sinusoidal supply signal is provided to the quasi-adiabatic logic gate. Such an inductor can both provide charge to and recover charge from switching quasi-adiabatic logic gates, thereby further reducing power.

Abstract: An apparatus, such as a re-driver, can include a receiver port coupled to a first link partner across a first link; a transmitter port coupled to a second link partner across a second link; and a power management (PM) controller implemented in hardware. The PM controller can detect a PM control signal, determine a PM state for the apparatus based on the PM control signal, and cause the apparatus to enter the PM state. The apparatus can transmit electrical signals to the second link partner based on the PM state. The PM management control signal can include a clock request, an electrical idle, a common mode voltage, or other electrical signal indicative of a PM link state change of a link partner coupled to the re-driver.

Abstract: A glitch absorbing buffer reduces glitch power in digital circuits. The glitch absorbing buffer includes a logic element configured to identify a digital logic glitch and a delay circuit configured to selectively delay one input to a logic element. The amount of delay imposed is equivalent to a pulse width of the glitch. A Schmitt trigger may amplify the low pass behavior on the input.

Abstract: An integrated circuit includes a first stage and a second stage. The first stage receives a previous stage output data and a clock signal and generates a first output data. The second stage receives the first output data and the clock signal. The first stage includes a first flip-flop circuit, a first static combinational circuit, a dynamic combinational circuit and a multi-phase generator. The first flip-flop circuit receives the previous output data and the clock signal and generates an input data. The first static combinational circuit receives the input data and generates an intermediate data. The multi-phase generator receives the clock signal and generates a delayed clock signal. The dynamic combinational circuit receives the intermediate data and the delayed clock signal and generates the first output data.

Abstract: A capacitive interface device, includes a detection surface with one or more first capacitive electrodes extending in a first direction (X), second capacitive electrodes extending in a second direction (Y), third capacitive electrodes arranged in a matrix between the second capacitive electrodes and facing the one or more first capacitive electrodes, and linking tracks electrically connected within the detection surface to a plurality of adjacent third capacitive electrodes.

Abstract: Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. The cell camouflaging covert gate leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. A comprehensive security analysis of the covert gate shows that it achieves high resiliency against SAT and test-based attacks at very low overheads. Models are derived to characterize the covert cells, and metrics are developed to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.

Abstract: An over-voltage tolerant test bus for an integrated circuit (IC) is disclosed. The over-voltage tolerant test bus includes a first switch to be coupled to a test pin of the IC and a second switch to be coupled to an internal module of the IC. The second switch is coupled to the first switch in series. The over-voltage tolerant test bus also includes a protection circuit coupled between the first switch and the second switch and a supply voltage to keep a voltage between a source and a drain of the first switch substantially equal to a difference between a voltage at the test pin and the supply voltage.

Abstract: An input/output circuit includes a logic unit configured to generate a first signal and a second signal based on data and a first control signal, a driver including a first PMOS transistor having a first gate, a first source that receives a first voltage from a first voltage source, and a first drain, and a first NMOS transistor having a second gate that receives the second signal, a second source that receives a second voltage from a second voltage source less than the first voltage, and a second drain connected to the first drain, a gate-tracking circuit configured to receive the first signal and transfer the received first signal to the first gate of the first PMOS transistor based on a second control signal, and an input/output terminal connected to the first drain and the second drain.

Abstract: The present application discloses a shift-register circuit and driving method, a gate-driving circuit and display apparatus. The shift-register circuit includes an input sub-circuit, a reset sub-circuit, an output sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit. The pull-down control sub-circuit is configured, after an output period of an operation cycle for displaying one frame of image, to control the pull-down node at a first voltage level to keep voltage level low at an output port. Additionally, the pull-down sub-circuit is configured, under control of power signals, to pull down the voltage level at the output port. For the display-touch panel with full-in-cell touch sensors, the voltage level at output port can be effectively reduced to avoid mutual interference between drive signals and touch-control signals.

Abstract: A half bridge circuit driver chip and the protection method thereof are provided. The high side voltage detecting circuit connects to a high side signal output terminal and detects the high side turn-on voltage of the high side transistor, so as to obtain a high side turn-on signal. The low side voltage detection circuit connects to a low side signal output terminal and detects a low side turn-on voltage of a low side transistor, so as to obtain a low side turn on signal. When the high side turn-on signal and the low side turn-on signal are received by a protection circuit, a reset signal is generated. The reset signal is sent to the high side driving circuit for turning off the high side transistor and to the low side driving circuit for turning off the low side transistor.

Abstract: A level shifting circuit includes a first inverter, a second inverter, and a third inverter which are connected in a cascade. The first inverter operates at a first power supply voltage supplied to a first power supply line, and the third inverter operates at a second power supply supplied to a second power supply line. The second inverter includes a first p-type transistor having a source connected to the first power supply line, a second p-type transistor having a source connected to the second power supply line, and a first n-type transistor having a source connected to a ground line. Each gate of the first and second p-type transistors and the first n-type transistor is connected to an output terminal of the first inverter, and each drain of the first and second p-type transistors and the first n-type transistor is connected to an input terminal of the third inverter.

Abstract: An electronic device includes a resistance element coupled between a supply terminal of a first voltage and an output terminal of an output signal, a driving element coupled between the output terminal of the output signal and a supply terminal of a second voltage, and suitable for operating based on a control signal, and a controller suitable for generating the control signal based on an input signal of the controller to the driving element. The controller drives an output terminal of the control signal with a first driving force during an initial period of a first transition period of the control signal, and drives the output terminal of the control signal with a second driving force different from the first driving force during the remaining period of the first transition period. The initial period is determined depending on a threshold voltage of the driving element.

Abstract: An electrostatic discharge (ESD) protection circuit includes a snapback ESD protection device and an ESD tail current clamp circuit. The snapback ESD protection device is configured to shunt current of an ESD event to a voltage reference. The ESD tail current clamp circuit is connected in parallel with the snapback ESD protection device. The ESD tail current clamp circuit is configured to shunt tail current of the ESD event to the voltage reference while the snapback ESD protection device is disabled.

Abstract: A transmitter circuit includes a slew rate control circuit, a hysteresis circuit, a logic control circuit, and an amplifier circuit. The slew rate control circuit controls a slew rate of an input signal to generate a first output signal. The hysteresis circuit generates a first control signal according to the first output signal. The logic control circuit generates a second control signal and a third control signal according to the input signal and the first control signal. The amplifier circuit generates a second output signal according to the first output signal, the second output signal, the second control signal, and the third control signal.

Abstract: A driver circuit which is supplied with a positive power supply voltage, a negative power supply voltage, and an input signal, and drives a switching element including a control terminal according to the input signal includes: a first output terminal connected to the control terminal via a first impedance circuit, and outputs the positive power supply voltage or the negative power supply voltage according to the input signal, to charge the control terminal and put the switching element into an ON state; a negative power supply terminal supplied with the negative power supply voltage; a negative voltage switch having a first end connected to the negative power supply terminal; a third output terminal connected to a second end of the negative voltage switch and to the control terminal via a second impedance circuit; and a first discharge switch disposed between the negative power supply terminal and the first output terminal.

Abstract: The present invention relates to a semiconductor device provided with a dead-time generation circuit, the semiconductor device including: first and second status-detection circuits that each have a function of detecting whether first and second switching devices are in turn-off operation to output first and second status signals, respectively, and each have a function of generating a dead time of on-off operation of the corresponding one of the first and second switching devices; a first logic circuit that receives a first on-off command signal instructing the first switching device to be turned on or off, and the second status signal to output a signal allowing the first switching device to be turned on only when the second switching device is not in turn-off operation; and a second logic circuit that receives the first on-off command signal instructing the second switching device to be turned on or off, and the first status signal to output a signal allowing the second switching device to be turned on only

Abstract: A semiconductor building block is disclosed which includes a plurality of logic gates, each having at least one P-channel device, at least one N-channel device, and a current controller controlling current for each of the plurality of logic gate having a voltage source input (vdd), a ground input (vss), a first input current (ibiasn) adapted to control current through the at least one N-channel device, a second input current (ibiasp) adapted to control current through the at least one P-channel device, and an analog voltage input (delta) representing i) a predetermined ratio between respective on currents in the at least one P-channel device to ibiasp, and ii) the predetermined ratio between respective on currents in the at least one N-channel device to ibiasn.

Abstract: A half buffer circuit includes a current source coupled to a first node, a ground connection coupled to a second node, a feedback capacitor coupled between the first node and an output of the half buffer circuit, a transconductor element comprising a first input/output, a second input/output, and a transconductor element control input, and a switch network coupled between the first node and the second node. The first input/output is coupled to the output of the half buffer circuit. The second input/output is coupled to a ground connection. The switch network includes a first switch coupled between the first node and the second node, a second switch coupled between the first node and the transconductor element control input, and a third switch coupled between the second node and the transconductor element control input.

Abstract: A shift register circuit including a switch control port configured to couple to a pull-up node via two transistors in series controlled by another transistor. The switch control port is configured to keep at a low voltage level during a display scan stage for the shift register circuit to output a gate scanning signal via an output port to a gate line which optionally still transmit a touch scanning signal, to switch to a high voltage level to halt the gate scanning signal while transmitting the touch scanning signal only in the gate line during a touch scan stage within the display scan stage, and to switch back to the low voltage level after the touch scan stage to output the gate scanning signal without coupling interference of the touch scanning signal. The shift register circuit is compatible for driving either 60 Hz or high-frequency (>60 Hz) Full-in-cell touch sensing display panel.

Abstract: A measurement system includes a control device which controls a control target device in real time and transmits control data to a terminal device, and a measuring instrument which acquires data indicating a physical status of the control target device and transmits the data as measurement data to the terminal device. The control device includes a control unit and a sequence control unit, and the control unit transmits a timing signal to the measuring instrument. The control device transmits the control data that includes a piece of time information based on the timing signal to the terminal device. The measuring instrument transmits the measurement data that includes a piece of time information based on the timing signal to the terminal device. The terminal device compensates for a delay between the control data and the measurement data on the basis of the pieces of time information.

Abstract: Apparatus and associated methods relate to unit circuits that having a number of capacitors and/or buffers controlled by two different control signals, capacitors and/or buffers that receiving, through routing, a same control signal from a control circuit are physically placed adjacent without crossing routings that connects capacitors and/or buffers controlled by a different control signal. In an illustrative example, a first capacitor may be configured to receive a first control signal through an inverting buffer, and a second capacitor may be configured to receive the first control signal through a non-inverting buffer, the inverting buffer and the non-inverting buffer may be provided by an integrated buffer structure. By arranging the physical positions of the capacitors and/or buffers, wire capacitances of the unit circuit may be advantageously reduced.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for reducing latency in switching computing cores of a computing system between operating modes. Certain aspects provide a computing device including a plurality of computing cores, each configured to operate in any one of a plurality of operating modes. The computing device further includes a first voltage rail and a plurality of components, each associated with one of the computing cores. The computing device further includes a plurality of switches, each switch configured to selectively couple a corresponding one of the plurality of components to the first voltage rail. The computing device further includes a controller configured to determine a current operating mode of each of the plurality of computing cores and switch the plurality of switches at a first selected switching rate based on the determined current operating mode of each of the plurality of computing cores.

Abstract: A voltage regulation circuit is suitable to provide an output voltage to a core circuit. The voltage regulation circuit includes a pad, a pull-low unit, a first controlling unit, a second controlling unit and a voltage regulation circuit. The pad receives and provides an input voltage. The pull-low unit generates a pull-low voltage according to the input voltage. The first controlling unit generates a first controlling signal according to the input voltage and the pull-low voltage. The second controlling unit generates a second controlling signal according to the input voltage and the first controlling signal. The voltage regulation unit regulates the input voltage according to the first controlling signal and the second controlling signal, so as to generate the output voltage.

Abstract: A data-processing-circuit comprising: a clock-input-terminal configured to receive a clock-signal; a data-output-terminal configured to provide a data-output-signal; an adjustable-driver-buffer configured to: receive a data-signal; and apply a driver-strength-value to the data-signal in order to provide a data-output-signal, wherein the current level of the data-output-signal is based on the driver-strength-value; and a driver-control-module comprising: a time-alignment-module configured to: process the clock-signal and the data-output-signal in order to determine a timing-delay-signal that is representative of a time delay between: a transition in the clock-signal; and a transition in the data-output-signal; provide the driver-strength-value for the adjustable-driver-buffer based on the timing-delay-signal and a target-delay-signal, wherein the driver-strength-value is for reducing a difference between: the timing-delay-signal; and the target-delay-signal.

Abstract: A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.

Abstract: An asynchronous pipeline includes a first stage and one or more second stages. A controller provides control signals to the first stage to indicate a modification to an operating speed of the first stage. The modification is determined based on a comparison of a completion status of the first stage to one or more completion statuses of the one or more second stages. In some cases, the controller provides control signals indicating modifications to an operating voltage applied to the first stage and a drive strength of a buffer in the first stage. Modules can be used to determine the completion statuses of the first stage and the one or more second stages based on the monitored output signals generated by the stages, output signals from replica critical paths associated with the stages, or a lookup table that indicates estimated completion times.

Abstract: Various aspects provide for a multiplexer for high-speed serial links. For example, a system can include a first stage data path multiplexer circuit and a second stage data path multiplexer circuit. The first stage data path multiplexer circuit comprises a first inverter circuit to select a first data signal from a set of data signals and a second inverter circuit to select a second data signal from the set of data signals. The first inverter circuit comprises a first set of inverters and a first set of transmission gates. The second inverter circuit comprises a second set of inverters and a second set of transmission gates. The second stage data path multiplexer circuit is configured as a third inverter circuit to select the first data signal or the second data signal as an output data signal. The third inverter circuit comprises a third set of inverters and a third set of transmission gates.

Abstract: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.

Abstract: Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.

Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.

Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.

Abstract: Systems and methods for securing embedded devices via both online and offline defensive strategies. One or more security software components may be injected into firmware binary to create a modified firmware binary, which is functionally- and size-equivalent to the original firmware binary. The security software components may retrieve live forensic information related to embedded devices for use in live hardening of the modified firmware binary while the embedded device is online, dynamically patching the firmware. In addition, the live forensic information may be aggregated with other analytical data identifying firmware vulnerabilities. A vulnerability identification and mitigation system can then identify and inject modifications to the original firmware binary to develop secure firmware binary, which may be imaged and loaded onto one or more embedded devices within a network.

Abstract: In certain aspects of the disclosure, an apparatus comprises a latching element having a data input, a first feedback input, a second feedback input, and an output. A pull-up input block is coupled to the data input and has at least a first pull-up input, and a pull-down input block is also coupled to the data input and has at least a first pull-down input. A feedback pull-down block implementing a logic function complementary to the pull-up input block is coupled to a feedback pull-down control device and responsive to the first pull-up input, and a feedback pull-up block implementing a logic function complementary to the pull-down input block is coupled to a feedback pull-up control device and responsive to the first pull-down input. The pull-up input block and pull-down input block are guaranteed not to be enabled concurrently.

Abstract: A voltage level shifting circuit includes two PMOS transistors and four NMOS transistors. Sources of the PMOS transistors receive a first supply voltage value, a first PMOS transistor gate coupled with drains of second PMOS and NMOS transistors is a first output, and a second PMOS transistor gate coupled with drains of first PMOS and NMOS transistors is a second output. The first NMOS transistor source is coupled with a third NMOS transistor drain, and the third NMOS transistor gate is a first input. The second NMOS transistor source is coupled with a fourth NMOS transistor drain, and the fourth NMOS transistor gate is a second input. A voltage generating circuit generates a voltage at first and second NMOS transistor gates based on the first supply voltage value and on a signal, the signal behaving based on the first supply voltage value and a different second supply voltage value.

Abstract: A power semiconductor module includes an insulated-gate type power semiconductor device, and a drive circuit controlling a gate voltage applied to the power semiconductor device in accordance with an input signal to drive the power semiconductor device so as to turn ON and OFF. The drive circuit includes a variable resistance circuit changing the gate voltage to the power semiconductor device, and a short-circuit state detecting circuit which maintains the resistance value of the variable resistance circuit to be a predetermined value at the time of a normal operation of the power semiconductor device, and which increases the resistance value of the variable resistance circuit so as to be greater than the predetermined value when a short-circuit state of the power semiconductor device is detected to suppress an oscillation in the power semiconductor device.

Abstract: Disclosed are devices, systems, apparatus, methods, products, media and other implementations, including a method that includes triggering a beacon circuit combined with a hardware-based protection module, included within a hardware device, the hardware-based protection module configured to provide protection against malicious implementations within the hardware device, with the beacon circuit being configured to provide a beacon output when triggered. The method further includes determining based on the beacon output provided by the triggered beacon circuit whether the hardware device includes at least one malicious implementation.

Abstract: A transmitter includes: an output driver that outputs differential signals to differential signal lines; first termination resistors and a first switch which are provided in series between a first reference voltage input terminal to which a reference voltage is inputted and the differential signal lines; a pulse generator that outputs a common-mode pulse to the differential signal lines during a period during which a pulse output instruction signal is at a significant level; and a detector that outputs a detection result signal indicating a magnitude relationship between a voltage level of the common-mode pulse and a threshold, during a period during which the pulse output instruction signal is at a significant level, and outputs a detection result signal indicating that the voltage level of the common-mode pulse does not exceed the threshold, during a period during which the pulse output instruction signal is at a non-significant level.

Abstract: A circuit includes: a first type of swing reduction circuit coupled between an input/output pad and a buffer circuit; and a second type of swing reduction circuit coupled between the input/output pad and the buffer circuit, wherein the first type of swing reduction circuit is configured to increase a voltage received by respective gates of a first subset of transistors of the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage, and the second type of swing reduction circuit is configured to reduce a voltage received by respective gates of a second subset of transistors of the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

Abstract: A number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits.

Abstract: A radiation-hardened electronic system is disclosed. The radiation-hardened electronic system includes a reconfigurable analog circuit block, a digital configuration logic circuit block, and a radiation-hardened isolation latch circuit connecting between the reconfigurable analog circuit block and the digital configuration logic circuit block. The reconfigurable analog circuit block includes multiple analog inputs and outputs. The digital configuration logic circuit block includes multiple digital inputs and outputs for controlling various functionalities of the reconfigurable analog circuit block via a set of configuration data. The radiation-hardened isolation latch circuit prevents the configuration data from entering the reconfigurable analog circuit block when the configuration data has been corrupted by a SEU.

Abstract: A method and circuit for implementing a level shifter for translating logic signals to output voltage analog levels, and a design structure on which the subject circuit resides are provided. The circuit includes a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string is connected between an analog voltage rail and an analog ground. A plurality of level shifter cascaded inverters are connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground. An output of the level shifter is programmed by the level shifter resistor divider string connected to the cascaded inverters.

Abstract: A gate potential control device configured to control potential of a gate of a main switching element is provided herein. The gate potential control device includes: a turn-on switching element and a turn-off switching element. In a turn-off operation, a main voltage between main terminals of the main switching element increases from an on-voltage to a peak value of a surge voltage and then decreases to an off-voltage. The gate potential control device is configured to keep both of the turn-on switching element and the turn-off switching element turned off in a period which is at least a part of a specific period in the turn-off operation, the specific period being from a timing after a predetermined time lapse from a timing of rise-up of the main voltage from the on-voltage to a timing at which the main voltage reaches the peak value.

Abstract: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.