Abstract: Embodiments herein describe normalizing an output of a TDC in a DPLL to a resolution of the TDC. A DTC can delay a reference clock which is then input into the TDC. The TDC outputs a digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a DCO in the DPLL. This digital code is normalized to a resolution of the TDC and the result is filtered by a DLF.

Abstract: A dynamically configurable clock divider may include a multifrequency clock divider circuit for generating a programmable frequency output clock signal from a given frequency input clock signal may include a first counter, and a second counter. The second counter may alternate between an active state and an inactive state with opposite states of the first counter to control delivery of the programmable frequency clock signal. When the first counter is programmed to be transitioned from the inactive state to the active state, the second counter may continue to maintain the active state and a previous frequency value of the output clock signal for a predetermined number of clock signals before transitioning to the inactive state and handing control of the output clock signal to the first counter which assumes the active state.

Abstract: An apparatus for generating an output oscillator signal is provided. The apparatus includes a deviation determining circuitry configured to generate a deviation signal based on a first comparison signal and a second comparison signal. Further, the apparatus includes a first oscillator configured to generate the output oscillator signal based on the deviation signal and a second oscillator signal from a second, resonator-based oscillator. The first comparison signal is based on the second oscillator signal or the output oscillator signal. The second oscillator signal has a frequency of at least 1 GHz. The second comparison signal is based on a third oscillator signal from a third oscillator. The third oscillator signal has a frequency lower than 1 GHz.

Abstract: A receiver comprising a signal phase shifting block generating concurrent phase shifted copies of an input signal, and an impedance translation function block configured to receive the phase shifted copies of the input signal and generate a down converted signal wherein the impedance translation function block is driven by a single clock signal of frequency determined by a desired carrier frequency. The receiver including an energy harvesting block coupled to the phase shifting block to receive one or more in-band or out-of-band interferers in the input signal and reflected signals from the impedance translation function block due to nonlinearities.

Abstract: A system and method for jetting a viscous material includes an electronic controller and a jetting dispenser operatively coupled with the electronic controller. The jetting dispenser includes an outlet orifice and a piezoelectric actuator operatively coupled with a movable shaft. The jetting dispenser is under control of the electronic controller for causing said piezoelectric actuator to move the shaft and jet an amount of the viscous material from the outlet orifice. The electronic controller sends a waveform to the piezoelectric actuator to optimize control of the jetting operation.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Abstract: In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.

Abstract: A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit includes a control circuit and a signal generation circuit. The control circuit is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit is configured to receive the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the frequency control word, and the spread spectrum output signal corresponds to the frequency control word.

Abstract: An amplifier includes: a circuit pattern providing a plurality of signal paths having different lengths; a transistor chip; a plurality of pads of transistor cells, the pads being electrically connected to the circuit pattern and being arranged on the transistor chip; a plurality of the transistor cells; a plurality of transmission lines for connecting each of the plurality of pads and each of the plurality of transistor cells, the transmission lines being arranged on the transistor chip, and a plurality of harmonic processing circuits each connected to each of the plurality of transmission lines and arranged on the transistor chip. The plurality of harmonic processing circuits each has a capacitor and an inductor, and a product of the capacitance of the capacitor and the inductance of the inductor is made constant in each of the plurality of harmonic processing circuits.

Abstract: A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.

Abstract: Portable communications device and method for full duplex operation in a time division multiple access radio system. The method includes providing a switch for connecting one of a first voltage controlled oscillator and a second voltage controlled oscillator to a synthesizer. The synthesizer generates a first frequency when connected to the first voltage controlled oscillator and generates a second frequency when connected to the second voltage controlled oscillator. The method also includes controlling, using an electronic processor coupled to the switch, the switch to connect the first voltage controlled oscillator to the synthesizer for a first timeslot, and controlling, using the electronic processor, the switch to disconnect the first voltage controlled oscillator from the synthesizer and connect the second voltage controlled oscillator to the synthesizer for a second timeslot. The second timeslot is immediately adjacent to the first timeslot.

Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

Abstract: A clock signal generated by a fractional-N phase-locked loop circuit may include deterministic jitter resulting from a sigma-delta modulation of a frequency divisor used by a divider circuit. In order to reduce such jitter, a cancelation circuit is employed that can generate a feedback signal by delaying an output signal from the divider circuit, where the amount of delay applied to the output signal is based on an accumulated phase residue from the modulation of the frequency divisor. The resultant feedback signal is compared to a reference signal, results of which are used to adjust an oscillator circuit generating the clock signal, thereby reducing the deterministic jitter.

Abstract: A time difference amplifier (TDA) including a first delay storage unit (DSU) configured to generate a first output signal including a first transition in response to a first transition of a first input signal and a first transition of a first read signal, and a second DSU configured to generate a second output signal including a second transition in response to a second transition of a second input signal and a second transition of a second read signal. A first delay between the first and second transitions of the first and second output signals is based on a second delay between the first and second transitions of the first and second input signals and a third delay between the first and second transitions in the first and second read signals. First and second delay elements generate the first and second read signals by delaying the first and second input signals.

Abstract: A method for measuring a capacitive sensor output may include applying an excitation signal to a capacitor of the capacitive sensor which causes generation of a modulated signal from a baseband signal, wherein the excitation signal is of a carrier frequency which is higher than frequency content of the baseband signal, demodulating the modulated signal to generate an intermediate signal representative of a capacitance of the capacitor wherein the demodulating is based, at least in part, on the excitation signal, converting the intermediate signal into a pulse-density modulated output signal with a pulse-density modulator, and shaping a noise transfer function of the pulse-density modulator to have an approximate zero at the carrier frequency.

Abstract: A frequency locked loop, an electronic device, and a frequency generation method are provided. The frequency locked loop includes: a control circuit, configured to judge a size relationship between an input frequency and a feedback frequency to obtain a control signal, and determine a frequency control word according to the control signal, in which the control signal includes a first sub-control signal and a second sub-control signal, the control circuit is configured to generate the first sub-control signal in a case where the input frequency is greater than the feedback frequency, and the control circuit is configured to generate the second sub-control signal different from the first sub-control signal in a case where the input frequency is less than the feedback frequency; and a digital control oscillation circuit, configured to generate and output an output signal having a target frequency according to the frequency control word.

Abstract: A phase adjustment circuit includes: a local frequency band phase shifter that adjusts a phase of a signal in a local signal frequency band and that outputs the adjusted signal; a frequency-converting mixer that receives the adjusted signal and another signal different from the adjusted signal, and that mixes the adjusted signal with the other signal; and a buffer amplifier that is provided between the local frequency band phase shifter and the frequency-converting mixer, and that is capable of amplifying an input power that is to be input to the frequency-converting mixer so that the input power is up to be in an input power range in which an input-output characteristic of power of the frequency-converting mixer is out of a linear region.

Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.

Abstract: This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.

Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.

Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

Abstract: Various implementations described herein are directed to an integrated circuit that has memory circuitry with a memory structure and a reference path. The integrated circuit includes performance sensing circuitry having a logic structure that is adapted to detect variation of performance of the memory structure. The integrated circuit includes power management circuitry that is coupled to the memory circuitry and the performance sensing circuitry. The power management circuitry receives a feedback signal from the performance sensing circuitry and adaptively adjusts voltage provided to the memory circuitry based on the feedback signal to affect performance of the memory structure. The memory circuitry has a logic stage that reduces signal delay in the reference path for alignment with the adaptively adjusted voltage.

Abstract: A spur target frequency is periodically determined to cancel a spur using a spur cancellation circuit in a first phase-locked loop (PLL) in a system with at least a second PLL that is in lock with the first PLL. The spur target frequency is periodically determined utilizing divide ratios of the first PLL and the second PLL to determine the updated spur target frequency. As one or more of the divide ratios change, the spur frequency changes and the spur target frequency is updated to reflect the change.

Abstract: A method of operating a computer mouse includes receiving electromagnetic (EM) radiation emitted from a source external to the computer mouse, the received EM radiation induces noise within one or more bands of noise frequencies and an image sensor circuit of the computer mouse generates erroneous movement detection signals in response to an operating frequency of the image sensor circuit being within the one or more bands of noise frequencies. The method further includes determining the operating frequency of the image sensor circuit, comparing the operating frequency to a target frequency, wherein the target frequency is outside of the one or more bands of noise frequencies, and tuning the operating frequency of the image sensor circuit towards the target frequency.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL.

Abstract: A circuit and a method for automatically calibrating a phase interpolator are provided. Phase information of a reference clock signal and an output clock signal are processed by a phase detector to detect a phase difference of the two clock signals. A difference value between the phase difference and a standard phase difference corresponding to the digital control code is obtained, to generate compensation information. The compensation information is sent to the phase interpolator control unit for storage. When the phase interpolator operates normally, a phase interpolator control unit generates a control signal based on the compensation information, to regulate the phase value of the output clock signal of the phase interpolator.

Abstract: A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

Abstract: Superconducting device applications implemented with a surface acoustic wave resonator and a superconducting microwave resonator coupled to a Josephson ring modulator are provided. A method can comprise receiving, by a microwave Josephson mixer, and from a superconducting surface acoustic wave resonator of a superconducting device, a surface acoustic wave signal that comprises one or more phonons that resonate at a first frequency. The method can also comprise receiving, by the microwave Josephson mixer and from a superconducting microwave resonator of the superconducting device, a microwave signal that comprises one or more photons that can resonate at a second frequency. Further, the method can also comprise mixing, by the microwave Josephson mixer, the surface acoustic wave signal and the microwave signal based on a microwave control signal received from a microwave source operatively coupled to the microwave Josephson mixer.

Abstract: A mobile communication device adapted to perform spur relocation for a digital phase-locked loop includes a receiver to determine a first frequency channel of interest and to identify a first frequency command word corresponding to the first frequency channel of interest. The mobile communication device further includes control logic circuitry to identify a first frequency at which a first fractional spur associated with the first frequency command word starts to occur and to determine whether the identified first frequency is within the first frequency channel of interest. In addition, the mobile communication device includes a programmable feedback divider configured to change the first frequency command word to a second frequency command word, wherein a second fractional spur associated with the second frequency command word occurs at a second frequency outside the first frequency channel of interest.

Abstract: A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes (2n?(2m?1)) first delay units connected in series, and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes (2n+(2m?1)) second delay units connected in series, and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and n?m. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.

Abstract: Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to generate an output clock and includes a phase interpolator, a logic circuit, and an integrator. The phase interpolator is configured to generate by interpolation an intermediate clock according to a first reference clock, a second reference clock, and a control signal. The frequencies of the first reference clock, the second reference clock and the intermediate clock are substantially the same. The logic circuit is coupled to the phase interpolator and configured to generate the output clock according to the intermediate clock and one of the first reference clock and the second reference clock. The integrator is coupled to the phase interpolator and the logic circuit and configured to generate the control signal according to the output clock. The control signal varies with an average based on a duty cycle of the output clock.

Abstract: A TAF-DPS based circuits and methods to improve electronic system's frequency accuracy and enhance its frequency stability is disclosed in this application. Present invention creates a circuit architecture and a calculation scheme for compensating frequency source's frequency error. Present invention further discloses a method of incorporating said scheme into functional chip built in either ASIC or FPGA fashion. Present invention further presents a method of using TAF-DPS-frequency-compensation-scheme-equipped-chips as nodes in electronic network. As a result, the circuit and apparatus disclosed in present invention can improve electronic system's performance from the time synchronization perspective.

Abstract: A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.

Abstract: Systems, methods, and devices are provided for correcting compression distortion of wireless signals due to variations in operation parameters of the radio frequency system. The method may include using circuitry to generate a reference signal that is not pre-distorted by a processing block. The method may involve receiving an envelope signal representative of a signal being transmitted by a transceiver. The method may also involve determining a first peak-to-average ratio of the envelope signal and receiving a second peak-to-average ratio of the reference signal. The method may additionally involve determining a difference between the first peak-to-average ratio and the second peak-to-average ratio. The method may also include adjusting a gain of an amplifier of the transceiver based on the difference.

Abstract: A radio frequency (RF) mixer is provided. The RF mixer includes two linear-in-the-amplitude-domain RF channels connected in parallel, with each of the two linear-in-the-amplitude-domain RF channels having of an input RF signal applied equally to each channel. Two controllable gain devices are structured to receive the input RF signal. A local oscillator (LO) communicates with both of the controllable gain devices, with one of the controllable gain devices receiving a signal from the LO directly, and the other controllable gain device receiving a signal from the LO after a phase of the LO signal is reversed by a phase inverter. Finally, an output of each of the linear-in-the-amplitude-domain RF channels is combined to form a common intermediate frequency (IF) output.

Abstract: Operational configuration and temperature compensation methods are provided for bulk acoustic wave (BAW) resonator devices suitable for operating with liquids. Temperature compensation methods dispense with a need for temperature sensing, instead utilizing a relationship between (i) change in frequency of a BAW resonator at a phase with adequate sensitivity and (ii) change in frequency of a phase that is correlated to temperature. Operational configuration methods include determination of an initial phase response of a BAW resonator in which temperature coefficient of frequency is zero, followed by comparison of sensitivity to a level of detection threshold for a phenomenon of interest.

Abstract: At least one embodiment relates to generating at least one RF signal based on at least one digital baseband signal at a first clock rate. At least one digital pulse sequence at a second clock rate corresponding to a center frequency of the RF signal is modulated based on the digital baseband signal. Pulses of the pulse sequence are quantized based on a time grid of a third clock rate. A ratio between a number of second clock cycles corresponding to one first clock cycle and a number of third clock cycles corresponding to one first clock cycle is non-integer.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.

Abstract: An apparatus includes a control circuit configured to generate a frequency divider control signal approximating a fractional divide ratio. The apparatus includes a frequency divider configured to generate an output clock signal based on an input clock signal and an adjusted frequency divider control signal. The output clock signal is a frequency-divided version of the input clock signal. The apparatus includes a measurement circuit configured to provide digital time information corresponding to an edge of the output clock signal. The apparatus includes an adaptive adjustment circuit configured to generate the adjusted frequency divider control signal based on the frequency divider control signal and the digital time information.

Abstract: In some aspects, a method for phase multiplexing includes receiving a plurality of phases, selecting one of the plurality of phases based on a select signal using a multiplexer, and outputting the selected one of the plurality of phases at an output of the multiplexer. The method also includes gating the output of the multiplexer during a glitch at the output of the multiplexer.

Abstract: Upstream noise suppression circuits include a splitter and a combiner that are connected by first and second communications paths. An information signal removal circuit is provided on the second communications path and is configured to remove an upstream information signal therefrom. A phase shifter is also provided on the second communications path between the upstream information signal removal circuit and the combiner.

Abstract: An electrical connector includes: an insulative housing; and an inserting module positioned in the insulative housing and including a transformer, the transformer comprising: a magnetic core having a central opening; and a first and second wire groups each including plural wires, each wire having a central portion, a first end, and an opposite second end, the central portions of each wire group wound around the magnetic core through the central opening, wherein the first and second wire groups joint to function as a primary winding and a secondary winding of the transformer, and a wire diameter of the secondary winding is greater than a wire diameter of the primary winding.

Abstract: An apparatus is disclosed for hybrid-controlled clock generation. In an example aspect, the apparatus includes an analog control circuit, a digital control circuit, a transistor array, an oscillator circuit, and a selection circuit. The oscillator circuit is coupled to the transistor array. The selection circuit includes a first input that is coupled to the analog control circuit, a second input that is coupled to the digital control circuit, and an output that is coupled to the transistor array. The selection circuit is configured to obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit. The selection circuit is also configured to connect, based on the selection signal, the analog control circuit or the digital control circuit to the transistor array.

Abstract: According to one embodiment, a radio frequency (RF) receiver circuit includes a low noise amplifier, a poly-phase filter, and an in-phase quadrature (IQ) mixer circuit coupled between the low noise amplifier and the poly-phase filter. The IQ mixer circuit includes an IQ generator having a differential in-phase input port, a differential in-phase output port, and a differential quadrature output port; a first frequency mixer having a differential local oscillator (LO) input port, where the differential LO input port of the first frequency mixer are coupled to the differential in-phase output port of the IQ generator to drive the first frequency mixer; and a second frequency mixer having a differential LO port, where the differential LO input port of the second frequency mixer are coupled to the differential quadrature output port of the IQ generator to drive the second frequency mixer.

Abstract: A semiconductor device includes an oscillator that oscillates at a specific frequency, a semiconductor integrated circuit that integrates a temperature sensor that detects a peripheral temperature, and a controller that is electrically connected to the oscillator and that corrects temperature dependent error in the oscillation frequency of the oscillator based on the temperature detected by the temperature sensor and a sealing member that integrally seals the oscillator and the semiconductor integrated circuit.

Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

Abstract: It is to provide a technique capable of controlling the throughput and the power consumption of a semiconductor device at a desired ratio. A semiconductor device includes a clock generation circuit that generates a clock signal and a data processing unit that receives the clock signal. The clock generation circuit includes an oscillator that generates a source clock signal, an output circuit that outputs a clock signal with the source clock signal enabled, and a control circuit having a setting circuit in which the data processing unit sets the ratio of the enable. The semiconductor device can change the frequency of the clock signal by partially permitting or prohibiting the source clock signal in time.

Abstract: A binary signal generator circuit includes a programmable waveform generator (PWG) having an input stage for receiving a digital data stream, a serial clock signal for controlling receipt of the digital data, a frequency synchronization and a clock signal. The PWG includes registers including a first and second register for storing bits representing a first frequency (f1) and for storing bits representing a zero frequency (fo), respectively. A MUX receives a control signal based on the digital data for toggling between bits representing f1 and fo coupled to a digital-to-analog converter (DAC) with an output providing a modulated signal that toggles between essentially f1 and essentially fo. A differential output amplifier receives the modulated signal for generating a first and second amplified signal modulated between essentially f1 and essentially fo. The first and second amplified signal are phase shifted relative to one another, taken together providing a differential signal.

Abstract: Systems and methods for controlling a process applied to a substrate within a plasma chamber are described. The systems and methods include generating and supplying odd harmonic signals and summing the odd harmonic signals to generate an added signal. The added signal is supplied to an electrode within the plasma chamber for processing the substrate. The use of odd harmonic signals facilitates high aspect ratio etching of the substrate.