Abstract: A circuit includes an input terminal, a first transistor, a second transistor, a comparator, a voltage reference circuit, and a control circuit. The first transistor includes a first terminal coupled to the input terminal. The second transistor includes a first terminal coupled to the input terminal. The comparator includes a first terminal coupled to the input terminal. The voltage reference circuit is coupled to a second terminal of the comparator. The control circuit includes an input, a first output, and a second output. The input is coupled to an output of the comparator. The first output is coupled to a second terminal of the first transistor. The second output is coupled to a second terminal of the second transistor.

Abstract: An LVDS driver circuit includes: a current source; a differential unit configured to receive a first input signal and a second input signal and output a first output signal and a second output signal; and a feedback control circuit configured to be coupled to a first output node and a second output node and to perform, by outputting a control voltage to a gate of a transistor, feedback control that sets a common voltage of a differential output signal. In the differential unit, the first output node and the second output node are in a high impedance state in the high impedance mode, the differential unit is configured to output the first output signal and the second output signal in the signal output mode, and the control voltage in the high impedance mode is larger than the control voltage in the signal output mode.

Abstract: A random code generator includes a memory cell, two write buffers and two sensing circuits. The memory cell includes a first program path between a first source line and a first bit line, a second program path between the first source line and a second bit line, a first read path between a second source line and a third bit line, and a second read path between a third source line and a fourth bit line. The two write buffers are connected with the first bit line and the second bit line, respectively. The two sensing circuits are connected with the third bit line and the fourth bit line, respectively. The two sensing circuits generate a first output signal and the second output signal to the corresponding write buffers according to the read currents in the corresponding read paths.

Abstract: Disclosed is a mass analysis apparatus and method, wherein the precision of detection of a first material including a second material is improved, without enlarging the apparatus, and the measurement time is reduced. The mass analysis apparatus for analyzing a sample containing a first material including an organic compound and at least one second material including an organic compound and having a mass spectrum peak overlapping that of the first material includes a peak correction unit, wherein, when an intensity ratio (peak B)/(peak A) of peak A, not overlapping that of the first material, and peak B, overlapping that of the first material, is a correction coefficient (W), an intensity of a net peak D of the mass spectrum of the first material is calculated by subtracting W×(intensity of peak A) from an intensity of a peak C of the mass spectrum of the first material in the sample.

Abstract: A readout circuit, for at least one sensing element, includes an amplifier including an input node for receiving charges from the sensing element or elements and an output node, a first feedback loop comprising a feedback capacitor, and at least one second feedback loop comprising another feedback capacitor, between the output and input nodes of the amplifier, for defining different gains. The at least two feedback capacitors being each connectable to a reference voltage supply via respective switches, for pre-loading the feedback capacitors with a predetermined charge different from the charge obtainable from the at least one sensing element, for sampling signals at a reset level before charge transferal. The loops comprising a respective switch between their capacitors and the output node, for operatively connecting and disconnecting each loop, for obtaining reset voltages at two different gains and signal voltages at two different gains.

Abstract: A single prong, multiple signal conducting plug and plug detection circuitry is provided. The plug may be electrically coupled to a stereo headset including a microphone. The plug may include four signal conducting regions arranged in a predetermined order along the length of the prong. Detection circuitry may be operative to determine whether a microphone type of plug (e.g., a four region plug including a microphone region and two audio regions, or a three region plug including microphone region and only one audio region) or a non-microphone type of plug (e.g., stereo plug) is inserted into the jack of an electronic device (e.g., mobile phone). Detection circuitry may also detect user activated functions performed in response to user activation of one or more switches included with the headset. For example, the headset may include a single switch for performing a function with respect to a microphone (e.g., end-call function).

Abstract: A power-on reset circuit with hysteresis includes a current mirror, a voltage division circuit, a hysteresis control circuit, and a logic driver. The current mirror is coupled to an external supply voltage. The voltage division circuit generates a first control voltage according to the external supply voltage. The hysteresis control circuit generates a second control voltage according to the external supply voltage and the first control voltage. The logic driver generates an output voltage according to the second control voltage. The hysteresis control circuit further defines a first threshold voltage and a second threshold voltage which are different from each other, such that the logic switching state of the output voltage is determined by comparing the external supply voltage with the first threshold voltage or the second threshold voltage.

Abstract: The present invention relates to analogue-to-digital converter circuitry, and in particular to alignment between one set of analogue-to-digital circuitry and another set. Such sets may be referred to as converter channels.

Abstract: An electronic magnetic bearing fault-tolerant drive module includes a first plurality of switching elements and a second plurality of switching elements. At least one winding is interposed between the first plurality of switching elements and the second plurality of switching elements. The first and second switching elements are configured to selectively operate in a first mode and a second mode to generate an electromagnetic field. The electronic magnetic bearing fault-tolerant drive module is configured to detect one or more electrical faults including an open-circuit fault of at least one of the first and second switching elements.

Abstract: Methods and systems of pre-balancing a switched capacitor converter are provided. A first comparator includes a positive input configured to receive a voltage across an output capacitor and a negative input configured to receive a first hysteresis voltage. A second comparator includes a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter and a negative input configured to receive a second hysteresis voltage. A first current source is coupled between the output capacitor and GND and is configured to discharge the output capacitor upon determining that the voltage across the output capacitor is above a tolerance provided by the first hysteresis voltage. A second current source is coupled between the input capacitor and GND and is configured to discharge the input capacitor upon determining that the voltage across the input capacitor is above a tolerance provided by the second hysteresis voltage.

Abstract: A level shifter circuit to translate a first voltage level and a second voltage level of a signal is disclosed. The level shifter circuit includes a comparator. The comparator includes an input differential transistor pair with a matched current mirror load. The level shifter also includes a parallel signal path circuit to reduce the voltage transition lag caused by the comparator, a hysteresis adjusting device and a reference voltage generator circuit to provide a reference voltage to the comparator.

Abstract: A spreading sequence generator for a first radio frequency (RF) transceiver receives an RF signal from a second RF transceiver. The first RF transceiver measures power levels of the received RF signal at a plurality of instants to generate respective digital power level values and uses the plurality of digital power level values to create a first spreading sequence. The second RF transceiver receives an RF signal from the first RF transceiver and performs the same functions to create a second spreading sequence. Due to the reciprocal nature of the RF channel between the first and second RF transceivers, the first and second cryptographic keys match.

Abstract: An electronic circuit includes a transmitter with a first output configured to be connected to a first signal line of a signal bus, a second output configured to be connected to a second signal line of a signal bus, and an input configured to receive an input signal; and a ringing suppression circuit with a third output configured to be connected to the first signal line, and a fourth output configured to be connected to the second signal line. The transmitter is configured to operate in one of a first operating state or a second operating state dependent on the input signal. The ringing suppression circuit is configured to detect a change from the first operating state to the second operating state of the transmitter, and to operate in a ringing suppression mode for a predefined time period in response to detecting the change.

Abstract: Systems, devices, methods, and techniques are disclosed for open load detection in the connections coming from output stages of electrical systems. In some examples, an open load detection circuit includes a circuit output configured to provide an output voltage to a load, a first switch coupled to the circuit output and coupled to a first supply voltage configured to switch the load, and at least one delta voltage circuit coupled to the circuit output configured to provide a delta voltage. The at least one delta voltage circuit is coupled to the first switch to create a reduction in voltage magnitude of the first supply voltage to a switch voltage of the first switch provided to the circuit output. The open load detection circuit also includes at least one current source coupled to the circuit output to provide a current to the circuit output.

Abstract: Various embodiments relate to signal processing and, more particularly, to processing of received speech signals to preserve and enhance speech intelligibility. In one embodiment, a communications apparatus includes a receiving path over which received speech signals traverse in an audio stream, and an dynamic audio enhancement device disposed in the receiving path. The dynamic audio enhancement (“DAE”) device is configured to modify an amount of volume and an amount of equalization of the audio stream. The DAE device can include a noise level estimator (“NLE”) configured to generate a signal representing a noise level estimate. The noise level estimator can include a non-stationary noise detector and a stationary noise detector. The noise level estimator can be configured to generate the signal representing a first noise level estimate based on detection of the non-stationary noise or a second noise level estimate based on detection of the stationary noise.

Abstract: Per-port performance optimization may be provided. First, performance data may be received corresponding to each of a plurality of ports. Then it may be determined that performance of at least one of the plurality of ports can be improved based on the received performance data corresponding to the least one of the plurality of ports. Next, in response to determining that the performance of the at least one of the plurality of ports can be improved, at least one of a plurality of components may be adjusted corresponding to the at least one of the plurality of ports to improve performance of the least one of the plurality of ports.

Abstract: The present document relates to the measurement of the current through a transistor. In particular, the present document relates to a circuit arrangement which allows an accurate measurement of the current through a power transistor. A circuit arrangement is described. The circuit arrangement is configured to provide an indication of a current flowing through a pass switch, when the pass switch is arranged in parallel to the circuit arrangement. The circuit arrangement comprises a matching unit which comprises a switch bank comprising a plurality of parallel reference switches; a resistor bank comprising a plurality of serial reference resistors; and a reference current source configured to provide a reference current flowing through the switch bank and the resistor bank. The resistor bank and the switch bank are arranged in series.

Abstract: A method for detecting an open-phase condition of a transformer having a grounded-wye high voltage side connection including monitoring current flowing in a neutral connection on the high voltage side of the transformer in real time by voltage relaying and current relaying to identify an open phase condition signature in a signal capable of characterizing change of current magnitude. A current signal may be injected onto the neutral terminal and the zero-sequence mode of the transformer monitored to detect an open-phase condition indicated by an increase in network impedance and decrease or elimination of the injection current.

Abstract: A method for generating spread spectrum spreading sequences in communicating devices. A first device receives a first sequence of one or more signals from a second device, sends a second sequence of one or more signals to the second device, samples the first sequence of one or more signals, generates sampling results, and generates a spreading sequence based on the sampling results. The second device receives the second sequence and creates an identical spreading sequence using an identical process to create sampling results and generate the sequence. The spreading sequence may be used by the first and second devices for spread spectrum communications with each other. Gain for spread spectrum communications may be dynamically varied based on available bandwidth by varying the number of signals and sampling rate.

Abstract: A switch is provided having a switch transistor as well as a monitoring component to monitor a control signal applied to the switch transistor. With the monitoring component, in some implementation a monitoring of the control signal independent from a load path may be possible.

Abstract: The present invention appropriately detects line-breakages in a signal line related to a battery connected to a discharge circuit for discharging. Namely, an initialization operation produces a state in which a capacitor (C1) is charged with the difference between the voltage of a signal line (Vn) and a self-threshold voltage (Vx), and a capacitor (C2) is charged with the difference between the voltage of a signal line (Vn?1) and a self-threshold voltage (Vx), in a comparison circuit (26). In a comparison operation, a voltage adjusting section (ILn+1) produces a state in which line-breakage detection current is drawn out from a signal line (Ln), a signal line (Lc) is connected to the capacitors (C1, C2) and a voltage (DVn) is input to the capacitors (C1, C2). When an output OUT=L level, it is detected that there is no line-breakage, and when the output OUT=H level, it is detected that there is a line-breakage.

Abstract: A circuit for setting a threshold level for extracting data from a signal stream includes a terminal couplable to the signal stream. A peak detector is coupled to the terminal. A valley detector is coupled to the terminal. A comparator is coupled to outputs of the peak detector and the valley detector for generating a threshold voltage for extracting data or commands from the signal stream. A method of extracting data from a signal stream including: peak detecting the signal stream to generate a first signal; valley detecting the signal stream to generate a second signal; combining the first and second signals to generate a threshold signal; and extracting data from the signal stream utilizing the threshold level signal.

Abstract: Undershoot reduction circuitry includes, for example, a first comparator, a second comparator, and a controller. The first comparator is operable for comparing an indication of a power supply voltage output against a first threshold. The second comparator is operable for comparing an indication of the power supply voltage output against a second threshold. The controller is operable for generating a first power control signal to raise the power supply voltage output when the indication of the power supply voltage output has a first slope and crosses the first threshold and to lower the power supply voltage output when the indication of the power supply voltage output has an opposite slope and crosses the second threshold.

Abstract: A switching device is controlled by a microprocessor to selectively configure the circuit between a current measurement mode and a calibration mode. When the switch is set to the “on” state, the circuit acts as a normal prior art circuit, with the output Vout being read by the microprocessor to determine the current to the load. However, when the switch is set to the “off” state, a small value resistor (which may be roughly three orders of magnitude greater than Rshunt) connects the inputs of the measuring circuit so that the circuit can generate an output Vout corresponding to the zero load current. By connecting the V+ and V? inputs together with a low resistance resistor, the no-load condition Vdiff=V+?V??0 applies. In this state, the no-load offset can be determined by measuring the output voltage of the circuit without turning off the load.

Abstract: A droop detector includes: a plurality of input nodes, each input node configured to receive a supply voltage; an output node; a plurality of detector modules, each detector module comprises: an input terminal coupled to each input node, an output terminal coupled to the output node; and an input tracking unit configured as a voltage follower to detect a droop in the supply voltage coupled to each input node and output an output voltage that follows the supply voltage on the output terminal when the droop is detected on the supply voltage; and a comparator coupled to the output node and configured to output a control signal when the droop is detected.

Abstract: The present document relates to the measurement of the current through a transistor. In particular, the present document relates to a circuit arrangement which allows an accurate measurement of the current through a power transistor. A circuit arrangement is described. The circuit arrangement is configured to provide an indication of a current flowing through a pass switch, when the pass switch is arranged in parallel to the circuit arrangement. The circuit arrangement comprises a matching unit which comprises a switch bank comprising a plurality of parallel reference switches; a resistor bank comprising a plurality of serial reference resistors; and a reference current source configured to provide a reference current flowing through the switch bank and the resistor bank. The resistor bank and the switch bank are arranged in series.

Abstract: Integrated circuits with wireless communications circuitry having peak cancelation circuitry operable to perform crest factor reduction is provided. The peak cancelation circuitry may receive at least first and second carrier waveforms and may include at least a first canceling pulse generator (CPG), a second CPG, a first peak detector for performing peak detection on the first waveform, a second peak detector for performing peak detection on the second waveform, a third peak detector for performing peak detection on a combined waveform of the first and second waveforms, and a pulse allocator that receives clipping information from the three peak detectors and that controls the amount of peak cancelation that is being performed by the two CPGs. The allocator may determine whether the combined waveform contains any peaks. In response to determining that the combined waveform does not contain any peaks, the CPGs may be configured in bypass mode.

Abstract: A voltage measuring device includes an input configured to be coupled to a secondary of an inductive coupling of a DC to DC voltage converter. A switch coupled to the input forms a discharge path parallel to a sampling capacitor dependent on the voltage at the input equaling or exceeding a first voltage threshold and independent of an output voltage at the output of the device. The sampling capacitor is coupled to the output. A rectifier in series with the sampling capacitor is biased to conduct upon the input voltage, minus the output voltage, equaling or exceeding a second voltage.

Abstract: An adaptive over-voltage protection circuit includes an over-voltage protection reference voltage provider and an over-voltage signal output unit. The over-voltage protection reference voltage provider provides a voltage of an over-voltage protection level higher than that of an over-voltage protection voltage corresponding to an output voltage supplied to a load from among a plurality of different over-voltage protection levels as an over-voltage protection reference voltage when the output voltage reaches a range of a rated voltage of the load. The over-voltage signal output unit outputs an over-voltage signal indicating an over-voltage by comparing the over-voltage protection voltage with the over-voltage protection reference voltage.

Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

Abstract: A solid-state image pickup device which includes, on a semiconductor substrate, an image pickup area which includes plural columns of pixels, and plural column amplifier circuits each provided at each column of pixels or at every plural columns of pixels, wherein: each of the column amplifier circuits includes at least two amplifier circuit stages; a preceding amplifier circuit is a variable-gain amplifier circuit and the switchable gains include plural one or more gains; and a subsequent amplifier circuit is capable of amplifying, at one or more gains, the signal amplified at one or more gains in the preceding amplifier circuit.

Abstract: A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit. The pixel signal readout circuit includes a plurality of comparators disposed to correspond to a pixel column array, and a plurality of counters. Each counter includes a first amplifier, a second amplifier, and a mirror circuit to from a current mirror in parallel with the second amplifier. The first amplifier includes differential transistors, initializing switches connected between gates and collectors of the differential transistors, and first and second capacitors connected to each of the gates of the differential transistors. The second amplifier includes an initializing switch and a third capacitor. The mirror circuit includes a gate input transistor whose gate is inputted with a voltage sampled by the first amplifier or a voltage sampled by the second amplifier.

Abstract: This document discusses, among other things, apparatus and methods for a detection circuit. In an example, the detection circuit can include a voltage divider configured to receive a first supply voltage from an external device coupled to the detection circuit, first and second transistors configured to receive a control voltage from the voltage divider and to couple an output to ground when the control voltage exceeds a first threshold, and a bias circuit configured to bias the first transistor to set the first threshold.

Abstract: Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.

Abstract: A method of operating a system including a MEMS device of an integrated circuit die includes generating an indicator of a device parameter of the MEMS device in a first mode of operating the system using a monitor structure formed using a MEMS structural layer of the integrated circuit die. The method includes generating, using a CMOS device of the integrated circuit die, a signal indicative of the device parameter and based on the indicator. The device parameter may be a geometric dimension of the MEMS device. The method may include, in a second mode of operating the system, compensating for a difference between a value of the signal and a target value of the signal. The method may include re-generating the indicator after exposing the MEMS device to stress and generating a second signal indicating a change in the device parameter.

Abstract: Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.

Abstract: A detection circuit includes a differential circuit including a pair of differential transistors configured to receive the input differential signal and a first current source, the pair of the differential transistors having a common output terminal connected to the first current source, a hold capacitor connected between the common output terminal and a reference potential for generating a hold potential, a level sensing circuit configured to sense a voltage level of the input differential signal and output a switching signal, and a switch configured to receive the switching signal and electrically connect the common output terminal and a second current source when the switching signal exceeds a threshold level being lower than the hold potential by a predetermined amount, and electrically disconnect the common output terminal and the second current source when the switching signal stays lower than the threshold level.

Abstract: Hardware interrupt functionality associated with a disable pin may be used to place a near-field communication (NFC) device into various operational modes. For example, various intermediate voltage windows may be defined within an I/O voltage domain and a resistive divider running off an I/O rail may generate multiple reference voltages within the I/O voltage domain. In one embodiment, different comparators may compare voltage on the disable pin to the reference voltages generated with the resistive divider to determine whether the voltage on the disable pin falls within one of the intermediate voltage windows. As such, if a particular comparator determines that the voltage on the disable pin falls within one of the intermediate voltage windows, a control signal may be generated to transition the NFC device into a corresponding operational mode.

Abstract: Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.

Abstract: Embodiments of comparator circuits are disclosed. A comparator circuit may include a differential input circuit, an output circuit, a positive feedback circuit operably coupled between the differential input circuit and the output circuit, and a hysteresis control circuit operably coupled with the positive feedback circuit. The hysteresis control circuit includes a switching device and a transistor. The comparator circuit provides sub-hysteresis discrimination and high speed discrimination.

Abstract: The present invention discloses a signal transmission device performing compensation by filtering characteristics for generating a transmission signal according to a pulse amplitude modulation signal. The signal transmission device comprises: a filtering characteristic compensation circuit for generating a compensation signal according to the pulse amplitude modulation signal and a filtering function; a filter coupled to the filtering characteristic compensation circuit for generating a filtered signal through filtering the compensation signal according to the aforementioned filtering function; and an analog front-end circuit for generating the transmission signal according to the filtered signal.

Abstract: A metering device includes a first transformer that receives an analog waveform and generates a first stepped-down output signal; a second transformer that receives the analog waveform and generates a second stepped-down output signal; first biasing circuitry that receives the first output signal from the first transformer and generates a first digital signal within a first range, wherein the first biasing circuitry includes a switching device for switching between a first and second operational sub-range; second biasing circuitry that receives the second output signal from the second transformer and generates a second digital signal within a second range; and a processor assembly in communication with the first biasing circuitry, wherein if the first digital signal saturates the first operational sub-range, the processor assembly controls the switching device to process the first output signal in the second operational sub-range.

Abstract: The first amplifier operates according a first clock, changes voltages of a first terminal and a second terminal from a first fixed voltage to a second fixed voltage according to a voltage of an input signal and a first reference voltage, respectively, when an on period of a first clock starts, and keeps the voltages of the first and second terminals at the second fixed voltage, respectively, after the voltages of the first and second terminals reach the second fixed voltage and until the on period of the first clock ends, and the first comparator generates first and second logic signals that have logical levels different from each other, based on a difference between the voltages of the first and second terminals when the on period of a second clock whose on period at least partially overlaps with that of the first clock starts.

Abstract: A software optimization system isolates an effect of a change in a control variable from effects of ongoing, unknown changes in other variables. The system discards effects due to noise so that effects of interest to a programmer are more easily visible. The software optimization system treats variations in one or more control variables and in the output of the system as signals. The system varies the control variable at a specific frequency unlikely to correlate with uncontrolled variations in external variables. The system uses digital signal processing (DSP) techniques to filter the output, isolating the frequency of the control variable variation. The system then compares the resulting filtered output to the input to determine the approximate effect of the variation in the control variable.

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor.

Abstract: Disclosed herein is a demodulator, including: a splitting/matching section for carrying out a matching process of making the amplitude and phase of a first modulated signal match respectively the amplitude and phase of a second modulated signal; and a demodulation section for generating a demodulated signal on the basis of the first modulated signal and the second modulated signal, which have been subjected to the matching process carried out by the splitting/matching section, wherein the splitting/matching section has a splitting section, a first matching section, and a second matching section, the first circuit-element constants determining the first input impedance of the first matching section and the second circuit-element constants determining the second input impedance of the second matching section are set at values determined in advance in order to make the first input impedance equal to the second input impedance.

Abstract: An apparatus and a method for recognizing an error in a power bridge circuit containing a load, a high-side branch and a low-side branch. Accordingly, a first switched current source is connected to the load and to a diagnosis connection for a high-potential of a diagnosis voltage, a second switched current source is connected to the load and to a diagnosis connection for a low-potential of the diagnosis voltage, and a control device for controlling the first switched current source and the second switched current source. The control device switches on one of the switched current sources when the high-side power switch and the low-side power switch are open, while the other switched current source is switched off. A testing device tests a voltage at the load when one of the switched current sources is switched on and the other of the switched current sources is switched off.

Abstract: A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a third transistor that connects the first transistor to a power source voltage; a fourth transistor that connects the second transistor to the power source voltage; a fifth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the third transistor; and a sixth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the fourth transistor.

Abstract: Embodiments of the present disclosure may provide a dynamic latch circuit with increased speed and that can perform comparisons on low input signals. The dynamic latch circuit may include a first input transistor receiving a first input signal and a second input transistor receiving a second input signal. A cross coupled inverters may be included to provide a first and second output signals based on the sampled input signals from the first and second input transistors. A reset circuit may be included to reset the first and second outputs to a reference voltage. The latch circuit may include an impedance controller coupled in parallel with the first and second input transistors.