Abstract: A phase locked loop is described for generating an output clock signal that is both synchronizing with a synchronizing signal and oscillating at substantially the same frequency as required by the system. The phase locked loop as disclosed compares the time durations of the output clock of a voltage-controlled oscillator with the system clock for N cycles. A correction signal is then generated by comparing these two time durations, and the correction signal is fed back to the voltage-controlled oscillator to eliminate the difference in the time durations. In addition, the voltage-controlled oscillator is also synchronized with the synchronizing signal by using the synchronizing signal as a reset.

Abstract: A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects whether the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcibly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit.

Abstract: A phase-locked loop which achieves the effect of frequency expansion is disclosed. An adjustable delay element is incorporated in a conventional phase-locked loop in order that one of the output clock signals of a divided-by-N counter and a divided-by-M counter leads (lags behind) the other. This in turn causes a phase frequency detector to alternately generate `up` and `dn` signals, thereby frequency expansion is achieved.

Abstract: A variable frequency oscillator including an oscillation unit including a ring oscillator having multiple loops, and a frequency control unit controlling switching among the multiple loops in accordance with a control input indicative of an oscillation frequency and thus generating an oscillation signal having the oscillation frequency.

Abstract: A phased-lock loop is disclosed for capturing the frequency of the input signal by adjusting a tunable oscillator such that a zero-crossing detector detects a zero-crossing point of the input signal relative to a predetermined number of counts at a counter where a control logic increments a tuning counter to increase the frequency at the tunable oscillator while decrements the tuning counter to decrease the frequency in the tunable oscillator. The predetermined number of counts at the counter representing one period, a fraction of a period, or a multiple of a period of the frequency of the input signal. The control logic adjusts the count at the tuning counter until the tunable oscillator generates an internal frequency that captures the frequency of the input signal.

Abstract: A charge pump of a phase comparator in a phase locked loop is provided a latched comparator to minimize the effect of "dead band" during the time between charging and discharging the loop filter of the charge pump. A latch is inserted between the charging or discharging amplifier and a reset switch which turns on either the charging amplifier or the discharging amplifier. The latch speed up the change over of the charging and discharging action due to regenerative action. The latch can be an asymmetrical flip flop with one inverter fed from a reference current source and a second inverter fed from an on/off current source as controlled by the sourcing command from the phase comparator.

Abstract: A phase locked loop (PLL) oscillating circuit includes a first oscillating circuit, a lock detector and a reference oscillating circuit. The first oscillating circuit generates an oscillation signal with a first frequency, and controls the first frequency based on a reference signal. The lock detector detects phase lock between the oscillation signal and the reference signal to a lock detection signal. The reference oscillating circuit includes a crystal oscillation element, and generates the reference signal. An oscillation state of the reference oscillating circuit is controlled based on the lock detection signal.

Abstract: The synthesis of high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock by using a shift register.

Abstract: A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

Abstract: A digital phase detector and charge pump circuit system reset circuit and method resets a digital phase detector according to the charge outputs between the charge pump circuits and a following loop filter. The sensing circuitry emulates portions of the circuitry of the digital phase detector and charge pump circuit system and minimizes deadband time. Current mirror portions of the charge pump circuit alternate between p-channel and n-channel devices to regularize output voltage levels produced by the charge pump circuit system.

Abstract: A circuit and method for preventing an oscillator from oscillating above a first predetermined frequency or below a second predetermined frequency. The present invention may comprise (a) a clock generation circuit configured to generate an output clock signal in response to (i) a reference clock, (ii) one or more control signals and (ii) a reset signal and (b) a control circuit configured to generate said reset signal in response to said one or more control signals.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a more general terms, a frequency synthesizer is disclosed having a first variable and a second capacitance circuits and frequency control circuitry to coarsely tune the output frequency by adjusting the first control signal and to finely tune the output frequency by adjusting the second control signal.

Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages.

Abstract: In a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system, an analog/digital (A/D) converter performs an A/D conversion upon an analog baseband signal in synchronization with a sampling clock signal having a time period that is a symbol time period. A phase detector receives successive first and third data sampled from the A/D converter, calculates second data by addition of the first and third data, determines whether or not a signal transition formed by the first and third data crosses a zero value within a predetermined deviation, and compares a polarity of the second data with a polarity of one of the first and third data, and generates a comparison result as a phase detection signal when the signal transition crosses the zero value. A loop filter passes a low-frequency component of the phase detection signal therethrough.

Abstract: A clock pulse generator which has a signal controlled oscillator for producing output clock pulses at a repetition rate determined by the value of a control signal. Control means is operative in a calibration cycle to set the control signal to a low or high value and record the clock pulses counted in a period of predetermined duration, to set the control signal to a high or low value and record the clock pulses counted in a period of said predetermined duration, and to calculate rate of change data representing the rate of change of recorded clock pulses with reference to change in the value of the control signal.

Abstract: A Phase-Locked Loop (PLL) system (30) and a method for modifying the output transition time of the PLL system (30). The PLL system has an input stage (36) connected to a PLL (37). The input stage (36) includes a phase detector stage (47), a phase difference threshold stage (48), and a phase difference modification stage (49). The input stage (36) receives a reference input signal and a feedback input signal and determines the phase difference between these two input signals. If the phase difference is greater than a predetermined value, then the input stage (36) decreases the phase difference between the reference input signal and the feedback input signal. If the phase difference is less than the predetermined value, then the phase difference between the reference input signal and the feedback input signal is not modified.

Abstract: Method and circuitry for a frequency synthesizer having wide operating frequency range. The frequency synthesizer uses multiple programmable loadable counters in a phase-locked loop arrangement to generate any combination of clock frequencies based on user programmed values. In a specific embodiment of the invention, the phase-locked loop includes a voltage-controlled oscillator with a built-in programmable phase shift. The present invention further provides a preferred embodiment for a high speed loadable down counter for use in the frequency synthesizer.

Abstract: The present invention provides an analog PLL circuit able to shorten a lockin time during which oscillating frequency and phase of a voltage controlling oscillator settle.An analog PLL circuit according to the present invention comprises a divider, a phase comparator, a charge pump, a low pass filter, a voltage controlling oscillator, and a divider. The voltage controlling oscillator has a ring oscillator composed of a plurality of logic inverting elements capable of changing the delay amount. During the reset period, the initial voltage is inputted to the voltage controlling oscillator via the analog switch, and the initial delay amount is set to each of the logic inverting elements. After the reset period finishes, at the point when the rising edge of the standard input signal is firstly inputted, the output of the D flip-flop becomes high level and the ring oscillator begins the oscillating operation.

Abstract: The switching time of a phase-locked loop (PLL) circuit can be reduced by increasing circuit bandwidth. A charge pump system is commonly used in the PLL circuitry to drive the voltage control oscillator (VCO). The increase in bandwidth intensifies the noise that is contributed by the charge pump system. To reduce charge pump noise, a chopper stabilizer circuit modulates the noise to a sufficiently high frequency so that a low-pass filter may filter out the modulated noise.

Abstract: The present invention provides an apparatus for setting the free-running frequency of a VCO to a reference frequency. The apparatus comprises frequency range means for setting the VCO within a VCO frequency range among a plurality of VCO frequency ranges. First counting means are operable to count to a first value at the VCO frequency rate and to provide a first ending signal when the first value is reached. Second counting means are operable to count to a second value at the reference frequency rate and to provide a second ending signal when the second value is reached. The second counting means are also operable to provide a reference count value when the first value is reached by the first counting means. A state machine is responsive to the first and second counting means for selecting a VCO frequency range among the plurality of VCO frequency ranges such that the VCO free-running frequency obtained through the selected range gives the closest value to the reference frequency.

Abstract: An integrated circuit device and method for synthesis of a signal having a desired frequency and low noise. The integrated circuit embodiment of the invention generally includes a phase locked loop (PLL) circuit used in conjunction with a frequency multiplier. Specifically, the integrated circuit embodiment includes a frequency multiplier connected to a first input of a phase detector, a low pass filter connected between the output of the phase detector and the input of a voltage controlled oscillator (VCO), and a frequency divider connected between the output of the VCO and a second input to the phase detector. The frequency multiplier produces a signal having a frequency that is a multiple of the frequency of a reference signal which is connected to the input of the frequency multiplier. For any desired output frequency, use of the multiplier results in a smaller divider ratio "n" in the PLL, thereby reducing the closed loop noise inside the PLL loop bandwidth.

Abstract: Present-day single or multiple fractional phase-locked loop frequency synthesizers are not phase coherent for they use a digital accumulator modulo a number P with a variable increment K, whose state is a function of the history of the change in values that have been imposed on the increment. This lack of phase coherence rules out the use of these synthesizers in certain fields such as that of Doppler radars. A novel type of single or multiple fractional phase-locked loop frequency synthesizer that is coherent in phase is proposed herein. This type of synthesizer comprises one or more counters with an increment of one, having their rate set by the reference oscillator of the synthesizer and being used in phase memories to enable changes in the increment or increments following a change in the fractional division ratio at instants that are synchronous with the reference oscillator.

Abstract: The phase of a pulsed test signal is measured with reference to a reference signal of constant frequency by sampling the test signal at times determined by transitions in the reference signal and comparing the sampled test signal with the output of a phase accumulator clocked by the reference signal. A resulting measurement signal represents a difference in the number of transitions occurring in the sampled test signal and a reference state signal output by the phase accumulator. The measurement signal may be averaged and integrated to obtain an error signal which may then be filtered to provide a control signal for an oscillator. A digital frequency synthesizer is provided by frequency dividing the output of the oscillator by a constant multiple to obtain the test signal and integrating an offset signal in addition to the averaged measurement signal so that the operating frequency of the oscillator is offset from a nominal frequency by an amount determined by the offset signal.

Abstract: The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One aspect of the present invention is directed to a method and apparatus that disables a charge pump circuit in a phase locked loop circuit when a frequency change in the output signal of the PLL circuit is implemented to limit transient signals generated by the PLL. Another aspect of the present invention is directed to a method and apparatus for coordinating a change in divider values for frequency dividers in a PLL of a CPU to limit transient signals from the PLL.

Abstract: A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising: a voltage controlled oscillator having a control node and an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Abstract: A correction circuit for controlling a correction required circuit includes an oscillator circuit, and a logic circuit which counts an oscillation frequency of the oscillator circuit and thus produces a control signal which causes the oscillator circuit to oscillate at a constant frequency. The control signal changes element values of elements of the oscillator circuit and the correction required circuit so that characteristics of the oscillator circuit and the correction required circuit can be controlled.

Abstract: The present invention is intended to reliably achieve a locked PLL even with a short VFO field to correctly perform subsequent reproduction of information data. A PLL circuit of the present invention is supplied with a composite signal composed of a repetitive signal including a pulse train of a constant duty ratio and a random signal including a pulse train allowing variations in duty ratio, where the two signals are arranged in time series. The circuit is provided with a VCO for generating an output signal having a frequency according to a control signal, a PFC for comparing the repetitive signal with the output signal in terms of phase and frequency to generate a phase frequency error signal, a PC for comparing the random signal with the output signal to generate a phase error signal, and loop filters for extracting predetermined band components of the phase frequency error signal and the phase error signal to generate the control signal.

Abstract: A phase-locked loop circuit adapted to follow up with the phase of an input signal includes a phase comparator 150 for phase-comparing, in synchronism with pre-set operating clocks, an input reference signal to an input signal entered as a counterpart for comparison. Since a first detector 154, a second detector 155 and JK-flip-flops 162, 163 output data responsive to pre-set operating clocks, there is produced no phase lag between NU data and ND data nor the phase lag between two tri-state logical outputs. In a conventional system, the phase lag between NU data and ND data was generated due to the differential delay of the input data caused by looped or the feedback components. Since the two input signals, namely the reference signal and the input signal, are phase-compared to each other in synchronism with the pre-set operating clocks, the comparison data obtained as a result of the phase comparison are outputted at a pre-set period thus reducing the malfunctions otherwise produced in the entire circuit.

Abstract: Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops) and a logic circuit (comprising an exclusive OR circuit, AND circuits and an OR circuit), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesizer apparatus can be activated with low noise and can provide a short lockup time.

Abstract: The present invention, generally speaking, provides improved methods of generating clean, precisely-modulated waveforms, at least partly using digital techniques. In accordance with one aspect of the invention, a "difference engine" is provided that produces a digital signal representing the frequency error between a numeric frequency and an analog frequency. The frequency error may be digitally integrated to produce a digital signal representing the phase error. The difference engine may be incorporated into a PLL, where the analog frequency is that of an output signal of a VCO of the PLL. Direct modulation of the PLL output signal may be performed numerically. By further providing an auxiliary modulation path and performing calibration between the direct modulation path and the auxiliary modulation path, modulation characteristics may be separated from loop bandwidth constraints.

Abstract: It is an object of the present invention to reduce the amount of spurious noise generated by an emission line spectrum of a signal propagating around the PLL of a PLL frequency synthesizer carrying out digital-signal processing.In order to achieve the object described above, the present invention provides a PLL frequency synthesizer with the following configuration.In a PLL frequency synthesizer having a charge-pump circuit, a waveform converter is provided at a stage behind the charge-pump circuit. The waveform converter converts the voltage waveform on a time axis of a rectangular wave output by the charge-pump circuit into a waveform which: is symmetrical with respect to a predetermined point of time; oscillates so as to have no direct-current component; and has a maximum value of the absolute values of maximums of wave heights thereof located at the center wherein the absolute value decreases uniformly as the wave height is separated farther away from the center.

Abstract: An extended frequency lock range is achieved in a PLL circuit based on sampled phase detectors by modifying a conventional PLL circuit to utilize a biased phase detector to achieve frequency acquisition of the oscillator output signal, without the need for a lock detector. A biased phase detector applies more phase error correction in one direction than in the other direction. For example, a positive biased phase detector applies more positive current, I.sub.UP, over time than negative current, I.sub.DOWN. For a positive biased phase detector, the VCO control voltage is initialized to a value below the lock-in voltage, and the positive biased phase detector will cause a steady increase in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero.

Abstract: An apparatus comprising a phase-locked loop, a select circuit and a control circuit. The phase-locked loop may be configured to generate a feedback signal (along with a buffered output signal) in response to a reference clock and a control signal. A select circuit may be configured to present a reference clock signal in response to a plurality of input clock signals and a select signal. The slew control circuit may be configured to generate the control signal in response to the select signal, and the feedback signal. The control circuit may be used to reduce noise presented to the phase-locked loop and may allow for a rapid initial frequency acquisition of the PLL to the reference frequency.

Abstract: A PLL circuit of which pull-in time is reduced. The PLL circuit comprises a voltage controlled oscillator; a frequency divider which divides the frequency of the output signal from the voltage controlled oscillator; a phase detector which compares the phase of a standard signal and the frequency-divided signal and outputs an advanced phase signal and a delayed phase signal; a charge pump which charges and discharges a capacitor in a low pass filter, depending upon the advanced/delayed phase signals; a voltage supplier which supplies the control terminal of the voltage controlled oscillator with a voltage which corresponds to the desired voltage decided by the different output frequencies of the voltage controlled oscillator, when the output of the low pass filter is not virtually connected with the control terminal of the voltage controlled oscillator.

Abstract: An output clock signal is generated from a selected input clock signal using a phase-locked loop (PLL). The output clock signal is used to detect failures in the selected input clock signal. If a failure is detected, a backup input clock signal is used to generate the output clock signal. In one embodiment, a clock detector has a counter that is initialized based on the selected input clock signal and incremented based on the output clock signal. The clock detector detects a failure in the selected input clock signal if (1) the counter is reset too early or too late, as determined by the counter value, or (2) the signal level in the selected input clock signal does not change within a specified time period.

Abstract: A phase-locked loop circuit for locking the phase of an oscillator to the phase of a reference signal includes a multi-cycle phase detector (11) for detecting a phase difference between an input signal and said reference signal through multiple clock cycles and for sending a corresponding phase adjustment signal, and, a multiple current source charge pump (12) connecting to said phase detector for receiving said phase adjustment signal and sending a current signal depending upon said phase adjustment signal.

Abstract: A circuit comprising an oscillator, a multiplexer, a half rate clock circuit and a full rate clock circuit. The oscillator may be configured to generate a first clock signal and a second clock signal in response to a control signal. The multiplexer may be configured to generate the control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal. The half rate clock circuit may be configured to generate the half rate clock signal in response to the first and second clock signals. The full rate clock circuit may be configured to generate the full rate clock in response to (i) one of the first and second clock signals and (ii) a reference clock.

Abstract: A phase locked loop unlock detector is provided for a data detection channel in a direct access storage device (DASD). The phase locked loop unlock detector includes a counter for generating a threshold reference relative to a reference signal. An unlock window generator is coupled to the counter for generating an unlock window signal. An unlock error detector is coupled to the unlock window generator for comparing a variable frequency signal with the unlock window signal.

Abstract: A digitally controlled tuner circuit for continuous-time filters. Active RC integrators include digitally programmable feedback capacitors to allow for digital fine tuning of their time constant. The PLL-based tuner circuit includes a sine-wave oscillator made up of the digitally-controlled active RC integrators.

Abstract: A FPLL has an I, a Q and a third multiplier, with the I multiplier supplying demodulated signals to a limiter and the Q multiplier supplying signals to a loop filter. A VCO and phase shift circuit supply quadrature signals to the I and Q multipliers. The analog input signal is applied to the I multiplier and to the third multiplier. The third multiplier, which is located in an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents, is also supplied with the digital output of the limiter. The third multiplier supplies its output to the Q multiplier.

Abstract: A sequence generator 10 for a frequency synthesiser 1,2,3,4,5,10 forming part of a direct modulator comprises an input 10a for receiving an input multibit signal X(z), an output 10c for outputting an output digital signal Y(z) and sequence generation means 10b. The sequence generation means is adapted to produce a noise transfer function which has a minimum value both at the frequency corresponding to the dc component of the input signal and at one or more frequencies away from the frequency corresponding to the dc component of the input signal.

Abstract: A phase locked loop circuit includes a reset signal generating circuit for generating a reference clock signal and a reset signal from an input clock signal. A phase locked loop section generates an output clock signal based on the reference clock signal such that a phase of the output clock signal is locked in that of the reference clock signal. Also, the phase locked loop section is reset in response to the reset signal such that the phase of the output clock signal is locked in an initial value.

Abstract: The invention relates to a frequency divider of the type comprising a prescaler followed by a programmable counter, and serving to divide by an overall division ratio D that can be written D=k.N+A. The prescaler operates with a pair of division ratios k/k+1, and includes means for changing from the higher division ratio k+1 to the lower division ratio k as a function of a modulus control signal. N is a first predetermined programmable value corresponding to the division ratio of the programmable counter. A is a second predetermined programmable value such that on being reached by the programmable counter, the prescaler receives the modulus control signal. The following is true: 0.ltoreq.A<N. According to the invention, the prescaler has at least two successive pairs of division ratios p/p+1,p+1/p+2, p+2/p+3, etc., and includes selection means for dynamically selecting one of the pairs as a function of a selection signal, the selected pair constituting the operating pair k/k+1.

Abstract: A phase interpolated frequency synthesizer with on chip tuning includes a voltage controlled oscillator, a fractional-N divider, phase compensation and on chip tuning circuits, a phase detector, and a loop filter. The phase compensation and on chip tuning circuits compensate for the phase lag from the fractional-N divider. The phase compensation circuit can include a series of voltage controlled delay elements with the tuning circuit providing a control voltage.

Abstract: A control system for a tuning fork gyroscope uses motor frequency to control motor amplitude. The tuning fork gyroscope has a drive signal input and an output signal from which motor frequency is determined. A phase/frequency detector generates an error signal by comparing the actual oscillation phase of the output signal with the phase of a reference signal from a crystal controlled frequency synthesizer. The error signal is filtered in a feedback loop control to reduce phase detector ripple. The output of the loop controller is then used to determine the appropriate drive signal to drive the error signal to a constant and maintain a predetermined oscillation frequency.

Abstract: A PLL response time is accelerated with a frequency detector counter. The PLL utilizes both a phase frequency detector and the frequency detector counter. Initially, the operation of the PLL is controlled by the frequency detector counter and the output of phase frequency detector does not affect the PLL system. During this period, the PLL synchronizes to an input clock frequency. After the PLL reaches a predetermined frequency range, the frequency detector counter stops working. Thereafter, the phase frequency detector controls the operation of the PLL. During this period, the PLL synchronizes to both the frequency and the phase of the input signal.

Abstract: A phase-locked loop fabricated on an integrated circuit includes a phase/frequency detector, a charge pump, a filter node and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second frequency control inputs and a VCO output, wherein the first frequency control input is coupled to the filter node and the VCO output is coupled to the phase/frequency detector. The VCO has a first voltage-to-frequency gain from the first frequency control input to the VCO output and a second voltage-to-frequency gain from the second frequency control input to the VCO output. An off-chip filter input is coupled to the filter node for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first frequency control input and the second frequency control input and has a variable time constant. A time constant control circuit is coupled to the on-chip loop filter for controlling the variable time constant.

Abstract: This invention provides a simple yet robust solution to the phase-locked loop frequency acquisition problem in clock and data recovery circuits by using a frequency detector with a deadband, which is constructed in part with an oversampling rotational frequency detector.

Abstract: An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another.

Abstract: A radio-frequency signal generator has a voltage-controlled oscillator for producing a radio-frequency signal. A frequency divider with a fixed division ratio has an input connected to the voltage-controlled oscillator and an output supplying a first clock signal. A first accumulator aggregates a first reference signal under the control of the first clock signal. A second accumulator aggregates a second reference signal under the control of a second clock signal. The aggregated signals are subtracted from one another, filtered through a digital filter, weighted and subsequently converted into an analog signal. The analog signal is filtered by an analog filter and fed to the voltage-controlled oscillator.