Abstract: A system for wireless communications includes an antenna and a controller, the antenna configured to transmit electrical data signals, the electrical data signals including an encoded message signal. The encoded message signal including one or more encoded message words. The controller is configured to encode one or more message words, of a message signal, into one or more encoded message words of the encoded message signal, based on a coding format. The coding format correlates each of a plurality of correlated ratios with one of a plurality of format words. Each of the plurality of correlated ratios is a ratio of a duty cycle of a pulse to a respective period associated with one or both of the duty cycle and the pulse. Each of the one or more encoded message words are encoded as one of the plurality of correlated ratios.

Abstract: Time-to-digital converter (TDC) using multiple Vernier in a cascaded architecture reduces the timing jitter by decreasing the number of the ring oscillator cycles during the measurement processes. Time-to-digital converter (TDC) measurements using a third oscillator for the second Vernier process has significant advantages compared to changing the period of the second oscillator during the measurement cycle. The Vernier architecture described herein may operate with faster oscillators, reducing the number of intervals before converging and leading to a lower time conversion and a better timing jitter Adding multiple cascaded Vernier interpolation may further improve the TDC measurement resolution while having only a small increment of time required to resolve the time interval calculations.

Abstract: A Time to Digital Converter (TDC) arrangement includes a first delay circuit configured to receive a signal with N phases; a set of phase detectors configured to compare each phase of the signal with a reference signal; a logic circuit configured to receive output signals from the set of phase detectors and detect which phase signal that is the closest signal leading or lagging the reference signal; a first multiplexer configured to receive outputs from the first delay circuit and the logic circuit; a second delay circuit configured to delay the reference signal; a TDC configured to receive output signals from the first multiplexer and the second delay circuit; an adder configured to sum outputs from the logic circuit and the TDC and generate an output signal of the TDC arrangement.

Abstract: Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.

Abstract: A system for wireless communications includes an antenna and a controller, the antenna configured to transmit electrical data signals, the electrical data signals including an encoded message signal. The encoded message signal including one or more encoded message words. The controller is configured to encode one or more message words, of a message signal, into one or more encoded message words of the encoded message signal, based on a coding format. The coding format correlates each of a plurality of correlated ratios with one of a plurality of format words. Each of the plurality of correlated ratios is a ratio of a duty cycle of a pulse to a respective period associated with one or both of the duty cycle and the pulse. Each of the one or more encoded message words are encoded as one of the plurality of correlated ratios.

Abstract: A system for wireless communications includes an antenna and a controller, the antenna configured to transmit electrical data signals, the electrical data signals including an encoded message signal. The encoded message signal including one or more encoded message words. The controller is configured to encode one or more message words, of a message signal, into one or more encoded message words of the encoded message signal, based on a coding format. The coding format correlates each of a plurality of correlated ratios with one of a plurality of format words. Each of the plurality of correlated ratios is a ratio of a duty cycle of a pulse to a respective period associated with one or both of the duty cycle and the pulse. Each of the one or more encoded message words are encoded as one of the plurality of correlated ratios.

Abstract: A method for determining the position of a rotor in an electronically commuted motor. The method comprises the steps of calculating the rotation angle using three Hall-sensors; identifying and correcting phase errors; and determining and correcting cyclic errors.

Abstract: Variable window filtered power system signals for electric power system monitoring and protection operations of an electric power system are provided herein. Upon detection of a power system disturbance, the filter window is decreased after a predetermined resize delay such that pre-disturbance samples are not included in the new window. As additional samples are obtained, the filter window grows to include new samples until the window reaches an initial filter window length. Gain and group delay correction factors accounting for window size and signal frequency are approximated.

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

Abstract: A wireless receiver system, for a wireless power transfer system, includes an antenna and a controller, the antenna configured to transmit electrical data signals, the electrical data signals including an encoded message signal. The encoded message signal including one or more encoded message words. The controller is configured to encode one or more message words, of a message signal, into one or more encoded message words of the encoded message signal, based on a coding format. The coding format correlates each of a plurality of correlated ratios with one of a plurality of format words. Each of the plurality of correlated ratios is a ratio of a duty cycle of a pulse to a respective period associated with one or both of the duty cycle and the pulse. Each of the one or more encoded message words are encoded as one of the plurality of correlated ratios.

Abstract: In a dual electrode Si optical modulator having a CPW electrode structure according to a related art, a phase difference of return currents propagating through two ground electrodes degrades the modulation frequency characteristic. To prevent this degradation, the modulator length has been shortened to terminate signal propagation before occurrence of a phase difference. However, a short modulator length would reduce an electric field applied to the optical waveguide, thus lowering the modulation efficiency. An optical modulator according to the present invention includes a bridge wiring that connects two ground electrodes, disposed between an RF electrode and an optical waveguide inside a substrate. The bridge wiring equalizes the potential between the two ground electrodes of the CPW, thereby eliminating a phase difference of return currents induced by a radio-frequency electrical signal to the RF electrode and propagating through the two ground electrodes.

Abstract: A modulator comprises one or more resonators. Each resonator has a light confining closed loop structure, such as a ring structure, and two, three or more electrodes associated with the light-confining structure, and may be a micro-resonator. An optical signal is modulated by a digital signal using the resonator. The procedure comprises obtaining the digital signal, mapping the signal using a mapping function to produce a transformed digital signal, the transformed digital signal being selected to produce, say linear, output from the resonator, inputting the transformed digital signal via electrodes onto the resonator; and modulating the optical signal via coupling from the resonator. Suitable mapping produces 16 QAM and other modulation schemes.

Abstract: Techniques for synchronizing a display transmitter and display panel are described. An example display panel includes a timing controller to receive display data from a transmitter and render the display data on a display screen of the display panel. The display panel is in a first clock domain and the transmitter is in a second clock domain which is derived separately from the first clock domain. The display panel also includes a time code generator to generate a first display time code and a frequency adjuster to receive a second display time code from the transmitter. The frequency adjuster adjusts the clock frequency of the display panel based on the first display time code and the second display time code.

Abstract: Many mobile devices and mobile networks utilize orthogonal frequency division multiplexing (OFDM) to calculate position information of mobile devices within the network. However, the Doppler Effect and other noise or obstructions can cause OFDM signals to become entangled, particularly when the mobile device is moving, making the calculated position information inaccurate. Described herein are systems and methods for disentangling the OFDM signals by calculating a symbol length for the signals that is longer than the minimum symbol length, which is used in traditional OFDM. Selecting a longer symbol length reduces the Doppler Effect and other noise on the signals, making positioning calculations more accurate.

Abstract: Systems and methods are provided for determining an angular position of a control shaft. The systems and methods receive at least three electrical signals from a synchro transducer coupled to a control shaft. The systems and methods further calculate two values associated with at two of the at least three electrical signals, determine an estimate of the angular position of the control shaft based on the at least two values, and generate an output signal indicative of the angular position of the control shaft based on the estimate.

Abstract: Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.

Abstract: A system and a method for determining a failure within a resolver are provided. The method includes detecting signals output from the resolver. In addition, an average value and a deviation value of the detected signals are calculated. Further, the controller is configured to determine a disconnection or a short circuit of the resolver using the calculated average value and deviation value.

Abstract: A phase modulation device including a diode-type phase modulator having a pair of side terminals connected to two sides of an optical waveguide core along an optical axis of the optical waveguide core, and a control unit that controls electrical signals to be input to the phase modulator, the side terminal of the phase modulator being divided into a plurality of portions along the optical axis of the optical waveguide core, the phase modulator having electrodes 15 respectively provided on the divided side terminals and electrically separated from each other, the control unit having switches and constant-current sources connected to the electrodes of the side terminals and controls stepwise the amount of change in phase of propagating light in the optical waveguide core according to the number of the switches turned on.

Abstract: According to an example, a method for storage device reading may include receiving an input signal indicative of a period of oscillation of a ring oscillator coupled to a storage device of a plurality of storage devices, and measuring the period of oscillation of the ring oscillator by a time-to-digital circuit. The method for storage device reading may further include determining a value of data stored in the storage device based on the measurement.

Abstract: A device includes a timing test circuit. The timing test circuit receives a timing signal related to the display of an image on a display. The timing test circuit also determines if the timing signals are invalid. Moreover, the timing test circuit transmits a fault indication when the timing signals are determined to be invalid.

Abstract: Presented herein is a magnetic field sensor architecture that uses outputs of a peak detector and threshold detector operating in parallel to detect magnetic anomalies that may be associated with the target being sensed, e.g., a rotational ferromagnetic object such as a toothed gear, and use such detection to prevent sensor malfunction. The sensor includes an edge detection circuit and an error detection circuit. In one embodiment, the edge detection circuit includes circuits to detect edges (or transitions) of the threshold and peak detector output signals and the error detection circuit includes circuits, responsive to the edge detection circuit, to indicate an error when a “missed transition” occurs or a peak-to-peak value of an input signal as detected by the peak detector for a current cycle differs from an expected peak-to-peak value by a predetermined amount.

Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

Abstract: A system (1) is described for determining offsets (?) of measuring instruments, in particular of measures with a null or constant mean value, composed of first processing means (3) adapted to compute, from at least one value of a measuring signal (S) deriving from an instantaneous measure performed by at least one measuring instrument or a sensor, at least one offset value (?) of such signal (S); and second processing means (5) adapted to subtract such offset value (?) from the value of the instantaneous measure signal (S) to obtain a corrected measure value (S??) of such signal S. A process is also described for determining offsets (?) of measuring instruments, in particular of measures with a null or constant mean value.

Abstract: One embodiment of the present invention features a poly-phase local oscillator generator combining frequency dividers and direct-injection-locked phase correctors. The poly-phase local oscillator generator comprises a plurality of phase correctors configured to relax frequency and tuning range of a reference local oscillator (LO), and a plurality of frequency dividers, coupled to the phase correctors, configured to offer different frequency segments. The phase correctors are expandable, so that phase accuracy can be optimized by cascading more of themselves.

Abstract: A time-to-digital converter includes first and second phase distribution circuits and N time-to-digital conversion circuits. The first and second phase distribution circuits each includes a plurality of frequency dividers connected in a tree structure. The first and second phase distribution circuits each divides a signal received by the frequency dividers of root nodes into N signals. The first and second phase distribution circuits each outputs the N signals each having a different phase. The N time-to-digital conversion circuits each converts a phase difference between an i-th signal (where i is an integer from 0 to N?1) that is output from the first phase distribution circuit and another i-th signal that is output from the second phase distribution circuit into a digital value.

Abstract: The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (Cn-1, . . . , C0) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((Cn-1, . . . , C0)) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values.

Abstract: An oversampling time-to-digital converter includes an input pulse generation circuit generating two pulse signals, a reference pulse generation circuit generating two pulse signals, a swap circuit swapping two pulse signals, a multiplexer selecting an output of the input pulse generation circuit or the swap circuit, a time-to-current conversion circuit outputting two pulse currents in accordance with an output of the multiplexer, a current mirror circuit whose input and output terminals receive the two pulse currents, an integration circuit integrating a differential current between the pulse current connected to the output terminal of the current mirror circuit and an output current of the current mirror circuit, and a comparison circuit comparing an output signal of the integration circuit to a threshold voltage. An output signal of the comparison circuit is given to the swap circuit as a control signal.

Abstract: The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

Abstract: Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.

Abstract: One embodiment includes a phase-based analog-to-digital converter (ADC) system. The system includes a voltage-to-phase converter configured to convert an input voltage to a phase difference corresponding to a phase-delay with respect to an input clock signal that is based on a magnitude of the input voltage. The system also includes a phase-to-digital converter configured to convert the phase difference into a digital output signal having a digital value corresponding to a magnitude of the phase difference.

Abstract: According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.

Abstract: A phase digitizing system includes an analog-to-digital converter (ADC), multiple phase accumulators and a processing device. The ADC generates sample segments of digital signal waveform samples based on an analog composite input signal received in a measurement channel, the composite input signal includes a first signal having a first frequency F1 and a second signal imported from a reference channel having a second frequency F2. The processing device is coupled to the phase accumulators, and digitally processes each sample segment with outputs of the phase accumulators, and continually generates digital phase data The processing device further provides increment values to each of the phase accumulators based on the digital phase data, causing an output of a first phase accumulator to represent an instantaneous phase of the first signal, and an output of a second phase accumulator to represent an instantaneous phase of the second signal.

Abstract: A phase digitizing system includes an analog-to-digital converter (ADC), multiple phase accumulators and a processing device. The ADC generates sample segments of digital signal waveform samples based on an analog composite input signal received in a measurement channel, the composite input signal includes a first signal having a first frequency F1 and a second signal imported from a reference channel having a second frequency F2. The processing device is coupled to the phase accumulators, and digitally processes each sample segment with outputs of the phase accumulators, and continually generates digital phase data The processing device further provides increment values to each of the phase accumulators based on the digital phase data, causing an output of a first phase accumulator to represent an instantaneous phase of the first signal, and an output of a second phase accumulator to represent an instantaneous phase of the second signal.

Abstract: The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.

Abstract: A system and methods are provided for converting a first temporally short and spectrally broad optical pulse into a train of spectrally narrow and distinct optical pulses. This involves receiving, on a first I/O channel, the first optical pulse associated with a plurality of wavelengths and performing wavelength division demultiplexing on the first optical pulse at an optical unit housed on an optical chip to output a plurality of second optical pulses on different ones of a plurality of second I/O channels, each of the second optical pulses associated with a unique wavelength range from the first optical pulse. This also involves receiving the second optical pulses at loop mirrors in the second I/O channels, wherein the second I/O channels are patterned as waveguides in the optical chip and reflecting, at the loop mirrors, the second optical pulses back to the optical unit.

Abstract: A phase to digital conversion circuit with improved resolution for a rotary traveling wave oscillator. The phase to digital conversion circuit connects with a closed loop transmission line via a plurality of signal lines or nodes distributed along the transmission line. As an oscillating signal propagates around the transmission line, a time waveform of the signal at each of the plurality of signal lines is transmitted to a corresponding plurality of latches. Upon a triggering condition, the plurality of latches simultaneously samples the signals from the plurality of signal lines. At least two reference clock signals are switchably coupled with the plurality of latches latch for triggering the plurality of latches based on an edge transition in each of the reference clock signals compared with an edge transition in each of the signals from the plurality of taps.

Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

Abstract: An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.

Abstract: A digital-to-synchro converter (“DSC”) is a device that converts digital signals to analog signals suitable for use by a synchro device. A conventional DSC implements complex circuitry to take digital input and generate [V Sin({acute over (?)}t) Sin(?)] and [V Sin({acute over (?)}t) Cos(?)] analog signals, and a Scott-T transformer to transform these analog signals into [V Sin({acute over (?)}t) Sin(?)], [V Sin({acute over (?)}t) Sin(?+120)], and [V Sin({acute over (?)}t) Sin(?+240)] analog signals. An inventive DSC, as typically embodied, implements a microcontroller to take digital input and generate [V Sin({acute over (?)}t) Sin(?)] and [V Sin({acute over (?)}t) Sin(?+120)] digital signals, a digital-to-analog converter to convert these digital signals to [V Sin({acute over (?)}t) Sin(?)] and [V Sin({acute over (?)}t) Sin(?+120)] analog signals, and a regular transformer (i.e.

Abstract: An linear encoder includes: a scale; a light-emitting element that emits light onto the scale; a detecting head that has a light-receiving element that receives the light emitted by the light-emitting element to be reflected or transmitted by the scale; and a connector connected to the detecting head via a cable. The connector comprises a display that displays a status of the light received by the light-receiving element and a connector controller that controls the display. The connector controller includes a display controller that controls the display in accordance with the intensity of the light received by the light-receiving element.

Abstract: First and second A/D converters perform analog/digital conversion of first and second signals of a Hall signal so as to generate third and fourth signals as digital signals. A differential conversion circuit generates a fifth signal as a single-ended signal that corresponds to the difference between the third and fourth signals. An offset correction circuit corrects offset of the fifth signal so as to generate a sixth signal. An amplitude control circuit stabilizes the amplitude of the sixth signal to a predetermined target value, and generates its absolute value, thus generating a seventh signal. A control signal generating unit generates a control signal based upon the seventh signal. A driver circuit drives a motor according to the control signal.

Abstract: According to one embodiment, a multiphase circuit, a flip-flop, and a decoder are provided. The multiphase circuit generates multiphase signals of which phases are different from each other by 180/M degrees by dividing a differential oscillation signal by M (M is an integral number not smaller than 2). The flip-flop captures the multiphase signal in synchronization with an input of a reference signal. The decoder decodes an output signal of the flip-flop.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

Abstract: Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit with a delay circuit input and a plurality of taps outputs. A sampling register samples data from the data inputs. The feed circuit provides for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input. A control circuit switches the feed circuit between normal operating mode and calibration mode, and controls the feed circuit successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode. The control circuit reads out resulting data from the sampling register for each selection and determines calibration data for the oscillator signal from said data.

Abstract: Provided are a TDC having a pipeline or cyclic structure and an operating method thereof. The TDC includes a first stage block and a second stage block. The first stage block detects a first bit of a digital code for a time difference between first and second input signals. The second stage block detects a second bit of the digital code for a time difference between first and second output signals of the first stage block. The first stage block amplifies a time difference between first and second delay signals for the first and second input signals to generate the first and second output signals, and transfers the first and second output signals to the second stage block.

Abstract: A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.

Abstract: A circuit arrangement is described comprising a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signal, a second signal generator configured to generate a second pulse signal, wherein a delay between a rising edge of the first pulse signal and a rising edge of the second pulse signal is proportional to a difference between the first input signal and the second input signal, a first converter configured to convert the first pulse signal to a first digital number proportional to a width of the first pulse signal, a second converter configured to convert the second pulse signal to a second digital number proportional to a width of the second pulse signal, wherein at least one of the first converter and the second converter comprises a cascade of at least two converter stages, wherein each converter stage of the at least two converter stages is configured to propagate and shrink

Abstract: A phase digitizing apparatus for generating a corresponding digital value in response to a phase of an input signal is provided. The phase digitizing apparatus includes a coarse phase generator, for generating a coarse phase code according to the phase of the input signal and a first time unit; a fine phase code generator, for generating a fine phase code according to the phase of the input signal and a second time unit; and a calculating unit, for generating the digital value according to the coarse phase code and the fine phase code; wherein the first time unit is greater than the second time unit.

Abstract: A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.

Abstract: A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).