Abstract: A method of weight calibration in a DAC (25) is disclosed. The DAC (25) comprises an input port (100) for receiving a sequence of digital input words (x[n]), each representing a digital input sample, and a digital control circuit (110) configured to encode each digital input word (x[n]) into a control word (z[n]) representing the same digital input sample. Each bit (Zi) in the control word (z[n]) has a corresponding bit weight (wi) and is in the following considered to adopt values in {?1, 1}. Furthermore, the DAC (25) comprises a set (120) of analog weights, each associated with a unique one of the bits (Zi) in the control word (z[n]), and summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word (Zi) weighted by the respective associated analog weights. The DAC (25) also has an output (140) for outputting the analog sample.

Abstract: An apparatus, such as a radar system that conducts beamforming operations, includes a plurality of analog-to-digital-converters (ADCs) and an error correction system coupled to the ADCs. Based upon an assessment of a plurality of errors associated with the ADCs by the error correction system, the error correction system programs sampling operations for the ADCs. The error correction system includes an error correction unit that identifies the plurality of errors associated with a plurality of sub-ADCs of the ADCs, a selection unit coupled to the error correction unit that sorts the errors associated with the plurality of sub-ADCs, and a programming unit coupled to the selection unit that reconfigures the sorted errors to generate a sequence of sampling operations for the plurality of sub-ADCs.

Abstract: A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.

Abstract: Aspects relate to analog-to-digital conversion of an analog signal. The resolution (number of bits) and/or the quantization levels of the analog-to-digital conversion may be configurable. A device may configure its analog-to-digital conversion parameters. For example, a first device may reduce the number of bits for its analog-to-digital converter to reduce power consumption. In this case, the first device may transmit an indication of selected analog-to-digital conversion parameters to a second device that will transmit to the first device. In this way, the second device may take appropriate action, if needed. A device may request another device to use certain analog-to-digital conversion parameters. For example, a first device may determine that a second device should use a larger number of bits for its analog-to-digital conversion process to improve the quality of the communication between the first and second devices.

Abstract: The present disclosure enables firmware-based interleaved-ADC gain calibration and provides hardware-thresholding enhancements. An on-chip memory may store subADC samples and a microprocessor accesses these stored samples for use with the calibration algorithm. Power estimates may be performed using square of each subADC sample to estimate gain error. Thresholding may be applied to the subADC samples, such as Maximum Amplitude Thresholding, Minimum Power Thresholding, and/or using Histogram Output Memory, to determine that samples are valid and may be used for calibration or that subADC data are to be discarded and a new subADC data capture is to be started.

Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.

Abstract: An AD converter with self-calibration function that does not require an instrument for calibration, and includes: a reference voltage unit that generates a reference voltage; a summation and conversion unit that has two or more unit voltages serving as units of amount of change in a summed voltage, and during conversion, sums up any one unit voltage of the two or more unit voltages until the summed voltage exceeds the reference voltage, with an input voltage being an initial value of the summed voltage; and a control unit including a calibration control section that calibrates the two or more unit voltages and an offset voltage of a comparator at a time of calibration, and a conversion control section that determines a polarity of the offset voltage of the comparator and thereafter converts the input voltage to a digital value during conversion.

Abstract: A composite analog-to-digital converter (ADC) has a low resolution ADC configured to receive and digitize analog data, the low resolution ADC having a low resolution and a high operating speed, one or more high resolution ADCs configured to receive and digitize the analog data, the one or more high resolution ADCs having a resolution higher than the low resolution ADC, and an operating speed lower than the high operating speed of the low resolution ADC, a sample clock generator to provide a sample clock signal to the low resolution ADC and to a clock divider, a mixer to receive the analog data and connected to the one or more high resolution ADCs, a local oscillator connected to the mixer to allow the one or more high resolution ADCs to be tuned to sample a portion of a spectrum of the first ADC. A test and measurement instrument contains a composite ADC.

Abstract: A drive-sense circuit coupled to a variable current load. The drive-sense circuit includes an impedance reference circuit operable to generate an impedance reference signal. The drive-sense circuit further includes a regulated voltage source circuit operable to generate a regulated voltage signal based on an analog regulation signal, where the regulated voltage signal is provided on a line to the variable current load to keep a load impedance on the line substantially matching the impedance reference signal, and where a current of the variable current load affects the regulated voltage signal. The drive-sense circuit further includes a voltage loop correction circuit operable to generate a comparison signal based on the impedance reference signal and the load impedance, where the comparison signal represents the current, and where the analog regulation signal is representative of the comparison signal.

Abstract: Techniques for facilitating analog-to-digital converter calibrations are provided. In one example, a method includes, for each of a plurality of time instances, generating a first ramp signal started at the time instance relative to a respective start of a first counter signal and generating a respective comparator output signal based on the first ramp signal and a first threshold signal. The method further includes capturing a respective first value of the first ramp signal in response to a transition of the respective comparator output signal. The method further includes determining a respective second counter value of a second counter signal based on the respective first value. The method further includes determining a scaling factor based on the second counter values and the time instances. Each of the first values is associated with the same counter value of the first counter signal. Related devices and systems are also provided.

Abstract: An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

Abstract: A background offset calibration system for an analog signal comparator provides low offset without compromising tracking bandwidth. The comparator includes a preamplifier and a decision latch. A switching selectively couples outputs of an analog circuit to the inputs of the preamplifier stage. A state control logic alternatively operates the system in a first phase in which the analog circuit acquires an input signal while the comparator is calibrated, and a second phase in which a comparison is performed by the comparator. In the first phase, the switching circuit disconnects the outputs of the analog circuit from the preamplifier stage and applies a common mode reference to the inputs of the preamplifier. An offset correction circuit determines correction changes from a history of states of the decision latch across multiple sampling cycles. The offset correction circuit adjusts a threshold voltage of the decision latch by applying the correction changes.

Abstract: A controller for an environmental sensor provides digital environmental measurement values from analog environmental measurements performed by analog circuitry, the digital environmental measurement values lying in a global scale range. The controller subjects the global scale range to a subdivision into scale subranges that are proper subranges of the global scale range. The controller selects, among the scale subranges, one scale subrange in which an analog environmental measurement is to be performed, selects an offset information and a gain information that are associated with the selected scale subrange and that are indicative of an offset and a gain to be applied by the analog circuitry to perform an analog environmental measurement in the selected scale subrange, and to provide the offset information and the gain information to the analog circuitry.

Abstract: A neuromorphic computing device includes first and second memory cell arrays, and an analog-to-digital converting circuit. The first memory cell array includes a plurality of resistive memory cells, generates a plurality of read currents based on a plurality of input signals and a plurality of data, and outputs the plurality of read currents through a plurality of bitlines or source lines. The second memory cell array includes a plurality of reference resistive memory cells and an offset resistor, and outputs a reference current through a reference bitline or a reference source line. The analog-to-digital converting circuit converts the plurality of read currents into a plurality of digital signals based on the reference current. The offset resistor is connected between the reference bitline and the reference source line.

Abstract: Receiver circuitry for an input/output device includes first stage circuitry and second stage. The first stage circuitry has a first input to receive an input signal, voltage adjustment circuitry, and differential amplifier circuitry. The first stage circuitry is coupled to the first input and has a transistor pair to receive the input signal, and adjust a voltage value of the input signal to generate an adjusted signal. The differential amplifier circuitry receives the adjusted signal and a reference signal, and generates a first differential signal and a second differential signal. The second stage circuitry receives the first differential signal and the second differential signal, and generates an output signal based on the first differential signal and the second differential signal.

Abstract: An error calibration apparatus and method are provided. The method is adapted for calibrating a machine learning (ML) accelerator. The ML accelerator achieves computation by using an analog circuit. An error between an output value of one or more computing layers of a neural network and a corresponding corrected value is determined. The computation of the computing layers is achieved by the analog circuit. A calibration node is generated according to the error. The calibration node is located at the next layer of the computing layers. The calibration node is used to minimize the error. The calibration node is achieved by a digital circuit. Accordingly, error and distortion of the analog circuit could be reduced.

Abstract: An electronic device may include wireless circuitry. The wireless circuitry may include a quadratic phase generator for outputting a perfectly interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator may include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator may receive as inputs a chirp count and a word length. The switch may be configured to switchably feed one of two input values that are a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator may output full-bandwidth chirps or reduced-bandwidth chirps. Bandwidth reduction can be achieved by scaling the two input values of the switches.

Abstract: A multiplexer (MUX) calibration system includes main MUX circuitry, first replica MUX circuitry, digital-to-analog (DAC) circuitry, detection circuitry, and control circuitry. The main MUX circuitry receives clock signals and outputs a first data signal based on the clock signals. The first replica MUX circuitry receives the clock signals and outputs a second data signal based on the clock signals. The DAC circuitry generates an offset voltage. The detection circuitry receives the second data signal and the offset voltage and generates a first error signal based on one or more of the second data signal and the offset voltage. The control circuitry receives the first error signal and generates a first control signal indicating an adjustment to the clock signals.

Abstract: A spectral leakage-driven loopback method for predicting performance of a mixed-signal circuit. The method includes generating, by an on-chip Digital Signal Processor (DSP) core, a digitally-synthesized single-tone sinusoidal stimulus. A nonlinear digital-to-analog-converter (DAC) channel is sampled. A DAC output signal is supplied to a nonlinear analog-to-digital converter (ADC) channel through an analog loopback path. Each of the DAC channel and the ADC channel are measured for a production testing. The on-chip DSP core performs postprocessing and predicting harmonics of the two individual DAC and ADC channels.

Abstract: Apparatus includes an ADC configured to convert an analog signal to a digital signal, a comparator having a first input responsive to the analog signal, a second input responsive to the digital signal, and an output at which a comparison signal is provided, and an output checker configured to process the comparison signal to generate a fault signal indicative of whether a fault has occurred in the ADC. The comparator can be an analog comparator in which case the digital signal is converted to an analog signal for the comparison or a digital comparator in which case an additional ADC is provided to convert the analog signal into a digital signal for the comparison. Embodiments include more than one ADC in which case summation elements are provided to sum the analog signals and the digital signals for the comparison.

Abstract: A gamma voltage generator within a display device includes a plurality of gamma generation circuits that respectively generate a plurality of gamma voltages. At least one gamma generation circuit includes an input circuit configured to receive a first reference voltage and a second reference voltage, a reference voltage select circuit configured to select a reference voltage among the first reference voltage and the second reference voltage by comparing a gamma voltage generated by the at least one gamma generation circuit with the first reference voltage and the second reference voltage, a digital-to-analog conversion circuit configured to generate an analog voltage corresponding to a gamma code based on the reference voltage selected by the reference voltage select circuit, and an output circuit configured to output the gamma voltage based on the analog voltage.

Abstract: A method of an electronic device includes: providing a capacitive digital-to-analog converter having a reference voltage input; providing a reference voltage providing circuit to generate a reference voltage to the reference voltage input of the capacitive digital-to-analog converter; and, generating a compensation signal into the reference voltage input of the capacitive digital-to-analog converter in response to at least one switching of at least one capacitor in a switchable capacitor network of the capacitive digital-to-analog converter.

Abstract: A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

Abstract: An analog-to-digital converter is disclosed that converts an input analog potential to a digital conversion value. An analog-to-digital converter according to one or more embodiments may include a comparator that compares the input analog potential with a reference potential; and a conversion circuit that measures comparison operation time from a start to an end of a comparison operation by the comparator and outputs the digital conversion value according to the measured comparison operation time and a comparison result by the comparator.

Abstract: Certain aspects of the present disclosure relate to a method for compressed sensing (CS). The CS is a signal processing concept wherein significantly fewer sensor measurements than that suggested by Shannon/Nyquist sampling theorem can be used to recover signals with arbitrarily fine resolution. In this disclosure, the CS framework is applied for sensor signal processing in order to support low power robust sensors and reliable communication in Body Area Networks (BANs) for healthcare and fitness applications.

Abstract: The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit (201) comprising: a clock signal generator (205) configured to provide an output clock signal (203) having a duty cycle; a duty cycle detector (208) arranged to receive the output clock signal (203) and provide an output flag if the duty cycle of the clock signal (203) is outside a predetermined range; a controller (214) arranged to provide a duty cycle select signal (216) to the clock signal generator (205) to cause the clock signal (203) to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector (208).

Abstract: A serial data receiver is disclosed. In one embodiment, a receiver includes an amplifier circuit configured to receive one or more signals that encode a serial data stream that includes a plurality of data symbols and to perform a comparison of the one or more signals to a threshold value to generate a recovered data symbol. The receiver circuit further includes a threshold circuit configured to generate a delayed version of the one or more signals. The threshold circuit is further configured to generate a delayed data symbol using the delayed version of the one or more signals and adjust the threshold value using the delayed data symbol.

Abstract: A digital closed loop control system. An output signal is detected with the aid of an analog-to-digital converter. A correction value is subtracted from the output signal prior to the analog-to-digital conversion and this correction value is added up again after the analog-to-digital conversion. The correction value in this case may be dynamically adapted. In this way, the analog-to-digital converter may be operated in a narrow conversion range.

Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.

Abstract: The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

Abstract: Techniques facilitating write-only device state inferences. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise: a monitor component; and a state component. The monitor component can compare a property of a feedback signal output by a write-only device with a reference signal. The state component can determine a state of the write-only device based on a comparison between the property and the reference signal.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless device may obtain, in a frequency range, device-specific data for use in determining at least one of a frequency or a power of a spurious signal. The wireless device may generate, based at least in part on the device-specific data, information that indicates the at least one of the frequency or the power of the spurious signal. Numerous other aspects are described.

Abstract: An energy-efficient implementation of a WiFi transceiver is proposed in this disclosure. The WiFi transceiver comprises a receive chain comprising a variable receive (Rx) filter circuit and a variable Rx analog-to-digital converter (ADC) circuit. The receive chain is configured to receive a receive signal during a receive mode of operation, having a receive bandwidth associated therewith and receive a transmit signal associated with a transmit chain of the transceiver during a transmit mode of operation, having a transmit bandwidth associated therewith. The WiFi transceiver further comprises a control circuit configured to dynamically adapt a bandwidth of the variable Rx filter and the variable Rx ADC in the receive chain to the receive bandwidth or to the transmit bandwidth, based on the mode of operation.

Abstract: A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.

Abstract: In a method of operating an analog-to-digital converter, a gain error and an offset error that are associated with a digital code generated from the analog-to-digital converter are obtained by performing a first analog-to-digital conversion on a first input analog signal. The gain error and the offset error are stored. A calibration digital code is generated by performing a second analog-to-digital conversion on a second input analog signal based on the gain error and the offset error.

Abstract: A device, which includes an input, configured to read in an analog signal, an analog/digital converter, configured to convert the analog signal into a digital value, and a processor, configured to determine a digital measured value. The processor is further configured to derive a calibrated digital value from the digital value with the aid of a linear calibration function and to derive the digital measured value from the calibrated digital value with the aid of a nonlinear measurement function. The processor modifies the linear calibration function in response to a calibration signal, based on an algorithm, which is based on the nonlinear measurement function, and a number of predefined comparison measured values.

Abstract: A method for trimming analog temperature sensors. First, raise a temperature of a temperature sensor to a highest temperature of a qualification temperature range. Then, trim the temperature sensor such that a high temperature code generated by the temperature sensor represents an actual temperature reported by the temperature sensor at the highest temperature. Next, lower the temperature of the temperature sensor to a lowest temperature of the qualification temperature range. Determine a slope error between the high temperature code and a low temperature code generated by the temperature sensor at the lowest temperature. Finally, determine a correction function that compensates for the slope error of measured temperature codes generated by the temperature sensor for temperatures across the qualification temperature range.

Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.

Abstract: A successive-approximation analog-to-digital converter includes a sampling circuit for sampling an analog input signal to acquire a sampled voltage, and a regenerative comparator for comparing the sampled voltage with a succession of reference voltages to generate, for each reference voltage, a decision bit indicating the comparison result. The converter also includes a digital-to-analog converter which is adapted to generate the succession of reference voltages, in dependence on successive comparison results in the comparator, to progressively approximate the sampled voltage. The regenerative comparator comprises an integration circuit for generating output signals defining the decision bits, and a plurality of regeneration circuits for receiving these output signals. The regeneration circuits are operable, in response to respective control signals, to store respective decision bits defined by successive output signals from the integration circuit.

Abstract: A method includes converting, by n analog to digital converter circuits, n analog signals into n first digital signals having a first data rate frequency; converting, by n digital decimation filtering circuits, the n first digital signals into n second digital signals having a second data rate frequency; and converting, by n digital bandpass filter (BPF) circuits, the n second digital signals into a plurality of outbound digital signals having a third data rate frequency. The coefficients for the taps of a digital BPF circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone component of the analog signal. The first data rate frequency is a first integer multiple of the third data rate frequency. The second data rate frequency is a second integer multiple of the third data rate frequency.

Abstract: An acoustic device is described and includes an acoustic sensor element configured to sense acoustic energy and produce an output signal and a threshold detector circuit including a switch having an input coupled to the output of the acoustic sensor element to receive the output signal, a control port that receives a control signal, and first and second output ports, a first channel including an analog-to-digital converter that operates at a first power level a second analog-to-digital converter that operates at a second higher power level, relative to the first power level and a threshold level detector that receives an output from the first analog-to-digital converter to produce the control signal having a first state that causes the switch feed the output signal from the acoustic sensor element to the second analog-to-digital converter when the first digitized output signal meets a threshold criteria.

Abstract: An illustrative embodiment disclosed herein is a circuit for sensing heating, ventilation, air conditioning, and refrigeration (HVACR) equipment. The circuit includes an input port that has an input voltage signal. The circuit includes an analog-to-digital converter (ADC) generating a first digital signal based on receiving a representation of a supply voltage, generating a second digital signal based on receiving the divided input voltage signal, and outputting the first digital signal, the second digital signal, and an output voltage reference. The circuit includes an amplifier coupled to the ADC and amplifying the output voltage reference to generate a supply voltage. The circuit includes a microprocessor coupled to the ADC and configured to calculate a first ratio of the first digital signal and the supply voltage. The microprocessor is configured to determine the input voltage signal by calculating a second ratio of the second digital signal and the first ratio.

Abstract: A physical quantity detection circuit includes: a detection signal generation circuit generating a detection signal, based on an output signal from a physical quantity detection element; an analog/digital converter circuit converting the detection signal into a first digital signal and converting a test signal into a second digital signal; a test signal generation circuit generating the test signal; and a malfunction diagnosis circuit diagnosing a malfunction of the analog/digital converter circuit, based on the second digital signal. A full-scale voltage of the analog/digital converter circuit is selected from among a plurality of voltages having different magnitudes, according to a power supply voltage. The test signal includes an upper limit value test signal, a lower limit value test signal, and a first intermediate value test signal. The test signal generation circuit performs resistive voltage division of the full-scale voltage and thus generates the first intermediate value test signal.

Abstract: A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

Abstract: Calibration of continuous-time (CT) residue generation systems can account and compensate for mismatches in magnitude and phase that may be caused by fabrication processes, temperature, and voltage variations. In particular, calibration may be performed by providing one or more known test signals as an input to a CT residue generation system, analyzing the output of the system corresponding to the known input, and then adjusting one or more parameters of a forward and/or a feedforward path of the system so that the difference in transfer functions of these paths may be reduced/minimized. Calibrating CT residue generation systems using test signals may help decrease the magnitude of the residue signals generated by such systems, and, consequently, advantageously increase an error correction range of such systems or of further stages that may use the residue signals as input.

Abstract: A drive sense circuit comprises an analog front-end. The analog front-end generates an analog drive sense signal based on an analog reference signal that has a magnitude that is substantially less than a supply rail power of the drive sense circuit. When the drive sense circuit is coupled to a load, the analog front end drives the load with the analog drive-sense signal and detects an analog signal variation in the analog drive-sense signal based on a characteristic of the load.

Abstract: An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.

Abstract: A delta-sigma modulator may include a loop filter, a quantizer, an input gain element having a programmable input gain and coupled between an input of the delta-sigma modulator and an input of the loop filter, a feedforward gain element having a programmable feedforward gain and coupled between the input of the delta-sigma modulator and an output of the loop filter, and a quantizer gain element having a quantizer gain and coupled between the output of the loop filter and an input of the quantizer. The programmable input gain is controlled in order to control a variable gain of the delta-sigma modulator. The programmable feedforward gain is controlled to be equal to the ratio of the programmable input gain and the quantizer gain such that the delta-sigma modulator has a fixed phase response.

Abstract: Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector may detect metastability at an output of a SAR ADC and compensator circuitry may implement a compensation scheme to compensate for the metastability. The identification of the metastability and/or compensation for the metastability can avoid detrimental effects and/or errors to the DSM loops that may be caused by the metastability of the SAR ADCS.

Abstract: The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing deterioration in signal characteristics due to parasitic capacitance caused by providing a configuration for realizing an electrode plating process when an electrode and an amplifier are provided on the same substrate. When a power source supplies a potential necessary for plating processing and a breaker reads a signal from liquid, and an amplifier amplifies and outputs the signal, the power source required for the plating processing is blocked with respect to the electrode. This is applicable to the potential measuring apparatus.