Abstract: This specification discloses a brain electrode device. The brain electrode device includes a set of contact points and a set of sub-circuits. The sub-circuits include sensor ports configured to connect to the contact to the respective ones of the contact points. The device can further include an intelligent multiplexer that aggregates signals from the set of sub-circuits and generates an aggregate signal. The aggregate signal is transmitted to a signal acquisition device.

Abstract: Devices and methods for determining the cumulative distribution of a polymer property in a reactor without physical separation of reaction subcomponents. The device includes a means of measuring an instantaneous property of the polymers being produced in a reaction vessel a plurality of times during a polymerization reaction as well as a means of determining the corresponding change in polymer concentration in the reaction vessel between measurements of the instantaneous polymer property. The device also includes a means of computing a statistical distribution appropriate to the polymer characteristic and applying the statistical distribution to a recently measured instantaneous value of the polymer property so as to have an instantaneous distribution of the polymer property and a means of adding together the instantaneous distributions of the polymer property in order to obtain the cumulative distribution of the polymer property in the reactor.

Abstract: Some embodiments provide a Quanta Image Sensor (QIS) comprising 3D vertically-stacked photosensor array and readout circuitry. In some embodiments, an imaging array comprises a plurality of single-bit or multi-bit jots, and readout circuitry in electrical communication with the imaging array and configured to quantize, for each jot, an analog signal corresponding to the electrical signal of the jot, wherein the imaging system is configured as a 3D vertically integrated circuit with the imaging array stacked vertically above the readout circuitry. The imaging array may be configured as an array of clusters with respect to the readout circuitry, each cluster configured as an array of n by m jots. The imaging array may include a further image processing circuitry layer disposed below the readout circuitry layer. Neighboring layers may be implemented on separate substrates and/or in a common substrate.

Abstract: A confined data communication system includes a reference generation circuit operable to produce one or more analog reference signals, an analog to digital converter circuit operable to process an analog signal to produce a digital representative signal, a digital filtering circuit operable to filter the digital representative signal to produce an affect value, a data processing module operable to interpret the affect value to produce processed output data, and a processing module operable to set frequency and waveform for each of the one or more analog reference signals, set digital filtering parameters for the digital filtering circuit, set a sampling rate for the analog to digital converter circuit, and set data interpretation parameters for the data processing module.

Abstract: A method of calibrating an analog front end (AFE) filter of a radio frequency integrated circuit (RFIC) includes: making a first measurement of the RFIC at a first measuring frequency while the AFE filter is bypassed; generating a first amplitude estimate and a first phase estimate at the first measuring frequency using the first measurement; making a second measurement of the RFIC at the first measuring frequency while the AFE filter is turned on; generating a second amplitude estimate and a second phase estimate at the first measuring frequency using the second measurement; and calculating a frequency response of the AFE filter at the first measuring frequency, which includes calculating an amplitude response of the AFE filter based on the second amplitude estimate and the first amplitude estimate; and calculating a phase response of the filter based on the first phase estimate and the second phase estimate.

Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.

Abstract: The present disclosure discloses a touch sensing signal processing circuit which senses a change in capacitance of a sensing node for touch sensing and provides a logic signal corresponding to the touch sensing. The touch sensing signal processing circuit of the present disclosure is configured using a delta-sigma analog to digital converter. Auto-tuning may be performed by delta-sigma analog conversion.

Abstract: A digital-to-analog converter comprising: a plurality of capacitances and a plurality of switches. A capacitance among the plurality of capacitances, of which the number corresponds to the resolution of the analog signal to be output, is used as a voltage value generation capacitance, so as to generate a voltage value based on the reference voltage to be added or subtracted, by switching a node to which the second terminal is connected by a corresponding switch. A remaining capacitance, which is not used as the voltage value generation capacitance among the plurality of capacitances, is used as a gain adjustment capacitance, so as to adjust gain of a voltage value based on the reference voltage to be added or subtracted, by holding a node to which the second terminal is connected by a corresponding switch.

Abstract: Disclosed is an image sensing device including a plurality of current cells whose total number to be used is adjusted based on a plurality of enable signals, and which are sequentially controlled based on a reset signal and a plurality of selection signals; a current-voltage conversion circuit suitable for converting a plurality of unit currents, which are supplied from current cells used among the plurality of current cells, into a ramp signal; and a first control circuit suitable for generating the plurality of enable signals based on a maximum conversion code value corresponding to a slope of the ramp signal.

Abstract: Clock and other cyclical signals are driven onto respective capacitively-loaded segments of a distribution path via inverting buffer stages that self-correct for stage-to-stage duty cycle error, yielding a balanced signal duty cycle over the length of the distribution path.

Abstract: A multiply-and-accumulate (MAC) circuit having a plurality of compute-in-memory bitcells is configured to multiply a plurality of stored weight bits with a plurality of input bits to provide a MAC output voltage. A successive approximation analog-to-digital converter includes a capacitive-digital-to-analog-converter (CDAC) configured to subtract a bias voltage from the MAC output voltage to provide a CDAC output voltage. A comparator compares the CDAC output voltage to a fixed reference voltage.

Abstract: A method for execution by an input/output (IO) control module of an integrated circuit (IC) includes determining whether a programmable IO interface module is for dynamic or static use. The programmable IO interface module includes a configurable front-end module and a configurable back-end module. When the programmable IO interface module is for the dynamic use, determining to configure the programmable IO interface module as the dynamic use of a configuration of a plurality of configurations. The plurality of configurations includes a bidirectional interface, an input, an output, a concurrent drive and sense interface, and a concurrent transmit-receive interface. The method further includes configuring the front-end module in accordance with the configuration, configuring the back-end module in accordance with the configuration, and determining whether to change the configuration to another configuration of the plurality of configurations.

Abstract: An electronic device may include wireless circuitry having analog-to-digital converter (ADC) circuitry. The ADC circuitry may include a sampling switch coupled to a bootstrap circuit. The bootstrap circuit may include a bootstrap capacitor, a first transistor coupled between an input of the sampling switch and a bottom plate terminal of the bootstrap capacitor, a second transistor coupled between the bottom plate terminal of the bootstrap capacitor and ground, and a resistor or transistor that is disposed between the first transistor and the bottom plate terminal of the bootstrap capacitor and that is configured to boost the input impedance of the bootstrap circuit.

Abstract: An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.

Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.

Abstract: A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.

Abstract: A device for providing side-channel protection to a data processing circuit is provided and includes a chaotic oscillator and a counter. The data processing circuit has an input for receiving an input signal, a power supply terminal, and an output for providing an output signal. The chaotic oscillator circuit has an input coupled to receive a control signal, and an output coupled to provide an output signal for controlling a voltage level of a power supply voltage of the data processing circuit. The counter has an input coupled to receive a clock signal, and an output coupled to control a variable parameter of the chaotic oscillator in response to the clock signal. In another embodiment, a method is provided providing the side-channel protection to the device.

Abstract: One example discloses a differential-signal-detection circuit, comprising: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive the first differential output signal and generate a first comparator output signal; a second comparator coupled to receive the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal.

Abstract: A digital-to-analog conversion, including: converting signal Y using word X=M+???N having length ?=?+? digits, where M is high order digits of ? long control word X, ???N is low order digits of ? long control word X, wherein ???; subjecting analog signal Z to three conversions, wherein, in the first conversion, signal Z1 is proportional to M? long high order digits of X, and to reference signal Y1, where Z1=Y1×M, in the second and third conversions, signals Z2 and Z3 are proportional to N? long low order digits of X and to signals Y1 and Y2, respectively, where Z2=Y1×N, and Z3=Y2×N, wherein, before the conversions, ???N low order digits of X are multiplied by ??; and adding Z1, Z2, Z3 to generate output signal Z0, wherein Y1 and Y2 relate by Y2=Y1(1±???), wherein ? is the base of the numbering system, ? is the number of digits, by which ???N is shifted.

Abstract: Sensors, including time-of-flight sensors, may be used to detect objects in an environment. In an example, a vehicle may include a time-of-flight sensor that images objects around the vehicle, e.g., so the vehicle can navigate relative to the objects. Sensor data generated by the time-of-flight sensor can return pixels subject to over-exposure or saturation, which may be from stray light. In some examples, multiple exposures captured at different exposure times can be used to determine a saturation value for sensor data. The saturation value may be used to determine a threshold intensity against which intensity values of a primary exposure are compared. A filtered data set can be obtained based on the comparison.

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

Abstract: The present application discloses a successive approximation register analog-to-digital converter with passive noise shaping, which comprises: switch capacitor arrays for acquiring analog input signals; a noise shaping circuit which is a passive integral network, the network has input ends connected respectively with output ends of the two switch capacitor arrays and for acquiring output signals of the two switch capacitor arrays, is composed of a plurality of sub passive integrators, and reconfigures the plurality of sub passive integrators to different circuit forms; a comparator which has two input ends connected respectively with output ends of the passive integral network and an output end connected with an input end of a logic circuit, and is configured to compare magnitudes of the output signals of the noise shaping circuit.

Abstract: An imaging system according to the present disclosure includes: an imaging device that is mounted in a vehicle, and captures and generates an image of a peripheral region of the vehicle; and a processing device that is mounted in the vehicle, and executes processing related to a function of controlling the vehicle on the basis of the image. The imaging device includes: a first control line, a first voltage generator that applies a first voltage to the first control line, a first signal line, a plurality of pixels that applies a pixel voltage to the first signal line, a first dummy pixel that applies a voltage corresponding to the first voltage of the first control line to the first signal line in a first period, a converter including a first converter that performs AD conversion on the basis of a voltage of the first signal line in the first period to generate a first digital code, and a diagnosis section that performs diagnosis processing on the basis of the first digital code.

Abstract: A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver.

Abstract: An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency. The analog signal includes a set of pure tone components. The first digital signal includes n 1-bit channels. The analog to digital conversion circuit further includes a digital decimation filtering circuit including n anti-aliasing filters operable to sample and filter the n 1-bit channels of the first digital signal to produce n second digital signals and n decimator circuits operable to decimate the n second digital signals to produce n third digital signals at a second data rate frequency. The analog to digital conversion circuit further includes a multiplexor operable to output the n third digital signals at the second data rate frequency on a single bus.

Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.

Abstract: This invention provides a secure method for sending data—private, arrival-time messaging. Private, arrival-time messaging is based on classical physics and not quantum mechanics. It insures a private language for communicators with privately-synchronized clocks. In this method, there is no encrypted message available to an eavesdropper. A private message is mapped onto a time measurement known only to an intended sender and an intended receiver such that a third party knowing only the arrival time of the message and not the time measurement can never know the private message.

Abstract: Methods, systems, and apparatus for quantum analog-digital conversion. In one aspect, a method includes obtaining a quantum analog signal; applying a hybrid analog-digital encoding operation to the quantum analog signal and a qudit in an initial state to obtain an evolved state of the qudit, wherein the hybrid analog-digital encoding operation is based on a swap operation comprising multiple adder operations; and providing the qudit in the evolved state as a quantum digital encoding of the quantum analog signal.

Abstract: A network platform manages the provisioning of a UE with a dominant identity profile and a recessive identity profile. The dominant profile is associated with a user's existing wireless data plan and the recessive profile corresponds to a data plan of a provider of device, or machine-to-machine, services to the UE. The UE uses the two profiles to transmit separate data contexts on separate respective bearers. When managing two separate bearers, the UE always uses the dominant profile first for managing a handoff to a stronger cell. The UE reports that the new cell that now serves the dominant context is the only cell that has enough strength to support the recessive context, even if other cells near the UE have signals strong enough. This necessarily causes the recessive context to always be handed off to the same cell to which the dominant context has already been handed off.

Abstract: A light sensor module includes a substrate. A first detection region is provided on the substrate. At least one photosensitive device is provided inside the first detection region. The at least one photosensitive device is adapted to collecting first light sensor data from the first detection region under current incident light. The first light sensor data are used for determining whether light sensor data collected by the light sensor module under the current incident light are to be compensated.

Abstract: A memristor-based circuit includes a voltage generator that applies a series of voltage pulses to a memristor to progressively change the resistance of the memristor. A comparator: receives an input electrical value; receives an electrical value based on the resistance of the memristor; compares the received values; and, based on the comparison, enables the application of the voltage pulses to the memristor by the voltage generator until a defined condition is satisfied. This circuit can be used to enable the memristor to be programmed to a desired resistance value, such as for use as a non-volatile memory. It can also enable the resistance of one memristor to be replicated to another memristor. By counting the number of applied voltage pulses, the circuit can be used as an encoder or analog-to-digital converter. Other variants of the circuit enable construction of a decoder or digital-to-analog converter, and an authentication circuit.

Abstract: An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.

Abstract: A calibration circuit, including: a first analog-to-digital converter (ADC) configured to sample a nonlinear reference signal continuously at an equidistant sampling rate to generate a reference sampled signal; a trigger timer configured to generate trigger signals; a second ADC configured to sample a point of each of the nonlinear reference signal and repeated versions of the nonlinear reference signal in response to the respective trigger signals at equidistantly increasing delays, to generate a device-under-test (DUT) sampled voltage; and processing circuitry configured to estimate a differential nonlinearity (DNL) of the DUT sampled signal, estimate a DNL of the reference sampled signal, and compare the estimated DNL of the DUT sampled signal with the estimated DNL of the reference sampled signal, to generate a DNL performance indication signal of the second ADC.

Abstract: An accessory device has a test port, an instrument port to connect to an instrument having an operating bandwidth, and one or more configurable signal paths connectable between the test port and the instrument port to convert a signal from the test port having a first frequency range to a signal having a second frequency range different than the first frequency range. A test and measurement system has a test and measurement instrument having an operating bandwidth, and an accessory device. The accessory device has a first instrument port to connect the accessory device to the test and measurement instrument, a test port to connect the accessory device to a device under test, and one or more configurable signal paths connectable between the test port and the instrument port to down-convert a signal from the test port having a first frequency range to a signal having a second frequency range lower than the first frequency range.

Abstract: An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled

Abstract: Under one aspect, a method is provided for processing a received signal, the received signal including a desired signal and an interference signal that spectrally overlaps the desired signal. The method can include obtaining an amplitude of the received signal. The method also can include obtaining an average amplitude of the received signal based on at least one prior amplitude of the received signal. The method also can include subtracting the amplitude from the average amplitude to obtain an amplitude residual. The method also can include, based upon an absolute value of the amplitude residual being less than or equal to a first threshold, inputting the received signal into an interference suppression algorithm so as to generate a first output including the desired signal with reduced contribution from the interference signal.

Abstract: An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.

Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

Abstract: An I/O interface configuration device for configuring I/O interfaces comprises an input interface, an output interface, a storage unit, a detecting pin, a converting unit and a computing unit. The input interface electrically connects to a controlling port of a controlling circuit to receive a data type. The output interface electrically connects to a controlled port of a controlled device to output another data type. The storage unit stores a plurality of configuration files, one of the configuration files corresponds to a circuit type of the controlling circuit. The detecting pin is adapted to retrieve the circuit type. The converting unit converts the data type to said another data type and selectively outputs said another data type from the output interface. The computing unit loads the configuration file corresponding to the circuit type and control the converting unit to configure the I/O interface according to the configuration file.

Abstract: An analog-to-digital converter has a first digital signal generator that generates a first digital signal based on whether or not a sampling signal of an input signal is equal to or lower than a signal corresponding to a second reference signal higher than a first reference signal, a first slope generator to generate a first slope signal that changes with time from the sampled and held signal equal to or lower than the first reference signal, a second slope generator to generate a second slope signal that changes with time from the sampled and held signal to a signal level equal to or lower than the second reference signal, and a second digital signal generator that generates a second digital signal based on a time at which the first slope signal matches the first reference signal or a time at which the second slope signal matches the second reference signal.

Abstract: An operation method of a receiving device may comprise: receiving a periodic band-limited signal from a transmitting device; determining whether a carrier frequency of the periodic band-limited signal satisfies a constraint; converting the periodic band-limited signal into a digital high-frequency band signal by sampling the periodic band-limited signal at an extraction rate equal to or less than a Nyquist extraction rate when the carrier frequency satisfies the constraint; down-converting the digital high-frequency band signal into a digital baseband signal; rearranging samples of a plurality of periods of the digital baseband signal into one period; and generating a reconstructed signal by performing low-pass filtering with a bandwidth of the periodic band-limited signal on the digital baseband signal in which the samples are rearranged.

Abstract: A technique for generating analog waveforms includes combining a desired, in-band signal with a randomizing, out-of-band signal at an input of a DAC, operating the DAC to generate DAC output based on a combination of the desired signal and the randomizing signal, and filtering the DAC output to pass the desired signal while removing the randomizing signal.

Abstract: Techniques for designing, creating, and utilizing a current biased tunable qubit are presented. A qubit device can comprise a first Josephson junction (JJ) located along a first current path of the device, and a second JJ and third JJ coupled in series along a second current path in parallel with the first current path, wherein the second and third JJs facilitate controlling frequency of the device. The first JJ can be larger in area than each of the second and third JJs, wherein a current splitting ratio between the first current path and second current path can be increased thereby. The device can comprise a capacitor with a first terminal associated with the second and third JJs, and a second terminal associated with ground. Alternatively, a high kinetic inductance wire can be used in the first current path, instead of the JJ.

Abstract: A digital pixel sensor for correcting and reducing a mismatch between a pixel and an analog digital converter provided. The digital pixel sensor includes a pixel array including a plurality of pixels; and a bank disposed on the pixel array. The bank includes: a plurality of comparators disposed on the plurality of pixels and configured to compare each of a plurality of pixel signals output from the plurality of pixels with a reference signal to output a plurality of comparison result signals; and a counter connected to the plurality of comparators, and configured to receive the plurality of comparison result signals and latch count code based on the plurality of comparison result signals.

Abstract: Disclosed is an image sensor. The image sensor includes an active pixel sensor array including first to fourth pixel units sequentially arranged in a column direction, and each of the first to fourth pixel units is composed of a plurality of pixels. A first pixel group including the first and second pixel units is connected to a first column line, and a second pixel group including the third pixel unit and the fourth pixel unit is connected to a second column line. The image sensor includes a correlated double sampling circuit including first and second correlated double samplers and configured to convert a first sense voltage sensed from a selected pixel of the first pixel group and a second sense voltage sensed from a selected pixel of the second pixel group into a first correlated double sampling signal and a second correlated double sampling signal, respectively.

Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Abstract: A continuous time digital signal processing (CT DSP) token includes a first signal indicating a change has occurred and a second signal indicating a direction of the change. An amplitude generation circuit operates to generate an amplitude value x in response to the token. A power estimation circuit processes the amplitude value x to generate a digital power signal in accordance with the formula: x2±2x+1.

Abstract: A TI-ADC (50) comprising a group of sub-ADCs (A1-AM+N) is disclosed. During operation, M?2 of the sub-ADCs (A1-AM+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A1-AM+N) in the group is M+N, N?1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A1-AM+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A1-AM+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (Ak1) in a first subset of the group of sub-ADCs (A1-AM+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme.

Abstract: In order to control communication operations properly in a secondary cell even when a beam failure and/or a BR failure occur in the secondary cell, a user terminal, according to one aspect of the present disclosure, has a control section that controls adjustment of a deactivation timer for a certain secondary cell and/or indication of a beam failure and/or a beam recovery (BR) failure in the certain secondary cell, based on the beam failure and/or a result of BR in the certain secondary cell, and a transmission section that transmits information about the beam failure and/or the BR failure in the certain secondary cell by using another cell.