Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

Abstract: An apparatus includes a decoding circuit, and a communication bus that is configured to transfer a particular data payload and a control signal that indicates whether the particular data payload includes a mask value. The mask value is indicative of enabled and non-enabled data words in the particular data payload. The decoding circuit is configured to receive, from an encoding circuit via the communication bus, the particular data payload and the control signal. In response to a determination that the control signal indicates that the particular data payload does not include the mask value, the decoding circuit is configured to use a default value for the mask value, and to create an uncompressed data payload from the particular data payload using the default value, wherein the default value causes the decoding circuit to maintain positions of data words between the particular data payload and the uncompressed data payload.

Abstract: This application provides a signal generation apparatus and method, and a system. The signal generation apparatus includes an encoder, a serializer, an equalizer, and N amplifiers. The encoder is configured to encode to-be-sent data, to obtain a first electrical signal. The serializer is configured to perform parallel-to-serial processing on the first electrical signal, to obtain a second electrical signal. The equalizer is configured to process the second electrical signal, to obtain a third electrical signal. The third electrical signal is amplified by the N amplifiers, to obtain N pairs of differential signals, where N is an integer greater than 2. In embodiments of this application, the N amplifiers amplify differential signals to obtain N pairs of differential signals, and the N pairs of differential signals are directly used as drive signals, so that power consumption for generating a drive signal can be reduced.

Abstract: A binary encoder includes an input configured to receive a binary signal, an encoding processor configured to compute a plurality of different variations of the binary signal, combine each of the different variations with a different redundancy sequence to create a plurality of optional output binary sequences, and select one of the optional output binary sequences according to a binary digit prevalence, and an output configured to output the selected binary sequence. A decoder configured to identify a redundancy sequence of a received binary signal to select a transformation function according to the redundancy sequence and to convert the binary signal according to the transformation function.

Abstract: A system for transmitting data over an optical communication path is configured to receive data to be encoded in a bitstream for transmission using an optical communication path and encodes the received data to obtain a bitstream. The system is further configured to determine that the bitstream includes a sequence of consecutive bits, and obtain a power level at which to transmit a portion of the bitstream based on a count of the consecutive bits in the sequence. The system may be configured to selectively activate a light source at a power level according to a modulation scheme to optically transmit the portion of the bitstream at the power level.

Abstract: An apparatus includes an encoding circuit, and a communication bus having conductive traces configured to transfer a data payload, including a control signal and up to a maximum number of data words. The encoding circuit is configured to receive an uncompressed data payload and a mask value, and to create, using the mask value, the control signal, the control signal indicative of whether the uncompressed data payload includes one or more non-enabled data words. In response to a determination that the control signal indicates that the uncompressed data payload includes one or more non-enabled data words, the encoding circuit is configured to create a compressed data payload from the uncompressed data payload, and to send, to a decoding circuit, the compressed data payload and the control signal via the plurality of conductive traces of the communication bus. The compressed data payload includes the mask value.

Abstract: Digital data (11) is encoded to a set of five line symbols for optical transmission. The line symbols have amplitude values of 0, ±A1, ±A2, where |A2|>|A1|. A first binary value maps to the line symbols 0 and ±A2 and a second binary value maps to the line symbols ±A1. The amplitude values of the line symbols can be in the ratio A1:A2=1:sqrt(2). At a receiver, the received signal is photodetected to generate an electrical signal which can represent a set of three possible received symbols (RS1, RS2, RS3). Digital data (26) is recovered from the received symbols by comparing the electrical signal with a first amplitude threshold (TH1) and a second amplitude threshold (TH2).

Abstract: A multivalued microprocessor including a multivalued processing module having a plurality of multivalued processing units constructed with multivalued logic gates. The microprocessor also includes a multivalued register file having a plurality of registers, wherein the registers are constructed with multivalued memory cells. The multivalued microprocessors utilizes two memory modules constructed with multivalued memory cells: one for storing solely instructions and one for storing solely data. A plurality of multivalued buses transmit multivalued data between the processing module, the register file, and the memory modules. A methodology for designing multivalued circuits that are constructed with multivalued logic gates and memory cells. The designs of multivalued memory cells, multivalued tristate buffers, and multivalued decoders using multivalued logic gates.

Abstract: A method and apparatus for transferring data maps the data to a modulation code using an encoder circuit having a configuration. A binary symbol of the data is mapped to a modulation code having a plurality of modulation digits and a modulation signal is generated based on the modulation code. A transmitter drive signal is modulated based on the modulation signal. A configuration of the encoder circuit is set based on a determined performance level. The transmitter drive signal may be used to produce an electromagnetic field by generating a positive, negative or zero electrical current in an induction coil of a first semiconductor die. A current induced by the electromagnetic field in an induction coil of a second semiconductor die is demodulated to recover the data whereby the data is transferred from the first semiconductor die to the second semiconductor die.

Abstract: The quantization parameters (QP) for Chroma are extended up to and more preferably to the same range as Luma QP (e.g., 0 to 51). Previous, values of Chroma QP only extended up to 39. Techniques are provided for determining extended Chroma QP values (e.g., for Cr and Cb) based on the Luma QP and picture level chroma offsets. In one preferred embodiment, slice level offsets are added making the method particularly well-suited for slice level parallel processing. The extension of Chroma QP enhances functionality, flexibility and friendliness of the High Efficiency Video Coding (HEVC) standard for various applications.

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

Abstract: A system may include an interface circuit and a plurality of wire buses electrically coupled with one another. The interface circuit may include transmitters which change states of the plurality of wire buses to transmit a plurality of multilevel symbols. The transmitters may drive wire buses, coupled to each other, to a termination voltage level.

Abstract: Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.

Abstract: The quantization parameters (QP) for Chroma are extended up to and more preferably to the same range as Luma QP (e.g., 0 to 51). Previous, values of Chroma QP only extended up to 39. Techniques are provided for determining extended Chroma QP values (e.g., for Cr and Cb) based on the Luma QP and picture level chroma offsets. In one preferred embodiment, slice level offsets are added making the method particularly well-suited for slice level parallel processing. The extension of Chroma QP enhances functionality, flexibility and friendliness of the High Efficiency Video Coding (HEVC) standard for various applications.

Abstract: According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

Abstract: The quantization parameters (QP) for Chroma are extended up to and more preferably to the same range as Luma QP (e.g., 0 to 51). Previous, values of Chroma QP only extended up to 39. Techniques are provided for determining extended Chroma QP values (e.g., for Cr and Cb) based on the Luma QP and picture level chroma offsets. In one preferred embodiment, slice level offsets are added making the method particularly well-suited for slice level parallel processing. The extension of Chroma QP enhances functionality, flexibility and friendliness of the High Efficiency Video Coding (HEVC) standard for various applications.

Abstract: A system may include an interface circuit and a plurality of wire buses electrically coupled with one another. The interface circuit may include transmitters which change states of the plurality of wire buses to transmit a plurality of multilevel symbols. The transmitters may drive wire buses, coupled to each other, to a termination voltage level.

Abstract: The quantization parameters (QP) for Chroma are extended up to and more preferably to the same range as Luma QP (e.g., 0 to 51). Previous, values of Chroma QP only extended up to 39. Techniques are provided for determining extended Chroma QP values (e.g., for Cr and Cb) based on the Luma QP and picture level chroma offsets. In one preferred embodiment, slice level offsets are added making the method particularly well-suited for slice level parallel processing. The extension of Chroma QP enhances functionality, flexibility and friendliness of the High Efficiency Video Coding (HEVC) standard for various applications.

Abstract: The quantization parameters (QP) for Chroma are extended up to and more preferably to the same range as Luma QP (e.g., 0 to 51). Previous, values of Chroma QP only extended up to 39. Techniques are provided for determining extended Chroma QP values (e.g., for Cr and Cb) based on the Luma QP and picture level chroma offsets. In one preferred embodiment, slice level offsets are added making the method particularly well-suited for slice level parallel processing. The extension of Chroma QP enhances functionality, flexibility and friendliness of the High Efficiency Video Coding (HEVC) standard for various applications.

Abstract: The quantization parameters (QP) for Chroma are extended up to and more preferably to the same range as Luma QP (e.g., 0 to 51). Previous, values of Chroma QP only extended up to 39. Techniques are provided for determining extended Chroma QP values (e.g., for Cr and Cb) based on the Luma QP and picture level chroma offsets. In one preferred embodiment, slice level offsets are added making the method particularly well-suited for slice level parallel processing. The extension of Chroma QP enhances functionality, flexibility and friendliness of the High Efficiency Video Coding (HEVC) standard for various applications.

Abstract: The quantization parameters (QP) for Chroma are extended up to and more preferably to the same range as Luma QP (e.g., 0 to 51). Previous, values of Chroma QP only extended up to 39. Techniques are provided for determining extended Chroma QP values (e.g., for Cr and Cb) based on the Luma QP and picture level chroma offsets. In one preferred embodiment, slice level offsets are added making the method particularly well-suited for slice level parallel processing. The extension of Chroma QP enhances functionality, flexibility and friendliness of the High Efficiency Video Coding (HEVC) standard for various applications.

Abstract: A power supply system providing communication from a master module to at least one slave module via transients, to alter operation of a load, is provided. The master module output a supply voltage that is either a normal supply voltage or a reduced supply voltage. The outputted supply voltage depends on input corresponding to a communication to be sent to the slave module to alter operation of the load of the slave module. The slave module receives the supply voltage and interprets the received supply voltage, which may vary between the normal and reduced supply voltages, to determine what the communication from the master module is. The slave module then uses information from the communication to appropriately alter operation of its load.

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices.

Abstract: Embodiments are provided for a quaternary decoder that includes a plurality of decoder circuits, each decoder circuit coupled to a respective input line of a plurality of quaternary interface lines and to a respective pair of binary output lines; and a control logic circuit having a plurality of control signal lines coupled to each of the plurality of decoder circuits, the control logic circuit configured to: output a first sequence of logic levels, and output a second sequence of logic levels after the first sequence is complete; wherein at a time after the second sequence is complete, each decoder circuit is configured to output a pair of binary data values that correspond to a quaternary state of the respective input line, the quaternary state being one of four quaternary states including a logic high state, a logic low state, a floating state, and a tie-back state.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

Abstract: An integrated sensor device (130) according to an embodiment includes a sensing element (140) and a communication interface (150) to communicate with an external control device (110). The communication interface (150) includes a receiver circuit (160) to receive, from the external device, a signal indicating a request to change a transmission mode, and a transmitter circuit (170) to change the transmission mode based on the received signal. By using an embodiment, it may be possible to improve a trade-off between a robustness of a system comprising a sensor even under adverse operational conditions, simplifying such an implementation or architecture, its energy consumption and a bandwidth of its infrastructure.

Abstract: Systems and methods for communicating digital data over a group of conductors include encoding data based on electromagnetic parameter values associated with two or more group symbols each having an independent encoding value such that a mathematical function of the encoding values in the group symbols yields a known value and communicating the encoded data by applying signals associated with the electromagnetic parameter values to the group of conductors.

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract: According to various examples, alternator controllers, systems for communicating with an alternator controller and methods for communicating with an alternator regulator are described herein. As an example, the alternator controller includes an input terminal configured to be coupled to a coil of a stator of an alternator and an interface circuit coupled to the input terminal and configured to convert a multi-valued signal at the input terminal into parallel signals. According to another example, a system for communicating with an alternator controller is described herein. This example includes a device and an alternator controller. The device includes an encoder. The alternator controller includes a decoder and at least one phase terminal. The encoder and the decoder are coupled via the at least one phase terminal of the alternator controller.

Abstract: Circuitry for transferring multiple digital data streams, e.g. digital audio data, over a single communications link such as a single wire. A pulse-length-modulator is responsive to a plurality of data streams to generate a series of data pulses with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal. The timing of the rising and falling edge of each data pulse is dependent on a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. An interface receives the stream of data pulses, and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.

Abstract: A method and an apparatus relating to an OFDM data communications system where the sub-carriers are modulated using differential quadrature phase-shift keying (DQPSK). The multi-carrier transmitted signal is directly generated using a summation of pre-computed sample points. As part of the multi-carrier signal generation, a signal for the guard interval is established. In an acoustic application of this approach, direct radiation of the sub-carrier approach is facilitated. Symbol synchronization in the receiver is based on signal correlation with the missed sub-carrier. Separation of the sub-carriers in the receiver uses a correlation of the received signal and reference signals that are derived from a table of pre-computed values. Optimal non-coherent processing of the sub-carriers without any phase tracking procedures is achieved.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

Abstract: An apparatus is provided for decoding last position information indicating a horizontal position and a vertical position of a last non-zero coefficient in a predetermined order within a current block to be decoded, the current block being included in a picture and including a plurality of coefficients. The apparatus includes one or more processors, a communication unit, and storage coupled to the one or more processors and the communication unit. The communication unit is configured to transmit a request for a bitstream to an external system, and receive the bitstream from the external system. The one or more processors are configured to obtain the bitstream, perform first arithmetic decoding, perform second arithmetic decoding, derive a horizontal component of the last position information, and derive a vertical component of the last position. A system for decoding and a displaying method are also provided.

Abstract: Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data.

Abstract: A decoding method decodes last position information indicating horizontal and vertical positions of a last non-zero coefficient in a predetermined order within a current block to be decoded, the current block including plural coefficients. The decoding includes obtaining a bitstream including first, second, third and fourth partial signals, in this order, performing first arithmetic decoding on the first and the third partial signals respectively to obtain decoded first and decoded third partial signals, performing second arithmetic decoding on the second and the fourth partial signals respectively to obtain decoded second and decoded fourth partial signals, the second arithmetic decoding being different from the first arithmetic decoding, deriving a horizontal component of the last position information from the decoded first and decoded third partial signals, and deriving a vertical component of the last position information from the decoded second and decoded fourth partial signals.

Abstract: Methods and apparatus intelligently switching between line coding schemes based on context. In one exemplary embodiment, an High Definition Multimedia Interface (HDMI) system is configured to transmit control and video data according to an 8B/10B line coding protocol, and data island data according to TERC4 (TMDS (Transition Minimized Differential Signaling) Error Reduction Coding 4-bit). Various elements of the disclosed HDMI devices are configured to determine when a context switch occurs, and thereafter seamlessly transition between the appropriate line code protocol.

Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.

Abstract: A system and method is disclosed for adding a low data rate data channel to a 100Base-T Ethernet link without significantly impacting an IEEE defined 100Base-T protocol for the Ethernet link. A dual data channel transmitter encodes a high data rate data stream in an MLT-3 encoder and encodes a low data rate data stream using bit representations that are not valid bit representations in the MLT-3 encoder. The dual data channel transmitter transmits both of the encoded bit streams in a dual data stream. A dual data channel receiver receives the dual data stream and separates and decodes the two bit streams. A low data rate data channel is provided in conjunction with a high data rate data channel without significantly impacting the operation of the high data rate data channel.

Abstract: Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data.

Abstract: Embodiments of the present invention disclose a data decoding method and apparatus, relate to the field of wireless communications, and can improve a resource utilization rate in a decoding process, thereby improving decoding efficiency. The method of the present invention includes: dividing a to-be-decoded data transport block into N code blocks, where N is an integer greater than or equal to 2; and decoding the N code blocks in parallel according to a reverse direction of encoding. The present invention is applicable to data decoding.

Abstract: A method for determining a parity check matrix utilized in a flash memory system is disclosed. The parity check matrix comprises M×N blocks. The method includes generating a first set of candidate blocks as candidates of a first set of blocks of the M×N blocks; calculating a plurality of first estimated results corresponding to the first set of candidate blocks; determining content of a first block of the M×N blocks according to a best result of the first estimated results; generating a second set of candidate blocks as candidates of a second set of blocks of the M×N blocks; calculating a plurality of second estimated results corresponding to the second set of candidate blocks by considering the content of the first block; determining content a second block of the M×N blocks according to the second estimated results.

Abstract: A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line.

Abstract: An encoder performs context-adaptive arithmetic encoding of transform coefficient data. For example, an encoder switches between coding of direct levels of quantized transform coefficient data and run-level coding of run lengths and levels of quantized transform coefficient data. The encoder can determine when to switch between coding modes based on a pre-determined switch point or by counting consecutive coefficients having a predominant value (e.g., zero). A decoder performs corresponding context-adaptive arithmetic decoding.

Abstract: An image coding method including: binarizing a first component and a second component which are included in last position information, to generate a first binary signal and a second binary signal, respectively; coding, by first arithmetic coding, a first partial signal which is a part of the first binary signal and a second partial signal which a part of the second binary signal, and coding, by second arithmetic coding, a third partial signal which is another part of the first binary signal and a fourth partial signal which is another part of the second binary signal; and placing the coded first through fourth partial signals in a bit stream, wherein in the placing, (i) the coded second partial signal is placed next to the coded first partial signal, or (ii) the coded fourth partial signal is placed next to the coded third partial signal.

Abstract: In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a sparse signaling code, wherein a codeword is representable as a vector of a plurality of components, some of which are quiescent components and some of which are non-quiescent components, wherein the number of quiescent components and non-quiescent components meet a sparseness requirement.

Abstract: This disclosure describes techniques for coding an enhancement layer in a scalable video coding (SVC) scheme. The techniques involve run-length coding of significant coefficients and refinement coefficients of the enhancement layer. Rather than performing two different run-length passes to separately code the significant coefficients and refinement coefficients, the techniques of this disclosure perform run-length coding of the significant coefficients and refinement coefficients together. Therefore, run values of the run-length coding codes the significant coefficients with the refinement coefficients. Additional techniques are also described, which can eliminate the need to send sign information for some of the refinement coefficients. Instead, this sign information for some of the refinement coefficients may be derived at the decoder based on the sign values of corresponding coefficients of previously encoded layers of the SVC scheme, which can further improve compression efficiency.