Abstract: The present disclosure provides a computation device including: a computation module for executing a neural network computation, and a power conversion module connected to the computation module, for converting input data and/or output data of the neural network computation into power data. The present disclosure further provides a computation method. The computation device and method of the present disclosure may reduce the cost of storage resources and computing resources, and may increase the computation speed.

Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.

Abstract: A system includes first logic to obtain a plurality of constituent data streams for each data object of a plurality of objects, second logic to analyze the plurality of constituent data streams to allocate each constituent data stream to one of a set of primary groups, third logic to assign the constituent data streams within each primary group of the set of primary groups having aligned timing to a netting group of the primary group, fourth logic to generate, for each netting group of each primary group of the set of primary groups, a plurality of continuous data streams by combining two or more of the constituent data streams within the netting groups, fifth logic to define a plurality of new data objects from the generated plurality of continuous data streams, each new data object of the plurality of new data objects specifying a plurality of continuous data streams associated with a pair of primary groups of the set of primary groups, sixth logic to incorporate at least one new data object of the pluralit

Abstract: Example devices and methods for compensating for monitoring a surge protection device are provided. In some embodiments, a device is configured to couple to a surge protection device. The device comprises a processor that is capable of sending a DC current signal. A serial data interface is electrically connected to the processor and includes at least one shift register. The device also comprises a multiplexer coupled to the serial data interface. The serial data interface is operable to direct the DC current through the multiplexer. The device also comprises an analog to digital converter (optionally embedded within the processor) that is operable to output a digital signal corresponding to a voltage induced by the DC current signal. Returned DC signals represent surge protection device's health and a multitude of other surge module information.

Abstract: The following coding scenario is addressed: A number of audio source signals need to be transmitted or stored for the purpose of mixing wave field synthesis, multi-channel surround, or stereo signals after decoding the source signals. The proposed technique offers significant coding gain when jointly coding the source signals, compared to separately coding them, even when no redundancy is present between the source signals. This is possible by considering statistical properties of the source signals, the properties of mixing techniques, and spatial hearing. The sum of the source signals is transmitted plus the statistical properties of the source signals which mostly determine the perceptually important spatial cues of the final mixed audio channels. Source signals are recovered at the receiver such that their statistical properties approximate the corresponding properties of the original source signals. Subjective evaluations indicate that high audio quality is achieved by the proposed scheme.

Abstract: Embodiments of the present invention may provide the capability to evaluate logarithm and power (exponentiation) functions using either hardware specific instructions, or a hardware specific implementation with reduced memory requirements. An input comprising a floating point representation of a real number may be received and a mantissa and an exponent may be extracted. A function of a logarithm of a mantissa of the real number may be approximated by utilizing a polynomial based on the mantissa. The approximated function of the logarithm may be combined with the exponent for calculating a value comprising a logarithm of the real number. Likewise, an input comprising a floating point representation of a real number and a representation of a second number may be received and an approximation of the real number to the power of the second number may be generated.

Abstract: A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.

Abstract: The disclosure relates to a device for determining an estimate of the logarithm of an input variable. The device has an approximation unit which is designed to use an approximation to determine from the input variable a first variable that corresponds to the integer component of the logarithmic value of the input variable. The approximation unit is further designed to determine a second variable which corresponds to an estimate of a non-integer component of the logarithmic value of the input variable. The device further comprises a determination unit for determining a correcting quantity by using the second variable; and an assessment unit for assessing the estimate of the logarithm of the input variable by combining the first variable with the second variable and the correcting quantity.

Abstract: A method and device for noise suppression in a data processing device may have input data entered into a storage device and saved as storage data, the storage data may be processed by a data processor and may be output as output data from the storage device. The input data may be scaled with an input scaling value from a scaling device, and the output data may be scaled with an output scaling value from the scaling device. When the input scaling value may be altered, the storage data may also be altered for noise suppression. The storage device and/or the scaling device may be configured and/or actuated such that the storage data may be changed in accordance with a change in the input scaling value. Some or all of the storage data may be changed in accordance with a change in the input scaling value, and upon a change in the input scaling value by a change value the storage data may also be changed with the same change value.

Abstract: A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value.

Abstract: An embodiment includes a method for detecting a potential floating-point error in an addition or a subtraction instruction included in an operation. The method may include identifying a first operand and a second operand. The first operand and the second operand may be configured to be manipulated during execution of the instruction. The method may include copying a first exponent of the first operand to a first comparison register. The method may also include copying a second exponent of the second operand to a second comparison register. The method may further include comparing the first exponent in the first comparison register to the second exponent in the second comparison register. Based on the comparison, a determination may be made whether the instruction includes a potential floating-point error when executing the instruction using the first operand and the second operand formatted according to a first precision.

Abstract: An information retrieval apparatus including a first detecting unit that detects a feeder indicative of a presence of a numerical value in a file subject to retrieval in which a numeral and a character are present together; a second detecting unit that detects a number of places in the numerical value correlated to the feeder detected by the first detecting unit; and a compressing unit that compresses the numerical value into compressed information including a compression code for a numeral indicative of the number of places detected by the second detecting unit and a compression code for a numeral at each place in the numerical value, wherein the numerical value is correlated to the feeder based on an appearance frequency of a numeral included in the file.

Abstract: Data compression using a combination, of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises: determining whether or not a parameter or attribute of data within a data block is identified for the data block wherein the determining is not based solely on a descriptor that is indicative of the parameter or attribute of the data within the data block; and compressing the data block with at least one encoder associated with the parameter or attribute of the data within the data block to provide a compressed data block.

Abstract: Methods, devices and algorithms for the linearization of nonlinear time variant systems and the synchronization of a plurality of such systems. An example of such a system would be a transmit path, including the power amplifier, as used in wireless transmit systems. Advances made in CMOS technology, digital to analog converter (DAC) technology make it possible to implement a substantial part of such a system in the digital domain. Another aspect is the integration of a substantial part of such a transmit system in a single integrated circuit (IC). A digital implementation that allows for linearization of a broad range of nonlinear and time variant effects. Since this digital implementations operate a high clock frequency a energy efficient implementation is essential to keep the power consumption under control. Another aspects is the reuse of methods, devices and algorithms used for the linearization a transmit system to synchronize multiple transmit systems.

Abstract: The transmission of broadcast data, such as financial data and news feeds, is accelerated over a communication channel using data compression and decompression to provide secure transmission and transparent multiplication of communication bandwidth, as well as reduce the latency. Broadcast data may include packets having fields. Encoders associated with particular fields may be selected to compress those particular fields.

Abstract: The transmission of broadcast data, such as financial data and news feeds, is accelerated over a communication channel using data compression and decompression to provide secure transmission and transparent multiplication of communication bandwidth, as well as reduce the latency. Broadcast data may include packets having fields. Encoders associated with particular fields may be selected to compress those particular fields.

Abstract: In one aspect, methods and systems for variable-block length encoding of data, such as an inverted index for a file are disclosed. These methods and systems provide for relatively fast encoding and decoding, while also providing for compact storage. Other aspects include a nearly 1:1 inverted index comprising a position vector and a data store, wherein values that have a unique location mapping are represented directly in the position vector, while for 1:n values (n>1), the position vector can include a pointer, and potentially some portion of information that would typically be stored in the data area, in order to fully use fixed width portions of the position vector (where a maximum pointer size is smaller than a maximum location identifier size).

Abstract: In certain embodiments, a computer system and process for use in a trading system are provided that allow trading entities to compress trade records while simplifying the reconciliation process. Advantageously, compressed trade records are processed by a custodian firm, while uncompressed reconciliation data are processed by a central counterparty. In some embodiments, a computer system and process are provided that allows trading entities to compress trade records across markets. Advantageously, compression across markets provides a larger pool of eligible trade records for compression, increasing the number of compressible trades, and thus reducing fees paid by the trading firm and the amount of data transmitted.

Abstract: Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of an input data stream to identify a data type of the data block, the input data stream comprising a plurality of disparate data types; performing content dependent data compression on the data block, if the data type of the data block is identified; performing content independent data compression on the data block, if the data type of the data block is not identified.

Abstract: The transmission of broadcast data, such as financial data and news feeds, is accelerated over a communication channel using data compression and decompression to provide secure transmission and transparent multiplication of communication bandwidth, as well as reduce latency. Broadcast data may include packets having fields. Encoders associated with particular fields may be selected to compress those particular fields.

Abstract: Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of an input data stream to identify a data type of the block, the input data stream comprising a plurality of disparate data type; performing content dependent data compression on the data block, if the data type of the data block is identified; performing content independent data compression on the data block, if the data type of the data block is not identified.

Abstract: Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of an input data stream to identify a data type of the data block, the input data stream comprising a plurality of disparate data types; performing content dependent data compression on the data block, if the data type of the data block is identified; performing content independent data compression on the data block, if the data type of the data block is not identified.

Abstract: A method compares an input value of the input signal stream with an output value of an integration function of a previous binary value to generate a new binary value based upon the comparison. The method then stores a plurality of successive binary values from the comparing step, and simulates an integration function for a plurality of possible bit sequences of the plurality of successive binary values. Finally, the method determines which sequence results in the smallest error between the input signal stream and the output value of the integration function, and uses the most significant bit of the determined sequence to adjust the integration function. A corresponding apparatus is also provided.

Abstract: A system and method for the on-demand transcoding of media content from a source type to a destination type is provided, wherein the system includes a plurality of transcoders for transcoding from a plurality of source types to a plurality of destination types, and wherein the system receives a transcoding request for media content, fetches the media content in response to the transcoding request, sends the media content to one of the plurality of transcoders based on the source type and destination type, transcodes the media content from the source type to the destination type, thereby generating transcoded media content, and transmits the transcoded media content. The system fetches, sends, and transcodes the media content and transmits the transcoded media content in a pipelined fashion. The system also provides for the publication of media content as a file or stream of digital data, for the archiving of media content, and the caching of transcoded media content to improve system efficiency.

Abstract: An audio signal processor for processing 1-bit signals, comprises an input 40 for receiving a 1-bit signal, means 41, 42 for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n is greater than one, means 43 for determining the absolute value of the n-bit signal, means 46, 51 for producing a dynamics control signal dependent on the said absolute value, means 48 for applying the dynamics control signal to the 1-bit input signal, and means 49 for requantizing the dynamics controlled signal as a 1-bit signal and shaping the noise in the requantized 1-bit signal. Circuits for producing LOG base 2 and the corresponding anti-log are also disclosed.

Abstract: A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper bit-slice is zero, the log signal generator (20) subtracts an offset from at least one parameter to generate a log signal (16); otherwise, the log signal generator (20) interpolates the at least one parameter and a lower bit-slice of the input signal (12) to generate the log signal (16).

Abstract: A method for testing protocol converters is presented, which permits the achievement of a test of all commands, independently of a corresponding test system. A modified protocol converter itself is used for the test. With the help of this method, a test for conversion of data structures can be carried out, of a slow protocol into the corresponding data structures of a fast protocol in the original speed.

Abstract: A method for encoding and decoding digital signals, particularly speech signals, by separating the original signal into a linear and nonlinear portions, the nonlinear portion may have linear aspects. The linear portion is encoded by LPC techniques and the nonlinear portion is encoded by use of a fractal transform. The encoded signal consists of LPC filter coefficients and fractal transform coefficients. The encoded signal is decoded by separating the LPC coefficients and fractal coefficients, using the LPC coefficients to generate an LPC filter, decoding the fractal coefficients using a fractal transform decoding method to obtain an error signal, and exciting the LPC filter with the decoded error signal to obtain decoded digital signals.

Abstract: A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

Abstract: A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, a multiplier, and two adders. The memory stores a plurality of parameters and second-order terms which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of computing the parameters and second-order terms is also disclosed.

Abstract: A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory, a multiplier, and an adder. The memory stores a plurality of parameters which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values.

Abstract: A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper bit-slice is zero, the log signal generator (20) subtracts an offset from at least one parameter to generate a log signal (16); otherwise, the log signal generator (20) interpolates the at least one parameter and a lower bit-slice of the input signal (12) to generate the log signal (16).

Abstract: A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, two multiplier, and two adders. The memory stores a plurality of coefficient which are based on a second-order Taylor polynomial used to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of using the converter is also disclosed.

Abstract: A converter which may be used for implementing either logarithmic or inverse-logarithmic functions includes a memory, a multiplier, and an adder. The memory stores a plurality of pre-computed values which are used in an interpolation to estimate a logarithmic or inverse-logarithmic function over a domain of input signals.

Abstract: A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

Abstract: A logarithm computing circuit for fixed point numbers is disclosed that has: a shift number detection circuit that inputs a number of a fixed point representation, detects a shift number of the inputted number for the purpose of dividing the inputted number into an exponent part and a mantissa part, calculates an exponent part from the shift number and a radix point position of the inputted number, subtracts 1 from the exponent part, and finally outputs the subtraction result as an integer part; a shift circuit that normalizes the inputted number by shifting the inputted number a number of bits equal to the shift number and generates a mantissa part that is equal to or above 0.5 and below 1; and a decimal-part computing circuit that converts the mantissa part to its logarithm to base 2, adds 1 to the conversion result and outputs the result as a decimal part.

Abstract: Data compression is effected on arbitrary high entropy digitized data by compression and entropy transformation in an iterative system. Compression includes nonlinear addressing. Entropy transformation may involve any of a number of techniques to reorder distribution of data for testing to determine if the newly ordered data is compressible. Among the techniques are a merge technique, a swapping technique and various arithmetic modification techniques.

Abstract: A method converts an n-bit floating point number to a logarithmic representation, the number having a first set of bits assigned to a mantissa, and a second set of bits assigned to an exponent. The logarithmic representation has a characteristic and a fraction. The method: (a) sets the characteristic of the logarithm equal to the second set of bits; (b) selects from a logarithm table a first logarithm of a first subset of the first set; (c) selects from the logarithm table a slope of a logarithmic function at the first logarithm; (d) multiplies the slope times a second subset of the first set to obtain an interpolated value; (e) adds the interpolated value to the first logarithm to obtain the fraction; and (f) adds the characteristic and the fraction to obtain the logarithmic representation.

Abstract: In order to mitigate against the multiplicative noise effects caused by known non-linearities in a trellis coded data transmission system, a signal constellation is formed by starting with a base constellation whose number of signal points and whose geometry are selected in accordance with conventional criteria and then warping that constellation by adjusting the positions of its signal points in accordance with a warp function which is the inverse of the known component of the non-linear characteristic of the transmission system. Because the constellation warping is deterministic, it is possible for the receiver to "unwarp" the received signal points prior to applying them to the Viterbi decoder. In preferred embodiments, the trellis code is of a type in which the dominant error event is a trellis path error.

Abstract: An artificial network for encoding the binary on-state of one-out-of-N inputs, say j, when only one state is on at a time wherein the jth on-state is represented by a suitable output level of an N-input MP type neuron operating in the non-saturated region of the neuron output nonlinearity. A single line transmits the encoded amplitude level signal to a decoder having N single input neural networks.

Abstract: A circuit for converting a 8-bit .mu.LawPCM code into a 14-bit linear code comprising an inversion circuit receiving a 8-bit .mu.LawPCM code for outputting a 8-bit inverted signal. A 6-bit signal is obtained by putting a bit of "1" at a place lower than the least significant bit of less significant four bits of the 8-bit inverted signal by one bit and another bit of "1" at a place higher than the most significant bit of the less significant four bits of the 8-bit inverted signal by one bit. The 6-bit signal is shifted by a bit shift circuit in the most significant bit direction by the amount which is within a range of 0 bit to 7 bits and which is determined by second to fourth significant bits of the 8-bit inverted signal.

Abstract: A coding method uses a pseudo-logarithmic compression law approximated by a straight line segment curve. Its code word on n+1 binary digits, where n is a positive invariant integer, has a lefthand part made up of a variable number p of binary digits having the same value (1) corresponding to the rank number of the segment concerned in the compression law and a righthand part, which may be absent, determining the interval within the segment concerned.

Abstract: The present invention provides a high-speed decoder for decoding signals encoded into Nordstrom-Robinson 16,256,6 non-linear code. The novel decoder receives a transmitted encoded signal in the form of a multi-dimensional vector to be decoded. The decoder comprises a plurality of computing elements coupled to the input encoded signals and produces modified multi-dimensional vectors and subcode values which are decoded in a plurality of subcode decoders to produce intermediate inner product values and information words associated with the intermediate inner product values. The intermediate inner product values are compared in comparator means to provide the maximum intermediate inner product value and its associated information which is indicative of the best mathematical estimate of the encoded signal being decoded.

Abstract: A digital level display in which a digital input signal has its highest order non-zero part logarithmically converted by a first decoder and its lower order part logarithmically converted by a second decoder. The outputs of the two decoders are added to be displayed.

Abstract: A 001 conference circuit for a digital communication system in which the analog-to-digital and digital-to-analog converters of at least two subscriber terminal stations have different bandwidth of their processable analog signals or in the code format of the digital signals or in the bit rate of the digital signals. It is not necessary for any conference participant to adapt to the equipment of any one of the other participants because the conference circuit comprises transcoders and corresponding transdecoders of different construction for each conference participant. This anoids the requirement that all conference participants must agree on the same bandwidth, the same code and the same bit rate.When establishing a conference connection, a control circuit actuates the appropriate transcoder and the corresponding transdecoder required for each conference participant.

Abstract: A high speed form of finite precision binary arithmetic coding comprises encoding/decoding performed in the logarithm domain, resulting in facilitated computation based on additions and subtractions rather than multiplications and divisions. In encoding and decoding, antilogs are used which are retrieved from an antilog table. The antilog table is characterized by the following constraints to assure decodability wherein for any two mantissas .alpha. and .beta. representing respective inputs to the antilog table:(a) antilog (.alpha.+.beta.).ltoreq.antilog (.alpha.) * antilog (.beta.); at least when (.alpha.+.beta.) is less than one; and(b) each antilog table output value is to be unique.