Abstract: A hybrid mechanism whereby hardware acceleration is combined with software such that the compression rate achieved is significantly increased while maintaining the original compression ratio (e.g., using full DHT and not SHT or an approximation). The compression acceleration mechanism is applicable to a hardware accelerator tightly coupled with the general purpose processor. The compression task is divided and parallelized between hardware and software wherein each compression task is split into two acceleration requests: a first request that performs SHT encoding using hardware acceleration and provides post-LZ frequency statistics; and a second request that performs SHT decoding and DHT encoding using the DHT generated in software.

Abstract: A method for encoding a non-negative integer, for example, representative of MWD/LWD data, includes encoding at least a portion of the integer using at least a first order Fibonacci derived sequence. The remainder of the integer may be encoded using conventional Fibonacci encoding. The invention tends to improve coding efficiency, downhole and surface synchronization, and surface detection.

Abstract: Disclosed are a Multiple User Multiple Input Multiple Output (MU-MIMO) codebook design method, and a communication device using the codebook. A MU-MIMO codebook design method includes analyzing beam patterns of candidate vectors included in a predetermined candidate codebook, and eliminating at least one of the candidate vectors based on the beam patterns of the candidate vectors to generate the MU-MIMO codebook for a MU-MIMO system being comprised of the remaining vectors.

Abstract: Systems and methods for the encoding of data in a dataset, comprising the storage of the data in an i-th temporary code list (TCL(i)); generating an i-th folder (folder(i)) from the i-th temporary code list (TCL(i)) by replacing each value by an index that refers to the same value in a reference database; generating new temporary codes, using a predetermined formula F that always combines at least two values from the i-th folder (folder(i)), and placing thereof in an (i+1)-th temporary code list (TCL(i+1)); and the recursive repetition of actions b) and c) for subsequent values of i, so long as the (i+1)-th temporary code list (TCL(i+1)) or the (i+1)-th folder (Folder(i+1)) contains one or more values more than once.

Abstract: Method and apparatus for determining an alternative character string, in response to an invalid character string being received by a consumer application, wherein the invalid character string is derived from the selection of a series of keyboard keys in combination with a modifier key and wherein each key is associated with at least one glyph. An embodiment includes: a converter component for converting each glyph of the invalid character string into a first format; a converter component for parsing each of the converted first formats into a second format; an alternatives engine for determining from each of the second formats a third format which can be derived from a combination of a selection of the key and an alternative modifier key; and a converter component for converting each of the determined third formats into their associated glyphs for compiling into a list of alternative character strings.

Abstract: A method for encoding a non-negative integer, for example, representative of MWD/LWD data, includes encoding at least a portion of the integer using at least a first order Fibonacci derived sequence. The remainder of the integer may be encoded using conventional Fibonacci encoding. The invention tends to improve coding efficiency, downhole and surface synchronization, and surface detection.

Abstract: Methods and apparatus are provided for modulation coding a stream of binary input data. A 4-ary enumerative encoding algorithm is applied to the input bit-stream to produce a succession of 4-ary output symbols. The 4-ary algorithm is operative to simultaneously encode respective generalized Fibonacci codes in the odd and even interleaves of the input bit-stream. The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints. Inverting the bits of the 4-ary output symbols produces an output bit-stream with (G, I)-constraints as in the PRML (G, I) codes used in reverse-concatenation modulation systems. Corresponding decoding systems are also provided.

Abstract: Techniques are provided for reducing error propagation in encoded data using Fibonacci modulation codes. The Fibonacci modulation codes have a Fibonacci base with a variable span that limits error propagation. Some of the elements in the Fibonacci base have a larger span than limited span elements in the base. Errors occurring in bit positions of an encoded sequence that correspond to the limited span elements do not propagate to adjacent bytes in the decoded sequence. The Fibonacci modulation codes can also have a relatively high code rate.

Abstract: Embodiments of our invention describe the method for producing forbidden pattern free (FPF) codewords using an encoder-decoder (CODEC). First, the method encodes a dataword to produce a FPF codeword by mapping dataword to a Fibonacci Numeral System space. Further, the FPF codeword is transmitted via adjacent lines of a bus and decoded when received from the bus to recover the dataword to eliminate all crosstalk on the bus.

Abstract: Methods and apparatus are provided for modulation coding a stream of binary input data. A 4-ary enumerative encoding algorithm is applied to the input bit-stream to produce a succession of 4-ary output symbols. The 4-ary algorithm is operative to simultaneously encode respective generalized Fibonacci codes in the odd and even interleaves of the input bit-stream. The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints. Inverting the bits of the 4-ary output symbols produces an output bit-stream with (G, I)-constraints as in the PRML (G, I) codes used in reverse-concatenation modulation systems. Corresponding decoding systems are also provided.

Abstract: Methods and apparatus are provided for partitioning a stream of binary input data into two binary output streams for supply to respective modulation encoders in a modulation coding system. A 4-ary enumerative encoding algorithm is applied to each of a succession of input words in the input bit-stream to produce a succession of 4-ary output symbols from the input word. The 4-ary algorithm simultaneously encodes respective j=? Fibonacci codes in the odd and even interleaves of the input word such that the two bit-sequences formed by respective corresponding bits of the succession of output symbols are range-limited codewords. The two binary output streams are then produced by separating the two range-limited codewords generated from each successive input word. The binary output streams can then be independently encoded by respective modulation encoders, and the encoder outputs interleaved to produce a modulation-constrained output stream. Corresponding decoding systems are also provided.

Abstract: Systems and methods of storing previously transmitted data and using it to reduce bandwidth usage and accelerate future communications are described. By using algorithms to identify long compression history matches, a network device may improve compression efficiently and speed. A network device may also use application specific parsing to improve the length and number of compression history matches. Further, by sharing compression histories, compression history indexes and caches across multiple devices, devices can utilize data previously transmitted to other devices to compress network traffic. Any combination of the systems and methods may be used to efficiently find long matches to stored data, synchronize the storage of previously sent data, and share previously sent data among one or more other devices.

Abstract: Systems and methods of storing previously transmitted data and using it to reduce bandwidth usage and accelerate future communications are described. By using algorithms to identify long compression history matches, a network device may improve compression efficiently and speed. A network device may also use application specific parsing to improve the length and number of compression history matches. Further, by sharing compression histories, compression history indexes and caches across multiple devices, devices can utilize data previously transmitted to other devices to compress network traffic. Any combination of the systems and methods may be used to efficiently find long matches to stored data, synchronize the storage of previously sent data, and share previously sent data among one or more other devices.

Abstract: An efficient data-directed scrambler is provided for processing digital signals having an unequally-weighted code. The data-directed scrambler includes inputs for receiving unequally-weighted bits of an input signal, outputs for supplying N scrambled bits of an output signal, and two or more scrambler columns connected in series between the inputs and the outputs. One or more of the scrambler columns includes a swapper cell and a digital fanout. Least significant bits in the unequally-weighted code are input to a swapper cell, and higher order bits in the unequally-weighted code are input to respective digital fanouts. In the other embodiments, an efficient data-directed scrambler is provided for processing digital signals having an equally-weighted code.

Abstract: The design of communication and storage systems requires a choice of modulation and coding. In conventional storage and communication systems, the commonly used modulation scheme is called Non Return to Zero (NRZ) and the commonly used codes are called Run Length Limited (RLL) codes. The disclosure describes a new modulation scheme that can be used to increase the data transmission rate or storage density. The disclosure also describes codes that are referred to as Interval Modulation Codes, which can be used to transmit or store information efficiently using the new modulation scheme. Also described are procedures for determining if there exist suitable Interval Modulation Codes, given predetermined parameters that describe their desired performance. The disclosure also describes procedures or algorithms for constructing optimal Interval Modulation Codes given a set of parameters that describe their performance. The described techniques can be used in different communication (e.g.

Abstract: Non-uniform modulation encoding techniques are provided to prevent data from containing bit patterns that are prone to errors during read back. Modulation encoding is performed on a data stream to remove error prone bit patterns. Unconstrained data, such as error check parity, that is inserted into the modulated data stream may contain error prone bit patterns. Stricter modulation constraints are enforced on bits that are next to the unconstrained data, than on the remaining bits. By enforcing stricter modulation constraints on these bits, an entire data bit stream can have a desired modulation constraint.

Abstract: Techniques are provided for applying modulation constraints to data streams using a short block encoder. A short block encoder encodes a subset of the bits in a data stream. Then, the even and odd interleaves in a data stream are separated into two data paths. A first modulation encoder encodes the even interleave according to a first modulation constraint. A second modulation encoder encodes the odd interleave according to a second modulation constraint, which in general coincides with the modulation constraint for even interleave.

Abstract: A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.

Abstract: An efficient bit interleaving scheme for a multi-band OFDM ultra-wideband (UWB) system. The encoded bits of the multi-band OFDM system are interleaved within each OFDM symbol and across OFDM symbols. The bit interleaving scheme minimizes performance degradation due to groups of contiguous OFDM tones experiencing a poor SNR caused by the frequency selective channel, exploits the frequency diversity across sub-bands, randomizes the effect of co-channel interference from simultaneously operating un-coordinated piconets, and randomizes the impact of generic narrow-band interferers present within the UWB spectrum.

Abstract: A method and apparatus for a state-driven decoder for decoding a Manchester encoded signal. The decoder comprises an input sampling stage, an over-sampling clock, and a digital logic state machine. The over-sampling clock operates at a frequency which is less than five times the data rate of the encoded signal. The input sampling stage asynchronously samples the encoded signal at the frequency of the over-sampling clock and a produces a stream of pulse samples. The digital logic state machine analyzes the stream of pulse samples in groups and based on the logic levels of each group of pulse samples generates an output bit corresponding to the decoded Manchester signal.

Abstract: The present invention discloses a mathematical technique which finds substantial utility in electrical engineering, particularly in the general field of data transformation, which occurs in applications such as data encryption and data compression. The technique uses a commencement matrix to transform a first number of a sequence of numbers. This initial transformation forms a forward resultant matrix. Successive transformation of succeeding numbers in the sequence produces for each number in the sequence an augmented forward resultant matrix. Each augmented forward resultant matrix is used to transform the next succeeding number of the sequence, and so on. A final transformed sequence is generated from the final form of the augmented forward resultant matrix.

Abstract: Encoding arrangement for encoding a sequence of (n-1)bit information words into a sequence of n-bit channel words, and a decoding arrangement for decoding a sequence of n-bit channel words into a sequence of (n-1)-bit information words. The encoding arrangement comprises input means for receiving the information words, converter means for converting the (n-1)-bit information words into n-bit channel words and output means for supplying the channel words. The converter means comprises weight vector coefficient supply means for supplying a weight vector w, the weight vector having n weight vector coefficients w.sub.i, where i is an integer running from 1 to n and the weight vector coefficients being in the form of (n-1)-bit binary words, and calculation means for carrying out a calculation using an information word so as to obtain a channel word. The weight vector coefficient supply means is adapted to supply only p bits of a weight vector coefficient w.sub.

Abstract: A novel method of adapting Fibonacci number weighting to raw binary code data of variable length to use the code as a fixed length code by using only those code sequences with a fixed number of cells rather than a fixed number of bits, converting the code to a continuous numerical sequence useful particularly for linear media and data transmission. Encoder and decoder systems useful to enable storing or recording and reading or utilization of the Fibonacci code in bar code, magnetic and other media.