Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

Abstract: Embodiments of the present disclosure relate to a display device and a driving method thereof, and the display device includes a demultiplexer connected to a first data line and transferring a data signal from the first data line to a plurality of second data lines during a data writing period of one frame, a compensator calculating an on-pixel ratio (OPR) using input data in the one frame and generating compensation data corresponding to a calculated OPR, and a data driver supplying the data signal to the first data line using the input data during the data writing period, and supplying a compensation data signal to the first data line using the compensation data in a blank period of the one frame, and the demultiplexer supplies the compensation data signal from the first data line to a second data line during the blank period.

Abstract: The present disclosure provides a method, apparatus, and measurement device for measuring distortion parameters of a display device, and a computer-readable medium. The display device includes a display screen and a lens located on a light exiting side of the display screen, and the method includes: acquiring a distortion image which is generated by imaging an initial image through the lens, wherein the initial image is an image displayed on the display screen, the initial image comprises a plurality of first corner points, and the distortion image comprises a plurality of second corner points which match the plurality of first corner points respectively; and determining the distortion parameters of the display device according to a locational relationship between the second corner points and a first corner points which match the second corner points.

Abstract: Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU.

Abstract: The technology described herein provides for indexing information in a bit vector search index. The bit vector search index comprises a data structure for indexing data about terms from a corpus of documents. The data structure includes a number of bit vectors. Each bit vector comprises an array of bits and corresponds to a different set of terms. Bits in the bit vector are used to represent whether at least one document corresponding to the bit includes at least one term from the set of terms corresponding to the bit vector. The bit vector search index is stored by first indexing information about documents using bit vectors on a first accumulation buffer storage device. When a threshold is satisfied, the information is transferred to bit vectors on a subsequent storage device.

Abstract: A memory control device of the present invention comprises a reset control section (32) for (i) suspending, at a time point where rp overtakes wp or wp overtakes rp or a time point immediately before that time point, a reading operation of data, and (ii) conducting again, at a predetermined time point where reading is to be resumed, the reading operation of the data from a position at which the reading operation has been started in a frame memory (31).

Abstract: Provided is a motor control system of a numerical controller that can instruct a plurality of motors and display data on a display device by means of a single serial bus. An amplifier which controls the motor drives the motor based on a motor command received from the numerical controller via the serial bus. The display device display data on a screen based on display data received from the numerical controller via the serial bus.

Abstract: Sequential fetch requests from a set of fetch requests are combined into longer coalesced requests that match the width of a system memory interface in order to improve memory access efficiency for reading the data specified by the fetch requests. The fetch requests may be of different classes and each data class is coalesced separately, even when intervening fetch requests are of a different class. Data read from memory is ordered according to the order of the set of fetch requests to produce an instruction stream that includes the fetch requests for the different classes.

Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs.

Abstract: A display driver integrated circuit which includes a distributor configured to output display data; a plurality of first-in first-out (FIFO) memories configured to receive the display data from the distributor according to an external clock and output the display data in response to an internal clock; and a plurality of graphics memories configured to receive the display data from the FIFO memories.

Abstract: Systems and methods of adjusting a frequency of a graphics controller may include a logic to determine a metric associated with an input/output (I/O) queue. The metric may be used to determine whether an I/O limited condition exists. The I/O limited condition may be associated with a graphics controller. There may be a logic to cause a frequency of the graphics controller to be decreased when the I/O limited condition exists, and a logic to cause the frequency of the graphics controller to be increased when the I/O limited condition does not exist. The I/O limited condition may exist when a magnitude of the metric is equal to or greater than a first threshold. The I/O limited condition may not exist when the magnitude of the metric is equal to or less than a second threshold.

Abstract: Some examples determine when to accumulate updates to a display device. In some implementations, a display manager may determine that a graphical user interface element, such as a user interface window, has opened or closed. The display manager may accumulate updates to a display device for a period of time or until a predetermined number of the updates have been received. After the period of time has elapsed or after the predetermined number of the updates have been received, the display manager may send a single update to the display device. The single update may include or may be equivalent to the one or more updates.

Abstract: An image processing method for processing an input image is provided. The image processing method includes: performing a plurality of first imaging processing operations on the input image to generate a first image; and performing a plurality of second imaging processing operations on the first image. Each of the first imaging processing operations is along a first direction, and the plurality of first imaging processing operations include a first scaling operation for increasing resolution. Each of the second imaging processing operations is along a second direction different from the first direction, and the plurality of second imaging processing operations include a second scaling operation for increasing resolution.

Abstract: An object is to provide an image processing circuit adaptable to displays having a variety of pixel numbers. The image processing circuit includes a data adjustment circuit, a first line memory and a second line memory capable of storing K pieces of data, an output timing control circuit, and an arithmetic circuit. To the data adjustment circuit, (X×Y) pieces of pixel data are input. Y pieces of pixel data are transmitted to the first line memory. When Y is less than K, (K?Y) pieces of dummy data are added to fill the first line memory. Then, the K pieces of data are output from the first line memory to the second line memory and a new set of K data is input to the first line memory. The arithmetic circuit stores the data input from the line memories and performs filtering.

Abstract: A technique for encoding and decoding video information uses a plurality of video processing modules (VPMs), whereby each video processing module is dedicated to a particular video processing function, such as filtering, matrix arithmetic operations, and the like. Information is transferred between the video processing modules using a set of first-in first-out (FIFO) buffers. For example, to transfer pixel information from a first VPM to a second VPM, the first VPM stores the pixel information at the head of a FIFO buffer, while the second VPM retrieves information from the tail of the FIFO buffer. The FIFO buffer thus permits transfer of information between the VPMs without storage of the information to a cache or other techniques that can reduce video processing speed.

Abstract: A method and apparatus is provided for providing local screen data of a source device, such as a personal computer, to a sink device, such as a television, game console, or home theatre system, at a rate determined by the sink device. In one example, the method and apparatus responds to requests from the sink device to provide local screen data by serving the local screen data to the sink device from a circular buffer. The local screen data is written to the circular buffer in FIFO order based on the requests from the sink device, and read from the circular buffer based on the requests.

Abstract: An image processing circuit and a method thereof are provided herein. The image processing circuit has a first scaling circuit, one or more line buffers, a first sharpness circuit, a second scaling circuit, and a second sharpness circuit. The first scaling circuit enlarges an input image along a first direction to generate a first enlarged image. The one or more line buffers temporarily store the pixel values of a plurality of pixel rows of the first enlarged image. The first sharpness circuit vertically sharpens the first enlarged image to generate a first sharpened image. The second scaling circuit enlarges the first sharpened image along a second direction to generate a second enlarged image. The second sharpness circuit horizontally sharpens the second enlarged image to generate a second sharpened image. Accordingly, it is possible to use the one or more line buffers having shorter data lengths to perform the vertical sharpening.

Abstract: A method for performing an operation using more than one resource may include several steps: requesting an operation performed by a resource; populating a ring frame with an indirect buffer command packet corresponding to the operation using a method that may include for the resource requested to perform the operation, creating a semaphore object with a resource identifier and timestamp, in the event that the resource is found to be unavailable; inserting a command packet (wait) into the ring frame, wherein the command packet (wait) corresponds to the semaphore object; and submitting the ring frame to the graphics engine.

Abstract: Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO's are arranged in coordination with serial processing units, such as in a pipeline processing environment. The multiple FIFO's contain pointers to entry addresses in a common buffer. Each subsequent FIFO receives only pointers that correspond to data that has not been rejected by the corresponding processing unit. Rejected pointers are moved to a free list for reallocation to later data.

Abstract: A multi-graphics processor system includes a CPU; a first GPU connected to the CPU via an input/output interface; and a second GPU connected to the first GPU via a second-GPU interface. The first GPU is provided with a second-GPU bus for communicating the CPU and the second GPU via the second-GPU interface. The CPU communicates with the second GPU via the second-GPU bus after receiving a signal indicating the timing of the data communication.

Abstract: In a digital video processing system for processing full-motion video in computer terminal systems, two main rendering paths are created for a computer terminal system: a screen buffer path and a full-motion video path. The screen buffer path renders a desktop display from a screen buffer within the terminal system. The full-motion video path decodes a video stream and then processes the decoded video stream with a video processing pipeline to fit the video frames within a destination video window within the desktop display. The video processing pipeline performs clipping, blending, chroma resampling, resizing, and color converting of the video frames in pipelined stages with minimal memory accesses. A video adapter then combines the desktop display with the processed digital video for a final terminal display.

Abstract: A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.

Abstract: A method, apparatus, system and medium for reading data from a tiled memory. In some embodiments a method may, include for one tiled-X cache read request, requesting two cache lines from the tiled memory without fragmenting the tiled-X cache read request, and returning data associated with the two requested cache lines.

Abstract: A display controller is provided. The display controller includes an external memory and a timing controller which compresses current frame data to generate front first in-first out (FIFO) input data, temporarily stores the front FIFO input data and writes the front FIFO input data to the external memory in a burst mode, and reads data from the external memory in the burst mode, temporarily stores the read data as back FIFO output data, and decodes the back FIFO output data to output previous frame data.

Abstract: An image processing circuit and a method thereof are provided herein. The image processing circuit has a first scaling circuit, a plurality of line buffers, a first sharpness circuit, a second scaling circuit, and a second sharpness circuit. The first scaling circuit enlarges an input image along a first direction to generate a first enlarged image. The line buffers temporarily store the pixel values of a plurality of pixel rows of the first enlarged image. The first sharpness circuit vertically sharpens the first enlarged image to generate a first sharpened image. The second scaling circuit enlarges the first sharpened image along a second direction to generate a second enlarged image. The second sharpness circuit horizontally sharpens the second enlarged image to generate a second sharpened image. Accordingly, it is possible to use the line buffers having shorter data lengths to perform the vertical sharpening.

Abstract: A display interface buffer includes a general purpose memory to store data capable of being displayed on a panel, a plurality of display drivers to receive data from the general purpose memory, each of the display drivers to drive a different portion of the panel with the data, and processor or a direct memory access controller to access data in the general purpose memory and to provide the data to the display drivers for presentation on the panel.

Abstract: Systems and methods for improving throughput of a graphics processing unit are disclosed. In one embodiment, a system includes a multithreaded execution unit capable of processing requests to access a constant cache, a vertex attribute cache, at least one common register file, and an execution unit data path substantially simultaneously.

Abstract: A method for processing an incoming command destined for a target is provided, comprising: determining if the incoming command is a data command or a management command; forwarding the incoming command to a storage management component of the target when the incoming command is a management command; when the incoming command is a data command: determining if a disk command queue on the target is full; sending the incoming command to the disk command queue when the disk command queue is not full; when the disk command queue is full: starting a timer, the timer having a predetermined length; sending the incoming command to the disk command queue when the disk command queue becomes not full prior to the expiration of the timer; and sending a rejection of the incoming command to the host only if, upon expiration of the timer, if the disk command queue is still full.

Abstract: A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

Abstract: Methods, systems, and apparatuses, including computer programs encoded on a computer storage medium, for rendering application content are disclosed. In one embodiment a content receiver receives application content for rendering on a display unit of a computing device. A first processing unit renders the application content onto a first frame of a plurality of frames, and a second processing unit sequentially renders the plurality of frames onto the display unit. A counter counts of a number of outstanding frames as provided by the first processing unit to the second processing unit relative to corresponding acknowledgement messages indicating that one of the outstanding frames has been rendered onto the display unit. If the count is less than a threshold, the first processing unit renders the application content onto the first frame, otherwise the first processing unit waits to render the application content until the count is less than the threshold.

Abstract: A method and apparatus is provided for providing local screen data of a source device, such as a personal computer, to a sink device, such as a television, game console, or home theatre system, at a rate determined by the sink device. In one example, the method and apparatus responds to requests from the sink device to provide local screen data by serving the local screen data to the sink device from a circular buffer. The local screen data is written to the circular buffer in FIFO order based on the requests from the sink device, and read from the circular buffer based on the requests.

Abstract: A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller including an input memory which receives pixel data and transmits the pixel data through a main route and a secondary route; wherein pixel data is transmitted through the main route and is processed for delivery to the display in a predetermined manner; characterized in that the secondary route comprises a memory for storing a two-dimensional section of the pixel data that corresponds at least in part to the pixel data being transmitted through the main route at that time; further characterized in that the display controller includes a detector for identifying a data feed latency event and in response there to switching the transmission of the pixel data to the secondary route and processing the pixel data through secondary route for delivery to the display such that when a data feed latency event occurs the stored two-dimensional section of the pixel data from the secondar

Abstract: A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.

Abstract: The invention relates to data accessing method and apparatus, and more particularly to data accessing method and apparatus for accessing a first-in first-out (FIFO) buffer compatible with mini-low voltage differential signal (mini-LVDS) transmission interface. The image data accessing apparatus comprises a FIFO memory for storing the image data, and a controller for accessing the FIFO memory in circular manner; wherein the controller writes the image data in pixel-basis and reads the stored image data in channel-basis.

Abstract: A method includes fetching first synthesized pixels from an update buffer of a memory and fetching data pixels from an image buffer of the memory during the first drive frame period. Respective data pixels are fetched synchronously with the fetching of corresponding first synthesized pixels. Respective data pixels fetched from the image buffer are synthesized with corresponding first synthesized pixels to generate second synthesized pixels. The second synthesized pixels are stored in the update buffer during the first drive frame period. The storing of second synthesized pixels may be paused based on a prediction that the fetching of first synthesized pixels will not complete within the first drive frame period. The fetching of data pixels from the image buffer of the memory may also be paused based on the prediction that the fetching of first synthesized pixels will not complete within the first drive frame period.

Abstract: Systems and methods for determining a compression tag state prior to memory client arbitration may reduce the latency for memory accesses. A compression tag is associated with each portion of a surface stored in memory and indicates whether or not the data stored in each portion is compressed or not. A client uses the compression tags to construct memory access requests and the size of each request is based on whether or not the portion of the surface to be accessed is compressed or not. When multiple clients access the same surface the compression tag reads are interlocked with the pending memory access requests to ensure that the compression tags provided to each client are accurate. This mechanism allows for memory bandwidth optimizations including reordering memory access requests for efficient access.

Abstract: Rate matching for use in data links between a source device and a sink device is provided. A rate matching device includes a first-in-first-out (FIFO) buffer having a write pointer and a read pointer; a write control having a write clock to write an input data stream from the source device onto the FIFO buffer using the write pointer; a read control having a read clock to read data from the FIFO buffer using a read pointer, insert data to an output data stream and transmitting the data stream to the sink device; a processor to provide a bit number based on the write clock period and the read clock period, wherein the read control inserts blanking data into the output data stream while the read pointer is stopped in the FIFO buffer to allow the write pointer to move ahead by the bit number provided by the processor. Some embodiments are thus able to avoid buffer overflow or underflow scenarios.

Abstract: Provided is a register circuit including a timing circuit controlled by an external control signal to receive an external timing signal and then to transmit a first timing signal and a second timing signal, wherein the first timing signal and the second timing signal have phases inverse to each other; two pass gates controlled by the first timing signal and the second timing signal to receive starting pulse signals and then transmit the pulse signals as one of the pass gates turns on; a signal output unit receiving the pulse signals to transmit an output signal; and two switches controlled by the external control signal to receive and to transmit the output signal as one of the switches turns on.

Abstract: Provided are a system for compensating response speed and a method of controlling frame data of an image. The system includes: a circuit for compensating response speed; an internal frame memory that comprises N sub frame memories formed in a single chip with the circuit for compensating response speed, wherein N is a natural number; a frame memory controller that comprises N sub frame memory controllers corresponding to each sub frame memory; and a data flow controller that comprises N write first-in-first-out (FIFO) circuits and N read FIFO circuits corresponding to each sub frame memory.

Abstract: Certain aspects of a system and method for handling video data may comprise determining data rates associated with each of a plurality of destination devices utilized for processing video data in a video processing system that supports multiple display data rates. A data rate associated with a first portion of the plurality of destination devices may be adjusted to match at least one data rate associated with one or more of a remaining portion of the plurality of destination devices in instances where the determined data rate of the first portion of the plurality of destination devices is greater than one or more data rate associated with one or more of the remaining portion of the plurality of destination devices.

Abstract: In devices in which display data is read from a memory for display, display underflow in a processing block is alleviated by controlling a clock frequency driving the processing block. Stages of the processing block send underflow detection signals to underflow prevention logic. The underflow prevention logic controls the frequencies of clock signals generated by a clock generator to alleviate the underflow condition.

Abstract: A system for processing a television (TV) picture-out-picture (POP) includes a line buffer, a first multiplexer, an image processing engine, a scaling engine and a timing generator. The line buffer receives partial pixels of a first picture and partial pixels of a second picture. The first multiplexer selects the partial pixels of the first and second picture as an output. The image processing engine performs an image processing on the partial pixels output by the first multiplexer to thereby produce processed pixels. The scaling engine performs a scaling operation on the processed pixels to thereby produce scaled pixels. The timing generator produces a timing signal for the image processing engine and the scaling engine and produces enable signals respectively for the first picture and the second picture. The image processing engine and the scaling engine process the partial pixels of the first or second picture in multiplexing.

Abstract: An image processing apparatus processes compression encoded data of a moving picture and outputs image data divided into a plurality of frames for displaying of the moving picture on a display device. A host CPU outputs a decoding command and a drawing command separately from each other. The decoding process on the compression encoded data can be performed in an independent manner from the drawing process of reflecting the image data, which are the decoding results, on the display object. At this time, a display control section executes the drawing process based on the image data stored in a ring buffer in accordance with the drawing command. Therefore, the host CPU can freely control timings at which the moving pictures are displayed on the display device.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: Embodiments of the invention provide a method for extending a graphics rendering framework. A rendering application locates a first file that includes a first implementation involving a first graphics material and compares data associated with the first file to data associated with a second file that includes a second implementation involving a second graphics material. The rendering application compares data associated with the first and second files, determines that the first graphics material matches the second graphics material, and determines that the first implementation is different from the second implementation. The data associated with the first file and the data associated with the second file are then combined into a data structure.

Abstract: An electronic device is disclosed. The electronic device comprises a transmitter, a converter, and a receiver. The transmitter transmits data and a control signal. The converter receives the control signal from the transmitter and converts the control signal. The receiver receives the data from the transmitter via a data bus isolated from the converter and receives the converted control signal from the converter. The data transmitted from the transmitter is directly electrically connected to the receiver.

Abstract: A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

Abstract: A system and method for processing graphics data which requires less read and write bandwidth. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory while reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to a bank of memory. The processing pipeline concurrently processes an amount of graphics data at least equal to that included in a page of memory. A third bank of memory is precharged concurrently with writing data to the first bank and reading data from the second bank in preparation for access when reading data from the second bank of memory is completed.