Abstract: A receiving apparatus is provided, including: a receiving unit to receive a plurality of pulses including a synchronization pulse and a data pulse having a data pulse width corresponding to a data value; a searching unit to search for pulse information indicating a pulse period or the like that falls within a synchronization pulse acceptable range from among pulse information indicating pulse periods or pulse widths of the respective pulses; a detecting unit to detect whether pulse information of a second pulse at a predetermined location relative to a first pulse corresponding to the searched pulse information indicates a pulse period or the like that falls within a data pulse acceptable range; an identifying unit to identify the first pulse as the synchronization pulse on condition that the pulse information of the second pulse indicates a pulse period or the like that falls within the data pulse acceptable range.

Abstract: A wireless transmit/receive unit (WTRU) is configured to receive a reference signal of a first type. The reference signal of the first type is other than a cell specific reference signal (CRS), an Multicast Broadcast Single Frequency Network (MBSFN) reference signal or a demodulation reference signal (DM-RS). Reference signals of the first type are received in resource elements other than resource elements used for a physical broadcast channel (PBCH), a primary synchronization signal or a secondary synchronization signal. The WTRU is configured to receive a radio resource control message indicating a subframe position in which the reference signal of the first type is transmitted and a periodicity of a transmission of the reference signal of the first type, and a number of antenna ports for a transmission of the reference signal of the first type.

Abstract: A content management system streams variable length segments of content items to client devices. The content management system stores a content item and makes the item available for access by one or more client devices. When a client device requests the content item from the content management system, the content management system sends the content item to the device by streaming the content item in segments. Specifically, the content management system partitions the content item into a sequence of variable length segments. An initial portion of the sequence includes rapid start segments that are configured as being the smallest segments in length from the sequence. A subsequent portion of the sequence includes the remaining segments having longer length(s). The content management system streams the segments to the client device in sequential order and in a streaming format.

Abstract: The embodiment of the present disclosure discloses a touch display device and a driving method thereof, relates to the display technical field, and can extend the time for the touch display device to perform touch control. The touch display device includes n rows of pixels and divides the n rows of pixels into several display regions, wherein n is a natural number greater than 1, the driving method of the touch display device comprising: after the touch display device sends a display signal to the ith row of pixels, and before the touch display device sends a display signal to the (i+1)th row of pixels, sending a touch control signal, by the touch display device, to perform touch control on one display region thereamong, wherein 1?i<n.

Abstract: A system for analyzing hardware of a turbine controller includes a user interface to receive a user input. The system further includes a turbine controller analysis assembly configured to generate a representation of information corresponding to devices and signals of the turbine controller based on receiving a first query from the user interface and a turbine controller selection from the user interface. The turbine controller analysis assembly is further configured to generate a representation of a bill of materials to modify the turbine controller with a first turbine controller modification module based on receiving from the user interface a first data module selection signal corresponding to the first turbine controller modification module.

Abstract: A system transmits video content from a single video source or multiple independent video sources by transmitting at least one data information segment (DIS) followed by a plurality of video data information segments (VDIS). Each DIS includes information that corresponds to a video source and to the plurality of VDIS transmitted subsequently. A receiver system receives at least one DIS followed by a plurality of VDIS, and processes the received VDIS in accordance with the information in the received DIS. The receiver system stores processed video content of the processed VDIS into a memory queue, and a separate memory queue is used for each video source. A display interface receives and processes video content of each memory queue to generate video pixels of a respective output image in accordance with preselected preferences, e.g., corresponding video source, video format, resolution, and/or starting location of the respective output image.

Abstract: A system and process is provided in which original video or dialog content is securely received from the content owner. Subtitle language data is derived, translated, stored and served on a separate database for synchronous playback with the content in video streaming, downloading or online TV following the activation of an option by the end user through a media player.

Abstract: Methods and apparatus for processing and displaying caption information associated with a video program are provided. The caption information is extracted from a video signal and different captions are rendered in sequence for different segments of the video program. A plurality of the different captions is blended in a form for simultaneous display superimposed on video images during one of the different segments of the video program. The different captions may be the latest caption corresponding to the current segment of video and a previous caption corresponding to a previous video segment. These different captions can be displayed such that they overlie each other and such that their opacity is different. In this manner, a viewer is able to have a prolonged period of time to read captions and can readily distinguish the current caption from the previous caption.

Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.

Abstract: A video input section acquires a video signal formed of a plurality of frames. A frame separator separates the video signal acquired by the video input section on a frame basis and distributes the separated video signals. A plurality of parallel processors perform video processing in parallel on the separated video signals corresponding to the frames separated and distributed by the frame separator. A frame combiner combines the separated video signals on which the plurality of parallel processors have performed the video processing.

Abstract: A method and receiving device are provided that determine a synchronization byte in a plurality of transport stream packets, wherein the synchronization byte has a predetermined synchronization value. The method/receiving device receives, via a receiver, a portion of a first transport stream packet of the plurality of transport stream packets; detects, starting from the beginning of the portion of a first transport stream packet, a continuous four byte pattern that does not include the predetermined synchronization value; detects a first occurrence of a byte having the predetermined synchronization value; detects a subsequent byte separated from the first occurrence by a predetermined byte length; determines a byte value of the subsequent byte; and validates that the first occurrence is the synchronization byte based on a comparison of the byte value and the predetermined synchronization value.

Abstract: A signal transmission apparatus includes: a vertical rectangular region sampling-out control section that obtains vertical rectangular regions, repeatedly performs a process where pixel samples read out from each line of class images are mapped to each line of video data regions of sub-images, maps pixel samples to each line of the video data regions, and repeatedly maps pixel samples to the next line; a line sampling-out control section that samples out the pixel samples every other line from each line of the sub-images to which the pixel samples have been mapped, so as to generate an interlace signal; a word sampling-out control section that samples out for each word the pixel samples which have been sampled out for each line so as to be mapped to video data regions of an HD-SDI prescribed by the SMPTE 435-2; and a readout control section that outputs the HD-SDI.

Abstract: Methods, devices, systems and computer programs facilitate presentation of a second content in synchronization with a first content. In one method, at least a portion of a first content that is being presented by a first device is received at a second device. The first content includes substantially imperceptible watermarks that are embedded in one or more components of the first content. A first watermark detection result is obtained by performing a watermark detection operation. Additionally, a second watermark detection result associated with the first content is received at the second device from a device other than the second device. The first watermark detection result and the second watermark detection result are augmented to obtain a combined watermark detection result, and the combined detection result is used to enable presentation of a second content in synchronization with the first content.

Abstract: According to one embodiment, an electronic device includes a reproduction controller and a transmitter. The reproduction controller is configured to reproduce a first type of information of a first content. The first content includes a plurality of types of information. The transmitter is configured to transmit an instruction to reproduce a second type of information of the first content to other electronic device.

Abstract: A wireless video/audio transmission system includes a transmitter configured to wirelessly transmit video/audio data streams The transmitter has an encoder module for generating the data streams including video data, audio data, and timing information. The video data includes only I-frames. The transmission system includes a receiver with a decoder module including a decoder IC, an SRAM, and a PLL circuit. The decoder IC detects the timing information, adjusts the PLL circuit to synchronize with a reference frequency, and decodes the data streams using the SRAM. Alternatively, the receiver includes a decoder module with a decoder IC and an SRAM. The decoder IC detects the timing information, generates a beacon pulse to be transmitted wirelessly to the encoder module, and the encoder module receives the beacon pulse, adjusts the PLL circuit incorporated within the encoder module accordingly so as to synchronize with the decoder module.

Abstract: There is disclosed a stream data reception/reproduction device capable of suppressing deterioration of quality of stream data reproduced even when the stream data is received via an IP network or the like in which the packet arrival timing and the order are not guaranteed. In this device, a reproduction speed control unit (107) sets various conditions in accordance with the value of the synchronization difference reported from a synchronization difference calculation unit (102). Only when the set conditions are satisfied, the speed of reproduction of a frame decompressed and inputted from a decoding unit (105) is adjusted. The reproduction speed control unit (107) interpolates a predetermined amount of sample data into the frame or decimates it from the frame when adjusting the reproduction speed.

Abstract: Stereographic glasses includes reception-stop timing control means that is so arranged as to: (i) cause a wireless-signal receiving section to stop receiving signals, after a cycle detection section detects a cycle of synchronous signals and a liquid crystal shutter control data memory section stores liquid crystal shutter control data therein signals; (ii) cause a liquid crystal shutter control signal timing generation section to generate timings for controlling opening and closing of liquid crystal shutters, based on cycle signals generated by a cycle signal generation section and the liquid crystal shutter control data stored in the liquid crystal shutter control data memory section; and (iii) cause a liquid crystal shutter control section to open and close the liquid crystal shutters, at the timings thus generated.

Abstract: Provided is an OFDM receiver which extracts a time sync signal from a prefix having a symmetric structure. The OFDM receiver, according to exemplary embodiments of the present invention, generates the sync signal (e.g., start point) of a symbol by using only the MSB (e.g., sign bit) of the cyclic prefix of an OFDM symbol, reducing the overhead of a logic circuit for generating the sync signal of the symbol.

Abstract: The present invention provides a system and method for automatically controlling the phase of the clock signal for sampling an HDTV signal, which implements a new and improved method for phase detection. The system and method utilize the standard format of an HDTV signal to consistently ensure accurate phase detection. Particularly, the system and method detect the target phase for the sampling clock using a tri-level sync pattern that exists at the beginning of each display line. This tri-level sync pattern or “sync pulse” is well suited for phase detection since it includes several static areas separated by substantial transitions. Furthermore, by using the sync pulse of the HDTV signal, the system and method provide consistent and accurate results, since the sync pulse will not change regardless of the whether the video data is static or in motion.

Abstract: A horizontal synchronization signal detection system includes a coarse period estimator and a fine period time estimator. The coarse period estimator estimates a minimum value and corresponding position of each period of a CVBS signal to calculate a coarse period of a horizontal synchronization signal. The fine period time estimator divides the horizontal synchronization signal into a first part and a second part so as to generate a first sum and a second sum by adding signals of the first part and the second part, and detects a middle point of the horizontal synchronization signal when the first sum equals the second sum. The steps of fine-tuning the coarse period to generate a fine-tuned coarse period, extracting the horizontal synchronization signal according to the fine-tuned coarse period, and determining whether the first sum is equal to the second sum are repeatedly executed until the first sum equals the second sum.

Abstract: A receiving apparatus includes a first receiving unit that receives signaling information and a first signal comprising reference data through a radio frequency broadcast network; a control unit that detects a plurality of additional data source information from the signaling information; a second receiving unit that accesses an internet protocol communication network, and receives a second signal comprising additional data from a source apparatus corresponding to each of the plurality of additional data source information; a storage unit that stores the reference data contained in the first signal and the additional data contained in the second signal; and an output unit that processes, synchronizes and outputs each of the reference data and additional data.

Abstract: A device for extracting a synchronization signal from a video signal has a first comparator and an adjustment circuit. The first comparator receives the video signal, compares the video signal with a first threshold, and generates the synchronization signal according to the compared result. The adjustment circuit receives the video signal, compares the video signal with a plurality of second thresholds of different values, and changes the first threshold according to the compared results.

Abstract: An endoscopic image processing apparatus includes an endoscope information reading section that reads endoscope information that is information relating to an endoscope from the endoscope, a synchronizing signal detecting section that is given an image pickup signal that includes a synchronizing signal outputted by an image pickup device provided in the endoscope from the endoscope, performs detection processing of the synchronizing signal, outputs the detected synchronizing signal when the synchronizing signal can be detected, and generates and outputs a synchronizing signal based on the endoscope information read by the endoscope information reading section when the synchronizing signal cannot be detected, and an image signal generating section that generates an image signal based on the synchronizing signal outputted from the synchronizing signal detecting section and the image pickup signal outputted from the image pickup device of the endoscope.

Abstract: A method and receiving device are provided that determine a synchronization byte in a plurality of transport stream packets, wherein the synchronization byte has a predetermined synchronization value. The method/receiving device receives, via a receiver, a portion of a first transport stream packet of the plurality of transport stream packets; detects, starting from the beginning of the portion of a first transport stream packet, a continuous four byte pattern that does not include the predetermined synchronization value; detects a first occurrence of a byte having the predetermined synchronization value; detects a subsequent byte separated from the first occurrence by a predetermined byte length; determines a byte value of the subsequent byte; and validates that the first occurrence is the synchronization byte based on a comparison of the byte value and the predetermined synchronization value.

Abstract: A method of synchronizing the phase of a local image synchronization signal generator of a local video data processor in communication with an asynchronous switched packet network to the phase of a reference image synchronization signal generator of a reference video data processor also coupled to the network, the local and reference processors having respective clocks, the reference and local image synchronization signal generators generating periodic image synchronization signals in synchronism with the reference and local clocks respectively including: frequency synchronizing the local and reference clocks; sending an image timing packet providing reference image synchronization data indicating the difference in timing, measured with respect to the reference processor's clock, between the time at which the image timing packet is launched onto the network and the time of production of a reference image synchronization signal; and controlling the timing of the production of the local image synchronization si

Abstract: According to embodiments, a color signal processing circuit includes: an A/D converter configured to convert an analog television signal into a digital signal by using a clock; a color signal demodulation circuit configured to color-demodulate the television signal converted into the digital signal by the A/D converter; a clock generation section configured to generate the clock that is used by the A/D converter; and a frequency control section configured to control the clock frequency of the clock generation section on the basis of a color subcarrier frequency of a color signal included in the analog television signal and on the basis of the vertical synchronization signal frequency of the analog television signal.

Abstract: A video signal synchronization signal generating apparatus for making a display reference synchronization signal Vb that serves as a reference of video display and has a first frequency and an input synchronization signal Vi that constitutes images and has a second frequency synchronized with each other, the apparatus including: a frequency ratio generating section configured to divide a frequency that is double the first frequency by the second frequency to calculate a frequency ratio n; a Vx generation comparator circuit section configured to generate coincidence signal Vx? having pulses that are inserted by equally dividing one period of the input synchronization signal Vi by the frequency ratio n; and a Vx generation circuit section configured to remove the alternate pulses of the coincidence signal Vx? to generate synchronization signal Vx of a same phase as the phase of the input synchronization signal Vi.

Abstract: A sync separation circuit separates a synchronizing signal from a video signal containing the synchronizing signal. A minimum level detecting section detects a minimum level of a video signal. A sync tip level detecting section detects a sync tip level in the video signal. A pedestal level detecting section detects a pedestal level in the video signal. Based on both the sync tip level detected by the sync tip level detecting section and the pedestal level control by the pedestal level detecting section, a slice level setting section sets a slice level corresponding to an intermediate value between the sync tip level and the pedestal level. The slice level control section sets the slice level based on the minimum level detected by the minimum level detecting section if the slice level set based on the sync tip level and the pedestal level is inappropriate.

Abstract: The invention concerns receive circuitry for extracting horizontal and vertical synchronization signals from a digital synchronization signal associated with a video signal, the digital synchronization signal having a plurality of pulses, the receive circuitry including detection circuitry arranged to determine a first value indicative of the time delay between a timing edge of a first pulse and a timing edge of a second pulse of the digital synchronization signal; and a synchronization extraction block arranged to determine that one of the plurality of pulses is a vertical synchronization pulse based on a comparison between the first value and a reference value.

Abstract: In a device for separating a synchronous signal in a video signal, a capacitor receives the video signal to obtain a coupling signal, a level determining circuit receives the coupling signal and compares a voltage level of the coupling signal with a number of reference voltages. The reference voltages define several reference voltage ranges, one of which is a predetermined reference voltage range. The level determining circuit outputs an adjusting signal according to a reference voltage range corresponding to a minimum voltage level of the coupling signal within a predetermined time period. A level adjusting circuit has several current sources for receiving the adjusting signal and thus controls the current sources to adjust a DC level of the coupling signal. A synchronous signal separating circuit separates the synchronous signal from the coupling signal when the minimum voltage level of the coupling signal is substantially within the predetermined reference voltage range.

Abstract: A system, apparatus and methods for providing a single use imaging device utilizing split data streams to maximize the data transfer rate between components for use in sterile environments is disclosed and described. A single use high definition camera used for general purpose surgical procedures including, but not limited to: arthroscopic, laparoscopic, gynecologic, and urologic procedures, may comprise an imaging device that is a sterile and designed to ensure single use. The imaging device may have one or more imaging sensors, either CCD or CMOS, encased in a housing. The imaging device may further components for splitting the transmitted data.

Abstract: A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization compensation period and the detected phase difference; a synchronization phase correcting section configured to correct the phase of the input synchronizing signal on the basis of the output signal of the adding section; a gate signal generating section configured to generate a gate signal representing the synchronization compensation period based on the display synchronizing signal; a synchronization determining section configured to determine whether the synchronization can be effected, by detecting whether the input synchronizing signal exists within the synchronization compensation period; and a selecting section configured to perform switching to the corrected input synchronizing signal on the basis of the determination result of the synchron

Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.

Abstract: In a method and circuit for recovering a sync signal from an input sync signal passing through a cable to a display device, an average value of the input sync signal is obtained during a predetermined time period so as to obtain a sync threshold, which is compared with the input sync signal. A sync signal is output when the input sync signal is greater than the sync threshold.

Abstract: A H-sync phase locked loop device for TV video signal is provided herein. After the TV video signal is digitalized, clamping and slicing operations are performed on the digitalized TV video signal to respectively generate a clamped signal and a sliced signal. According to the clamped signal and the sliced signal, an H-sync frequency calculator can calculate the falling and rising transients of the H-sync signal and an H-sync frequency is obtained therefrom. Because the H-sync frequency is dynamically adjusted according to the input TV video signal, the phase locking of the input TV video signal can tolerate more deviations of the H-sync by replacing a predetermined H-sync frequency.

Abstract: A method of synchronizing the phase of a local image synchronization signal generator of a local video data processor in communication with an asynchronous switched packet network to the phase of a reference image synchronization signal generator of a reference video data processor also coupled to the network, the local and reference processors having respective clocks, the reference and local image synchronization signal generators generating periodic image synchronization signals in synchronism with the reference and local clocks respectively comprises the steps of: frequency synchronizing the local and reference clocks; the reference video data processor sending, via the network, to the local data processor an image timing packet providing reference image synchronization data indicating the difference in timing, measured with respect to the reference processor's clock, between the time at which the image timing packet is launched onto the network and the time of production of a reference image synchroni

Abstract: The present invention provides a synchronizing signal detection circuit capable of always stably detecting a synchronizing signal. The synchronizing signal detection circuit predicts detection positions of synchronizing pulses every synchronization cycle peculiar to an input video signal. The synchronizing signal detection circuit further supplies the input video signal to a plurality of unnecessary signal eliminating paths in common and extracts synchronizing signals of every path respectively from video signals of every path obtained by eliminating unnecessary signals according to the characteristics of the paths every path.

Abstract: A synchronization detector of a video signal processor includes a line buffer, a parameter extraction unit and synchronization detection unit. The line buffer sequentially stores a digital video signal corresponding to an input analog video signal, line by line of the input analog video signal. The parameter extraction unit continuously extracts horizontal synchronization parameters from the digital video signal stored line by line and continuously extracts vertical synchronization parameters from a portion of the digital video signal stored line by line. The synchronization detection unit generates horizontal and vertical synchronization signals of the input analog video signal using time information related to local minimum values of the horizontal synchronization parameters and time information related to local minimum values of the vertical synchronization parameters.

Abstract: In one aspect a transmission system with a transmitter which can be connected to a video source and a receiver linked to the transmitter via at least four circuit pairs, to which receiver a playback device can be connected is provided. Data is usually exchanged digitally between a graphics card in a personal computer and an LCD display module. The personal computer transmits a digital R, G, B video signal to the LCD display module via a special, so-called DVI (Digital Video Interface) cable. This DVI cable is also provided to transmit so-called DDC (Display Data Channel) data, which particularly comprises specification information of the LCD display module. A transmission system is proposed, which simplifies a connection of an LCD display module to a personal computer and with which the DVI cable can be dispensed with.

Abstract: A display apparatus, equipped with a common input terminal inputting different video signals, can discriminate the type of an input video signal entered from the common input terminal. The display apparatus includes the common input terminal inputting different video signals. A synchronizing signal separation unit separates a synchronizing signal from a video signal entered from the common input terminal. A frequency measurement unit measures a frequency of the synchronizing signal. An input signal discrimination unit discriminates the video signal entered from the common input terminal based on a type of the synchronizing signal separated by the synchronizing signal separation unit and a measurement result obtained by the frequency measurement unit.

Abstract: According to an embodiment, a synchronization byte detection portion includes: an 0x47 detector configured to sequentially read in TS data in predetermined units from a memory storing TS data including predetermined synchronization data, and detect a predetermined synchronization byte; a counter configured to count a number of times the predetermined synchronization byte is detected by the 0x47 detector; and a determination instruction portion configured such that, in a case where after detecting an initial predetermined synchronization byte, the 0x47 detector reads in TS data at predetermined intervals and the 0x47 detector does not detect the predetermined synchronization byte at the predetermined intervals a predetermined number of times in succession, the determination instruction portion causes the 0x47 detector to sequentially read in TS data from next TS data after the initial predetermined synchronization byte.

Abstract: A system and method for correcting so-called “lip sync” errors is provided, using a synchronization test signal comprising a video signal including a colorbar signal that is periodically interrupted by a series of consecutive defined black frames and an audio signal comprising a tone periodically interrupted by a period of silence beginning at the same time as the first of the series of consecutive defined black frames. The synchronization test signal is configured to survive encoding, decoding, conversion, and compressing processes used in a typical digital broadcast system environment and thus provide a means of measuring the relative audio and video timing of a processed signal.

Abstract: The method according to the invention for adjusting the tuning of a receiver circuit for receiving modulated a high frequency signal within a frequency range, the high frequency signal comprising a sync signal, uses the steps of shifting a frequency of a local oscillator within the frequency range and looking for the sync signal, and storing the value of a first frequency, when a sync signal is recognized. Then, the frequency of the local oscillator is continuously shifted in the same frequency direction across the bandwidth of the modulated high frequency signal by controlling the presence of the sync signal. The frequency, at which the sync signal is lost, is stored as a second frequency. From the first and the second frequency in a further step an optimum tuning frequency, located between the first and second frequency, is calculated for the reception for the high frequency signal.

Abstract: A video signal output circuit includes a sync-tip clamp circuit fixing a sync-tip level of an input video signal at a constant voltage, a low-pass filter receiving the video signal output from the sync-tip clamp circuit and eliminating a predetermined high-frequency component, a dummy circuit receiving the video signal output from the sync-tip clamp circuit and outputting the video signal having substantially the same sync-tip level as that of the video signal output from the low-pass filter, and an output driver receiving the video signal output from the low-pass filter and outputting the video signal with a low output impedance. The sync-tip clamp circuit controls the sync-tip level of the video signal output from the dummy circuit such that the sync-tip level of the video signal is equal to a predetermined reference voltage.

Abstract: An object of the present invention is to provide a digital receiving apparatus for providing useful information to its user without interruption when reception quality deteriorates. It includes: an information separating unit 4 for reproducing a stream of demodulation signal S3, and separating it into stream signals S4 on multiplexed respective channels for output; a decoding unit 5 for decoding and outputting the stream signals S4; and a control unit 6 for switching and controlling a stream signal for the decoding unit 5 to decode out of the stream signals on the respective channels, and the control unit 6 switches to the stream signal on another channel and makes the decoding unit 5 decode it when physical information for indicating reception quality under reception and the data type of the stream signal on the channel selected out of the channels do not conform to a predetermined relationship.

Abstract: A method for generating a video clock and an associated target image frame is disclosed. The method generates an output clock signal for outputting a target image frame to a panel according to a frame pixel number and a vertical synchronization signal (Vsync). The target image frame corresponds to a source image frame. The frame pixel number is the number of total pixels included in a predetermined frame format, and the Vsync signal is an input Vsync signal or an output Vsync signal. The period of the output clock signal is the result of the period of the Vsync divided by the frame pixel number. In this manner, the format of the target image frame can remain substantially fixed, and is substantially equal to the predetermined frame format.

Abstract: According to embodiments, a color signal processing circuit includes: an A/D converter configured to convert an analog television signal into a digital signal by using a clock; a color signal demodulation circuit configured to color-demodulate the television signal converted into the digital signal by the A/D converter; a clock generation section configured to generate the clock that is used by the A/D converter; and a frequency control section configured to control the clock frequency of the clock generation section on the basis of a color subcarrier frequency of a color signal included in the analog television signal and on the basis of the vertical synchronization signal frequency of the analog television signal.

Abstract: An image processing device includes a synchronizing signal separation section, a counting section, a synchronizing signal determination section, and a video format determination processing section. The synchronizing signal separation section separates a horizontal synchronizing signal from a received broadcasting signal. The counting section counts the pulse number of the separated horizontal synchronizing signal. The synchronizing signal determination section determines presence/absence of a synchronizing signal based on the counted value by the counting section. The video format determination processing section determines a video format of the received broadcasting signal based on the number of scan lines. The video format determination processing section determines the video format only when it is determined that there is a synchronizing signal by the synchronizing signal determination section.

Abstract: A video synchronization signal generating circuit includes a sample and hold circuit, a voltage divider and an amplifier. The voltage divider produces an adaptive voltage level based at least in part on an output of the sample and hold circuit. The amplifier, which receives a video signal, is connectable by switches in different configurations. In a first configuration the amplifier acts as a comparator to compare the adaptive voltage level with the video signal. An output of the amplifier in the first configuration is an output of the video synchronization signal generating circuit. In a second configuration the amplifier forms part of the sample and hold circuit.

Abstract: A video signal processing circuit, in which a horizontal synchronizing signal is separated from an input analog video signal by a synchronism separating circuit, whether a “H” period of the horizontal synchronizing signal continues for more than a prespecified period of time or not is checked by a synchronizing signal monitoring counter, and power supply to an A/D converter is controlled thereby according to a result the confirmation.