Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, a first electrode, a second electrode, and a memory. The first electrode is provided on the substrate. The second electrode crosses on the first electrode. The memory portion is provided between the first electrode and the second electrode. At least one of an area of a first memory portion surface of the memory portion opposed to the first electrode and an area of a second memory portion surface of the memory portion opposed to the second electrode is smaller than an area of a cross surface of the first electrode and the second electrode opposed to each other by the crossing.

Abstract: The invention relates to a memory circuit for providing an item of information for a prescribed period of time. The memory circuit has a memory cell with a PMC resistance component which has a solid electrolyte material and a write circuit for writing to the memory cell by applying an electrical variable to the solid electrolyte material. The write circuit is configured to set a resistance of the PMC resistance component on the basis of the prescribed period of time. The resistance corresponds to a logic state of the memory cell and increases over time such that the resistance reaches or exceeds a prescribed resistance threshold value in the prescribed period of time.

Abstract: A chalcogenide material is formed to a first thickness over the first conductive electrode material. The chalcogenide material includes AxBy. A layer that includes a metal is formed to a second thickness over the chalcogenide material. The metal including layer defines some metal including layer transition thickness for the first thickness of the chalcogenide material such that when said transition thickness is met or exceeded, said metal including layer when diffused within said chalcogenide material transforms said chalcogenide material from an amorphous state to a crystalline state. The second thickness being less than but not within 10% of said transition thickness. The metal including layer is irradiated effective to break a chalcogenide bond of the chalcogenide material and diffuse at least some of the metal into the chalcogenide material.

Abstract: A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

Abstract: A read-only memory for storing a plurality of bits of information. The read-only memory includes a plurality of memory cells arranged in an array with each memory cell including a capacitor having either a relatively high capacitance or a relatively low capacitance representing a bit of stored information. The read-only memory further includes a reading means for accessing each memory cell and providing a first or second output responsive to the capacitance level of the memory cell capacitance means.