Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.

Abstract: Disclosed is a multi-bit memory device including: a first electrode; a third electrode which is disposed apart from the first electrode; a second electrode which is disposed between the first electrode and the third electrode; a first memory unit which is disposed between the first electrode and the second electrode and includes a material which is electrically polarized and exhibits hysteresis; and a second memory unit which is disposed between the second electrode and the third electrode and includes a material which is electrically polarized and exhibits hysteresis.

Abstract: A semiconductor memory device comprising: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said first wirings and said second wirings; wherein said control circuit applies a first voltage to said selected first wiring, and changes said first voltage based on the position of said selected memory cell within said memory cell array to apply a second voltage to said selected second wiring, so that a predetermined potential difference is applied to a selected memory cell arranged at the intersection between said selected first wiring and said selected second wiring.

Abstract: An integrated circuit can include at least one programmable metallization cell (PMC) comprising an ion conducting material and a metal dissolvable in the ion conducting material, selectively connected to a shunt node; and a biasing circuit comprising a current source coupled to the shunt node configurable to provide a first current in a first type operation, and a voltage regulator coupled to the shunt node configured to regulate a potential at the shunt node; wherein in the first type operation, the voltage regulator shunts current with respect to the shunt node in a same direction as a current flow of the at least one PMC.

Abstract: Memory device, comprising a storage material, a first electrode connected to the storage material; and a second electrode associated to the storage material.

Abstract: An integrated circuit may include: access circuits that couple first electrodes of a plurality of programmable metallization cells (PMC) to access paths in parallel, each PMC comprising a solid ion conducting material formed between the first electrode and a second electrode; a plurality of write circuits, each coupled to a different access path, and each coupling the corresponding access path to a first voltage in response to input write data having a first value and to a second voltage in response to the input write data having a second value; and a node setting circuit that maintains second electrodes of the PMCs at a substantially constant third voltage while write circuits couple the access paths to the first or second voltages.

Abstract: In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.

Abstract: Disclosed is a passive matrix-addressable memory apparatus. The passive matrix-addressable memory apparatus comprises: a plurality of first electrode lines horizontally arranged with respect to each other; a plurality of second electrode lines disposed orthogonal to the plurality of first electrode lines to be horizontally arranged with respect to each other; a memory unit formed between the plurality of first electrode lines and the plurality of second electrode lines, and containing an electrically polarizable material exhibiting hysteresis; and a switch unit. The switch unit comprises: first electrodes of a cantilever structure respectively formed between the memory unit and the plurality of first electrode lines to be electrically connected to the plurality of first electrode lines; and second electrodes electrically connected to the memory unit to be spaced apart from the first electrodes to face the first electrodes.

Abstract: A method and apparatus for providing electric microcontact printing is provided. A stamp is brought into contact with the surface of a substrate to provide high resolution features. Aspects of the invention may be used for data storage, microcontact printing, and for other applications requiring high resolution pattern transfer.

Abstract: Disclosed is a passive matrix-addressable memory apparatus. The passive matrix-addressable memory apparatus comprises: a plurality of first electrode lines horizontally arranged with respect to each other; a plurality of second electrode lines disposed orthogonal to the plurality of first electrode lines to be horizontally arranged with respect to each other; a memory unit formed between the plurality of first electrode lines and the plurality of second electrode lines, and containing an electrically polarizable material exhibiting hysteresis; and a switch unit. The switch unit comprises: first electrodes of a cantilever structure respectively formed between the memory unit and the plurality of first electrode lines to be electrically connected to the plurality of first electrode lines; and second electrodes electrically connected to the memory unit to be spaced apart from the first electrodes to face the first electrodes.

Abstract: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

Abstract: In a ferroelectret or electret memory cell a polymeric memory material is a blend of two or more polymeric materials, the polymeric material being provided contacting first and second electrodes. Each electrode is a composite multilayer having a first highly conducting layer and a conducting polymer layer, the latter forming a contact between the former and the memory material.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A memory device includes a semiconducting polymer film, which includes an organic dopant. The semiconducting polymer film has a first side and a second side. The memory device also includes a first plurality of electrical conductors substantially parallel to each other coupled to the first side of the semiconducting polymer layer, and a second plurality of electrical conductors substantially parallel to each other, coupled to the second side of the semiconducting polymer layer. The first and second pluralities of electrical conductors are substantially mutually orthogonal to each other. Further, an electrical charge is localized on the organic dopant.

Abstract: A semiconductor memory device for realizing high speed writing while maintaining credibility of write data, wherein a write gate is provided between a bit line and an input/output data line of a memory cell array, the write gate becomes open when a selected word line becomes an activation state and a write signal set to the input/output data line in accordance with write data is applied to the selected bit line via the write gate when writing, so that writing of data to a selected memory cell can be performed immediately after activating the selected word line when writing, and writing to the selected memory cell can be performed in parallel with reading and refreshing of non-selected memory cells, consequently, a time for storing charges to the selected memory cell can be sufficiently secured and writing at a high speed can be realized.

Abstract: In a data storage apparatus comprising means for storing and retrieving data in respective write and read operations, and first and second set of addressing electrodes are provided, the latter set having electrodes that preferably are oriented orthogonally to the electrodes of the first set, and the electrodes (b, c) of the second set are provided as parallel twin electrodes located in parallel recesses or trenches (3) in the electrodes of the first set. The trenches compris a soft ferroelectric or electret memory material with piezoelectric properties such that memory cells (1) with two subcells (&agr;1, &agr;2) are formed in the trench (3) respectively between the electrodes (a) of the first set and the parallel twin electrodes (b, c) on either side of the latter. In a write operation data are encoded in the memory cells (1) by means of an applied voltage potential over the subcells (&agr;1, &agr;2).

Abstract: Electrets can be produced from cycloolefin copolymers (COCs), and charges applied thereto are stable for long periods, even at high temperatures and high relative humidities. The reduction here in a positive charge applied to the COCs is smaller than that of negative charges applied to the COCs. The stability over time of the charges applied is impaired by adding polar additives, such as inorganic silicon compounds. Films, fibers or nonwovens produced from electrets can be processed to give filters.

Abstract: A semiconductor memory has a random access memory (DRAM) and a mask read only memory (MROM) formed on the same semiconductor substrate; each of the DRAM and MROM comprising a plurality of word lines, a plurality of bit lines and a plurality of memory cells: each of the memory cells included in the DRAM and the MROM comprising; a switching element including a source and drain regions and a gate electrode; a capacitance element formed of a lamination of an insulating film and a plate electrode subsequently laminated in this order; and a conductive parts connecting the switching element to the word lines, the bit lines, and a capacitance element; the MROM including a predetermined memory cell which lacks at least one part of the conductive parts.

Abstract: A photographic contact printing process is disclosed having application in the mass production of replicate video discs from a master disc, and other applications wherein it is desired to replicate micro-detail over a relatively large area. A problem with conventional contact printing from a mask to a photographic medium is one of maintaining intimate contact over a relatively large area since dust, dirt, etc., are almost impossible to completely eliminate in any practical manner. In accordance with the present invention, a contact printing process is provided wherein intimate contact is not necessary for making high quality contact prints. The present invention recognizes that in contact printing information from a master disc to a replicate disc, the contact printing process is significantly less sensitive to imperfect contact between the master disc and the replicate disc if one employs a replicate disc comprising a photosensitive material having a certain optical properties.

Abstract: A system for reading and storing data includes a rotating transparent substrate having a layer of dielectric material disposed thereon. A movable support member positioned adjacent one side of the substrate includes a radiant energy source and an electrical field generator which, when energized, produces an electret in the dielectric material when heated to an electret forming temperature by the radiant energy source and which polarizes light rays from the radiant energy source in a direction representing a binary value. An optical detector mounted on a support member adjacent the opposite side of the substrate detects the presence or absence of the polarized light and generates electrical signals representing such conditions. The electrical field generator includes a plurality of pole members for producing an electret having more than one plane of polarization, each of which represents a different binary value.

Abstract: A storage element for an erasable, digital, permanent storage device is disclosed in which a bipolar, charged electret serves as the storage medium. The electret has a thin conductive layer on one side and a ring electrode on the other. The state of charge of the electret is changeable to erase, or change the storage element.