Abstract: A memory includes cytokines, such as macromolecule proteins, as a poly-state data storage. Each fold state of multiple fold states of a protein are associated with a data value. Current flow through the protein is associated with a resistance of the protein associated with its current fold state. Application of light, electric fields or heat via an associated element or elements facilitates placement of a protein in a fold state that corresponds to an associated resistance and correlates with an incoming data value. Measuring of current or resistance allows for reading of a data value associated with the protein.

Abstract: Systems and methods are disclosed to control interactivity with a video gaming system. The system includes a game console and a controller that is configured to be held in a plurality of handhold orientations. The controller further includes a handle that extends between a first end and a second end along a length axis and an input feature disposed at the first end. The input feature includes sensors to detect manipulations that cause a relative movement between the input feature and the handle. The manipulations that are detected include torque applied to the input feature about the length axis. Where the detected manipulation are relayed to the game console where the game console correlates the detected manipulation into control of the video game. The gaming system can be primarily executed through a local game console, or the game console (or computing device), can communicate to remote servers, over the internet, to processes primary execution.

Abstract: A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

Abstract: Physical neural networks based nanotechnology include dendrite circuits that comprise non-volatile nanotube switches. A first terminal of the non-volatile nanotube switches is able to receive an electrical signal and a second terminal of the non-volatile nanotube switches is coupled to a common node that sums any electrical signals at the first terminals of the nanotube switches. The neural networks further includes transfer circuits to propagate the electrical signal, synapse circuits, and axon circuits.

Abstract: Physical neural networks based nanotechnology include dendrite circuits that comprise non-volatile nanotube switches. A first terminal of the non-volatile nanotube switches is able to receive an electrical signal and a second terminal of the non-volatile nanotube switches is coupled to a common node that sums any electrical signals at the first terminals of the nanotube switches. The neural networks further includes transfer circuits to propagate the electrical signal, synapse circuits, and axon circuits.

Abstract: An active memory element is provided. One embodiment of the invention includes a bi-polar memory two-terminal element having polarity-dependent switching. A probability of switching of the bi-polar memory element between a first state and a second state decays exponentially based on time delay and a difference between received signals at the two terminals and a switching threshold magnitude.

Abstract: A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

Abstract: A semiconductor device includes: a control-voltage supply unit 110; an MOS transistor including a gate electrode 109 and drain and source regions 103a and 103b; a dielectric capacitor 104; and a resistor 106. The dielectric capacitor 104 and the resistor 106 are disposed in parallel and interposed between the gate electrode 109 and the control-voltage supply unit 110. With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitor 104 and the gate electrode 109 upon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.

Abstract: An optical memory system includes memory cells which utilize synthetic DNA as a component of the information storage mechanism. In the preferred embodiment, memory cells contain one or more chromophoric memory units attached to a support substrate. Each chromophoric memory unit comprises a donor, an acceptor and, at some time during its existence, an active quencher associated with the donor and/or the acceptor. The donor and the acceptor permit non-radiative energy transfer, preferably by Forster energy transfer. To write to the memory cell, the quencher is rendered inactive, preferably by illumination with ultraviolet light. To read, the chromophoric memory units in a read portal are illuminated, and the read illumination is detected. In the preferred embodiment, multiple chromophoric memory units having resolvable read properties are contained within a single read portal. In this way, a multibit word of data may be read from a single diffraction limited read portal.

Abstract: Quantum pseudo-random address memory apparatus including a low dimensional plurality of address ports, a plurality of polymer nano-memory elements, polymer mixer elements coupling the address ports to a high dimensional plurality of the plurality of polymer nano-memory elements, and data output ports and structure coupled to the plurality of polymer nano-memory elements. The high dimensional plurality of polymer nano-memory elements is greater than the low dimensional plurality of address ports by a number resulting in substantially error free memory recalls.

Abstract: An optical memory system includes memory cells which utilize synthetic DNA as a component of the information storage mechanism. In the preferred embodiment, memory cells contain one or more chromophoric memory units attached to a support substrate. Each chromophoric memory unit comprises a donor, an acceptor and, at some time during its existence, an active quencher associated with the donor and/or the acceptor. The donor and the acceptor permit non-radiative energy transfer, preferably by Forster energy transfer. To write to the memory cell, the quencher is rendered inactive, preferably by illumination with ultraviolet light. To read, the chromophoric memory units in a read portal are illuminated, and the read illumination is detected. In the preferred embodiment, multiple chromophoric memory units having resolvable read properties are contained within a single read portal. In this way, a multibit word of data may be read from a single diffraction limited read portal.