Abstract: According to an aspect of the invention, there is provided a device for generating a unique response to a challenge, the device comprising: a plurality of structures, each structure being able to change from a first distinct state, to a second distinct state, in response to an appropriate input challenge; the device being arranged to facilitate a challenge of the plurality of structures in combination, by changing an input to the plurality of structures in combination, to cause each structure of the plurality of structures to change from the first distinct state, to the second distinct state; as part of the challenge, the device being arranged to facilitate a measurement of an output of the plurality of structures in combination, in response to the input; wherein the unique response is at least indicative of a sequence in which the change in state takes place for each of the plurality of structures, in response to the input.

Abstract: Systems, computer program products, and methods are described herein for implementing an enhanced authentication framework using Erasable Programmable Read-Only Memory (EPROM) grid pattern recognition.

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.

Abstract: A NOR flash memory apparatus and a recover and read method for the NOR flash memory apparatus are described. The recover and read method includes: operating a power-up process on the NOR flash memory apparatus during a power-up time period; operating a power-up reading operation and reading a mark bit of a memory block of the flash memory apparatus during a reading time period after the power-up time period; and, applying a negative voltage to a plurality of un-selected word lines for the power-up reading operation to operate without leakage current from bit lines of the memory block being caused and therefore to operate normally without causing mistakes.

Abstract: A storage device for booting a host computing device includes a first storage memory region having a first storage memory controller, a second storage memory region having a second storage memory controller, and a resilient boot controller. The resilient boot controller is configured to store boot code in the first storage memory region, prevent write access by the host computing device through the first storage memory controller to the first storage memory region, detect a reset of the host computing device through the input/output interface, copy at least a portion of the boot code from the first storage memory region to the second storage memory region, responsive to detection of the reset of the host computing device, and enable read access of the copied boot code by the host computing device through the second storage memory controller of the second storage memory region, responsive to the copy operation.

Abstract: To allow access to encrypted data stored in the memory of a user terminal, the corresponding secret encryption key is stored in a secure element integrated into the user terminal and this secure element serves as a highly secure relay toward an access device to this data, used by a third party. To do so, a secure communication channel is established between the third party and the secure element. The EAC standard allows mutual authentication accompanied by the establishment of such a secure communication channel. The secure element performs an encryption conversion of the data so that the latter is protected by a session (or transport) key associated with the secure communication channel, and no longer by the initial secret key. The third party can thus access the encrypted data without even knowing the initial secret key.

Abstract: Apparatuses and methods related to memory disablement for memory security. Disabling the memory for memory security can include, responsive to receiving a trigger signal, provide a voltage, which may be in excess of an operating or nominal voltage, to the access circuitry. The voltage may thus be sufficient to render the access circuitry inoperable for accessing data stored in the memory array.

Abstract: A physically unclonable function (PUF) cell array includes a first PUF cell arranged in a first column in a first direction and a second PUF cell arranged in a second column in the first direction. The first PUF cell includes a first set of conductive structures extending in the first and a second direction. The second PUF cell includes a second set of conductive structures extending in the first and the second direction. The first PUF cell includes a first conductive structure and a second conductive structure extending in the second direction. The second PUF cell includes a third conductive structure and a fourth conductive structure extending in the second direction. The first and third conductive structure or the second and fourth conductive structure are symmetric to each other with respect to a central line of at least the first or second PUF cell extending in the second direction.

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

Abstract: An electronic part including an integrated circuit and a memory, the integrated circuit including a first clock terminal to which a clock signal is inputted, a first data terminal via which a first serial data signal is inputted and outputted, a second clock terminal via which the clock signal is outputted to the memory, a second data terminal via which a second serial data signal is inputted and outputted from and to the memory, and a first interface circuit including a control circuit that controls the communication state of the integrated circuit to be a first communication state in which the first serial data signal inputted to the first data terminal is outputted as the second serial data signal via the second data terminal or a second communication state in which the second serial data signal inputted to the second data terminal is outputted as the first serial data signal via the first data terminal.

Abstract: Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. The memory device may have a register that enables or disables access to the portion when data indicating whether to enable or disable access to the portion is written into the register via a serial data in (SI) input.

Abstract: A wireless mouse includes a mouse body and a wireless receiver. The wireless receiver is connected with a computer host. When the mouse body is operated by a user, an original information is generated. The original information is encrypted and converted into an encryption information by the mouse body. The wireless receiver receives the encryption information from the mouse body. After the encryption information is received by the wireless receiver, the encryption information is decrypted by the wireless receiver. Consequently, the encryption information is restored into the original information. After the computer host receives the original information through the wireless receiver, the computer host performs a corresponding operation.

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Abstract: Systems, apparatuses, and methods for improving security of a silicon-based system by creating a glitch-resistant process for executing a software code block on the silicon-based system are disclosed. An example method may begin by marking the software code block as non-executable. Second, intent to execute the software code block is registered with a staging register. Third, the software code block is compressed into a compression constant. Fourth, the compression constant is compared with a first predetermined value using two comparators. Fifth, responsive to the comparators providing a true result after comparison, the software code block is marked as executable to allow the software code block to execute. In another aspect, the example method may be repeated for n>1 iterations, and in each iteration i, an ith software code block is compressed into an ith compression constant that is compared to an ith predetermined value.

Abstract: A memory device that includes a memory array having pluralities of non-volatile memory cells, a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, and a controller. The controller is configured to erase the pluralities of non-volatile memory cells, set each of the index memory cells to a first state, and program first data into the memory array by reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state, programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and setting the first one of the index memory cells to a second state different from the first state.

Abstract: Aspects of a storage device include a memory comprising a plurality of memory locations each associated with a physical address, the memory configured to store a plurality of video frames received from a host device at the physical addresses, each of the video frames being associated with a logical address; and a controller configured to store in a partition of the memory the logical addresses for a subset of the video frames, the controller being configured to provide the host access to the partition to read the logical addresses during rapid playback of the video frames. Aspects of the host device include a processor configured to write the video frames to the storage device, to identify the subset of the video frames to the storage device, and during rapid playback, to access the storage device to read the logical address for each video frame in the subset.

Abstract: A memory device having fault detection functionality for improving functional safety and a control system including the memory device are provided. The memory device includes a first memory cell array configured to store input data and output the input data as output data and a second memory cell array configured to store bit values of a row address and a column address of the first memory cell array in which the input data is stored, and output the bit values of the row address and the column address as an internal row address and an internal column address. The row/column address designating a read operation may be compared to the internal row/column address, and an address comparison signal as a result of the comparison may be output. The address comparison signal may provide fault detection functionality for a data error of an automotive electronic system.

Abstract: A semiconductor device includes a command decoder and a period signal generation circuit. The command decoder generates a first entry command and a first exit command based on a first internal chip selection signal and a first internal control signal and generates a second entry command and a second exit command based on a second internal chip selection signal and a second internal control signal. The period signal generation circuit generates a period signal based on the first entry command, the second entry command, the first exit command, the second exit command, and the period signal.

Abstract: The invention relates to a method for managing an memory LNVM erasable by block. The method comprises an index management of the memory blocks wherein the index indicates if a block is erased (Erased) or to be erased (TBE). A memory manager performs a block erasing when the memory is not in use and a block is to be erased and when the number of erased blocks is lower than a predetermined number.

Abstract: A method of testing an OTP memory is disclosed. An OTP program mechanism that uses heat accelerated electromigration can be fully tested. In one embodiment, an OTP cell's programmability can be tested if an initial OTP element resistance is less than a predetermined resistance, as such insures that sufficient heat can be generated to be programmable. A non-destructive program state, or fake reading 1, can be created by low-voltage programming a cell while reading the same cell at the same time. Accordingly, alternative 0s and 1s patterns can be generated to fully test every functional block of an OTP memory.

Abstract: A system may comprise a host device that stores a first application programming interface (API) and a transceiver. The transceiver may comprise a microcontroller unit (MCU) that stores a second API. The second API may be a subset of the first API. The first API and the second API may control different functions of a data-path chip of the transceiver. The MCU may be configured to provide controls and data from the first API through the MCU without operating on the controls and the data and without using the second API.

Abstract: A memory system includes a memory device including a first memory region of higher density storage and a second memory region of lower density storage; and a controller configured to control the memory device to sequentially perform a backup program operation to the second memory region and perform coarse program and fine program operations to the first memory region for each of data chunks, wherein the controller controls, for at least two among the data chunks, the memory device to first perform the coarse program and then perform the fine program operation, and wherein the controller controls the memory device to perform the backup program operation without a program verify process.

Abstract: An apparatus may include an address counter to provide first address information and second address information. The first address information may include a first number of bits and the second address information may include a second number of bits that is smaller than the first number of bits. The address counter may perform a first updating operation. The first updating operation being such that the first address information is updated from a first initial value to a first final value. The address counter may also perform a second updating operation, the second updating operation being such that the second address information is updated from a second initial value to a second final value. In addition, the address counter may also perform the second updating operation at least twice per the first updating operation being performed once.

Abstract: A monitoring apparatus may include reception logic operable to receive processing characteristic data generated during the processing of the effluent stream; segregation logic operable to segregate the processing characteristic data into contributing processing characteristic data associated with contributing periods which contribute to a condition of the at least one processing tool and non-contributing processing characteristic data associated with non-contributing periods which fail to contribute to the condition; and fault logic operable to utilise the contributing processing characteristic data and to exclude the non-contributing processing characteristic data when determining a status of the condition.

Abstract: A semiconductor chip comprises at least one data bus to transmit data processed by the semiconductor chip, an electric potential generator block packaged together with the at least one data bus to be blocked from external light by a package, the electric potential generator block to detect an event in which the package is unable to block the external light, and a switch configured to block a transmission of at least some data in the at least one data bus if the event is detected. A semiconductor chip comprises an energy harvesting element inside a package. The energy harvesting element may comprise an on-chip photodiode. A depackaging attack causes the generation of a voltage of a photodiode, and thus a change in physical state of the packaging can be detected.

Abstract: A storage device includes a nonvolatile memory device that includes memory blocks, each including memory cells, and a controller that receives a first write request from an external host device. Depending on the first write request, the controller transmits a first sanitize command to the nonvolatile memory device and transmits first write data and a first write command associated with the first write request to the nonvolatile memory device. The nonvolatile memory device is configured to sanitize first data previously written to first memory cells of a first memory block of the memory blocks in response to the first sanitize command. The nonvolatile memory device is further configured to write the first write data to second memory cells of the first memory block in response to the first write command.

Abstract: The subject disclosure is directed towards protecting code in memory from being modified after boot, such as code used in a dedicated microprocessor or microcontroller. Hardware, such as in logic or in a memory protection unit, allows a range of memory to be made non-writeable after being loaded, e.g., via a secure boot load operation. Further, startup code that is used to configure the hardware/memory may be made non-executable after having run once, so that no further execution may occur in that space, e.g., as a result of an attack. A function in the runtime code may allow for a limited, attack-protected reconfiguration of sub-regions of memory regions during the runtime execution.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: Systems, circuits, and chips for hardening a latch/flip-flop circuit against soft errors caused by alpha and neutron radiation are provided. As an example, a latch/flip-flop circuit including a switch to selectively couple a capacitor to first and second storage nodes during a hold phase is disclosed.

Abstract: A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

Abstract: A semiconductor system includes a medium controller and a semiconductor module. The medium controller outputs an address that is sequentially counted in a test mode, senses levels of data corresponding to the address in the test mode to determine if the data has a row error or a chip error, and changes a combination of a host address to generate and store a spare address if a combination of the address corresponds to the chip error in the test mode. The semiconductor module includes a plurality of semiconductor devices. The semiconductor module repairs the address to output the data from a redundancy area if a combination of the address corresponds to the row error. The semiconductor module outputs the data from a spare area selected by the spare address if a combination of the address corresponds to the chip error.

Abstract: Provided are methods, systems, devices of a security-driven design method. The present methods and systems can enable integration of security requirements in the early stages of design along with other design constrains so that potential attacks during IC development, usage, and retirement would render ineffectual. Example methods and systems can comprise circuits and circuit design using vanishable logic through a novel hybrid design method. An example method or system can comprise vanishable logic based on hardware re-configuration and transformation by employing non-volatile memory cells.

Abstract: An information processing device includes a main memory including a non-volatile memory and a volatile memory with access speed higher than the non-volatile memory, the volatile memory storing data in the non-volatile memory, a processor that issues a read request, a write request and a snapshot request and a memory controller that reads, in response to the read request, data in the volatile memory, writes, in response to the write request, write data in the volatile memory and also writes a write history in a sequential manner to the non-volatile memory, performs, in response to the snapshot request, snapshot processing of recording in non-volatile memory a write position of the write history up to a time of a snapshot, and performs, after the snapshot processing, data restoration processing of writing the written data at the write position in the write history to the non-volatile memory.

Abstract: Various embodiments enhance security and tamper resistance of device or components having a hardware intrinsic identity. For example, devices or components having PUFs can map challenges and helper values to a secret or share of secret to utilize a local identity in cryptographic operations. A plurality of components having individual identities can be extend so that the plurality of components can enroll into a shared global identity. Shares of the global identity can be distributed among the plurality of components or devices such that at least two devices must provide at least two shares of the global identity (or threshold operations on the at least two shares) to successfully use the global identity. Such sharing mitigates adversarial tampering attack on the global identity. Share refresh protocols can provide additional security, enable introduction of new components or devices to the global identity, and allow removal of existing components or devices.

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the

Abstract: Disclosed is a nonvolatile memory control method in which a unit of erase and a unit of read are different from each other. The control method includes: allocating a physical address of the nonvolatile memory to a logical address in a predetermined unit; and controlling a size of the unit of erase in which a physical address allocated to a logical address is included according to a write access state with respect to the logical address in the predetermined unit.

Abstract: A semiconductor memory device includes a memory cell array, a status signal generator, an RB output control unit and a control logic. The memory cell array includes a plurality of memory cells. The status signal generator outputs an internal status signal indicating whether the memory cell array is performing an internal operation. The RB output control unit outputs a ready/busy signal based on the internal status signal. The control logic controls the RB output control unit to adjust an output current of the RB output control unit.

Abstract: A semiconductor device includes a first storage unit including twin cells which are electrically rewritable and complementarily store 1-bit data based on a difference in a threshold voltage, a second storage unit including a memory cell which is electrically rewritable, data stored in the memory cell being erased when data in the twin cells is erased, at least one scrambler subjecting first data to a scramble processing by using scramble data to generate second data, a first write circuit which writes the second data into the twin cells in the first storage unit, a second write circuit which writes the scramble data into the memory cell in the second storage unit, and at least one descrambler subjecting the second data read from the first storage unit to a descramble processing by using the scramble data read from the second storage unit.

Abstract: An authentication circuit coupled to a plurality of memory bits includes a first circuit configured to provide a first data pattern to all the bits thereby causing each bit to be in a first data state, detect whether a transition from the first data state to a second data state occurs for each bit in response to a first reducing voltage applied to the plurality of bits, provide a second data pattern to all the bits thereby causing each bit to be in the second data state, and detect whether a transition from the second data state to the first data state occurs for each bit in response to a second reducing voltage applied to the plurality of bits, wherein the first data state is different from the second data state, and a second circuit configured to generate a PUF signature based on the transitions of each bit.

Abstract: Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and a memory controller that transmits a first command and a plurality of address signals indicative of a memory cell in a first bank of the plurality of banks at a first time. The first command is indicative of performing a first memory operation, and a second memory operation different from the first memory operation. The memory device receives the first command and the plurality of address signals and further performs the second memory operation to the first bank responsive, at least a part, to the plurality, of address signals and the first command.

Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

Abstract: Systems and techniques relating to decoder memory management are described. A described system includes a decoder system configured to perform decoder processes in order to decode signals generated by reading a storage medium, the decoder processes being associated with respective memory thresholds; and a memory structure coupled with the decoder system. The decoder processes use the memory structure in accordance with the respective memory thresholds. The decoder system can be configured to detect whether the memory structure is underutilized by a process of the decoder processes, determine an underutilization amount associated with the process with respect to the memory threshold of the process, identify a target decoder process of the decoder processes, and enable the target decoder process to exceed the memory threshold of the target decoder process based on the underutilization amount. Enabling the target decoder process to exceed can increase decoding performance of the target decoder process.

Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

Abstract: A mapping table updating method for a rewritable non-volatile memory module is provided. The method includes: allocating a mapping table storage area for storing a physical address-logical address mapping table in a buffer memory. The method also includes: determining whether a remaining storage space of the mapping table storage area is less than a threshold. If the remaining storage space is less than the threshold, mapping information of the physical address-logical address mapping table stored in the mapping table storage area is updated into at least one logical address-physical address mapping table, and the mapping information of the physical address-logical address mapping table stored in the mapping table storage area is cleared. The method also includes: storing updated mapping information corresponding to a programmed active physical erasing unit into the mapping table storage area.

Abstract: A computer-implemented method is provided for enabling exactly-once messaging. The computer-implemented method includes transmitting a plurality of messages from a first location to a second location via read requests and write requests made to a memory and controlling the read and write requests by a memory controller including a read queue, a write queue, and a lock address list, each slot of the lock address list associated with a lock bit. The computer-implemented method further includes initiating the read requests from the memory via the memory controller when associated lock bits are enabled and initiating the write requests from the memory via the memory controller when associated lock bits are disabled. The computer-implemented method further includes enabling and disabling the lock bits after the initiation of the write and read requests, respectively.

Abstract: The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. The example method further includes generating a random number by detecting a voltage differential between the first sense line and the complementary second sense line.

Abstract: An arithmetic processing device includes: a processor that issues a store command and a load command; and a memory coupled to the processor, wherein the processor: includes a cache memory which stores data to be stored corresponding to the store command and a buffer including entries which stores the data to be stored; searches, in a case where the load command is issued, the entries; and selects, when data to be loaded corresponding to the load command is present in the entries, the data to be loaded from the buffer.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to generate internal commands, internal addresses and internal data for performing an initialization operation. The second semiconductor device may be configured to store the internal data in a plurality of memory cells selected by the internal commands and the internal addresses.

Abstract: Memories include first and second arrays of non-volatile memory cells, a first plurality of data lines containing a first number of data lines selectively connected to respective subsets of the first array of non-volatile memory cells, a second plurality of data lines containing a second number of data lines, less than the first number, selectively connected to respective subsets of the second array of non-volatile memory cells, and sense circuitry selectively connected to the first and second pluralities of data lines. The memories are configured, when reading the second array of non-volatile memory cells, to connect the sense circuitry to each data line of the second plurality of data lines, and the memories are configured, when reading the first array of non-volatile memory cells, to connect the sense circuitry to a number of data lines of the first plurality of data lines equal to the second number.

Abstract: A storage system includes a storage device including a controller and a nonvolatile memory unit, and a host including a processor configured to determine whether or not the host is going to access the storage device within a predetermined range of time, and cause the storage device to be powered off when it is determined that the host is not going to access the storage device within the predetermined range of time.