Abstract: A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.

Abstract: An apparatus includes a subword driver configured to drive a subword line, wherein the subword driver includes a transistor coupled to the subword line, a word driver control circuit configured to provide a first control signal and a second control signal, and a word driver configured to receive the first and second control signals, and based on the first control signal provide a driving signal including a plurality of reset pulses to the transistor of the subword driver to activate the transistor a corresponding plurality of times to discharge the subword line, and further provide the driving signal including a transition following the plurality of reset pulses to activate the transistor to further discharge the subword line.

Abstract: A monitoring circuit according to an embodiment of the present disclosure includes a booster configured to amplify a current amount between a terminal to which a power voltage is applied and a ground terminal to generate a sensing voltage, and an oscillator configured to output a sensing signal of which a frequency is adjusted in response to the sensing voltage, wherein the booster includes a transistor having a first size and a transistor having a second size greater than the first size, and wherein the oscillator includes a plurality of transistors having a third size greater than the first size.

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Abstract: An non-volatile static random access memory (nvSRAM) is provided in the present invention, including a first pass gate transistor, a second pass gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, which construct collectively two cross-coupled inverters with two storage nodes, wherein resistive random-access memories (RRAM) are set between the first storage node, the first pull-up transistor and the first pull-down transistor and between the second storage node, the second pull-up transistor and the second pull-down transistor.

Abstract: The present disclosure relates to a method and apparatus for determining a signal margin (SM) of a memory cell, a storage medium and an electronic device, and relates to the technical field of integrated circuits. The method for determining an SM of a memory cell includes: when the memory cell performs write and read operations, determining a sense signal threshold of the memory cell under an influence of a noise; and determining, based on the sense signal threshold, an actual SM of the memory cell during data reading.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: According to at least one aspect, a controller having a mode of operation including one of an on mode and an off mode is provided including a voltage supply node, a mode of operation signal node, a powered component, a switching device coupled in series between the voltage supply node and the powered component, a power supply detector coupled to the switching circuit, the voltage supply node, and the mode of operation signal node, the power supply detector being configured to receive a mode of operation signal indicative of the mode of operation of the controller from the mode of operation signal node, determine that the controller is in the off mode based on the mode of operation signal, and control the switching device to prevent a current from passing from the voltage supply node to the powered component responsive to determining that the controller is in the off mode.

Abstract: Devices and techniques are disclosed herein to provide a number of different bias signals to each of multiple signal lines of an array of memory cells, each bias signal having an overdrive voltage above a target voltage by a selected increment and an overdrive period, to determine settling times of each of the multiple signal lines to the target voltage for the number of different bias signals, to determine a functional compensation profile for an array of memory cells comprising a relationship between the different bias signals and the determined settling times of the multiple signal lines.

Abstract: A resistive memory device includes a resistive cell connected between a first bit line and a first source line, a reference cell including a reference resistor and connected between a second bit line and a second source line, and a write driver connected to the first bit line or the first source line, connected to the second bit line or the second source line. The write driver includes a comparator configured to compare previous data written in the resistive cell with the target data by comparing a voltage of the first source line with a voltage of the second source line or comparing a voltage of the first bit line with a voltage of the second bit line, and determine whether the target data is written in the resistive cell after comparing the previous data with the target data.

Abstract: A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.

Abstract: Embodiments of this application provide a method and system for adjusting a memory, and a semiconductor device. The method for adjusting a memory includes: acquiring a mapping relationship among a temperature of a transistor, a substrate bias voltage of a sense amplification transistor in a sense amplifier, and an actual data writing time of the memory; acquiring a current temperature of the transistor; and adjusting the substrate bias voltage on the basis of the current temperature and the mapping relationship, such that an actual data writing time corresponding to an adjusted substrate bias voltage is within a preset writing time.

Abstract: Disclosed is a memory structure that includes wordlines (WL) and cell supply lines (CSL) positioned between and parallel to voltage boost lines (VBLs). The VBLs enable capacitive coupling-based voltage boosting of the adjacent WL and/or CSL depending on whether a read or write assist is required. During a read operation, all VBLs for a selected row can be charged to create coupling capacitances with the WL and with the CSL and thereby boost both the wordline voltage (Vwl) and the cell supply voltage (Vcs) for a read assist. During a write operation, one VBL adjacent to the WL for a selected row can be charged to create a coupling capacitance with the WL only and thereby boost the Vwl for a write assist. The coupling capacitances created by charging VBLs in the structure is self-adjusting in that as the length of the rows increase so do the potential coupling capacitances.

Abstract: A circuit for testing a memory and a test method thereof are provided. According to the circuit for testing a memory provided by the present disclosure, a switch control circuit is connected between a discharge end and a negative bias signal end of a Sub Wordline Drive (SWD) and configured to input a trigger signal, so that potential of a Word Line (WL) signal end in a to-be-tested circuit meets a preset potential suspension range. Then, it is determined whether there is leakage behavior between the WL signal end and a Bit Line (BL) signal end in the to-be-tested circuit by detecting whether the present level state of a stored signal in the to-be-tested circuit is consistent with an initial level state. The to-be-tested circuit is a corresponding circuit in a single memory.

Abstract: A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.

Abstract: A word line driving circuit includes a driving circuit and a control circuit. The control circuit includes a control sub-circuit, a first switching sub-circuit and a second switching sub-circuit. The first switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a first power supply voltage, and a second terminal electrically connected with a third input terminal of the driving circuit. The second switching sub-circuit is provided with: a control terminal electrically connected with the control sub-circuit, a first terminal electrically connected with a second power supply voltage, and a second terminal electrically connected with the third input terminal of the driving circuit. The second power supply voltage is greater than a ground voltage.

Abstract: A semiconductor memory is provided. The semiconductor memory comprises a memory chip and a voltage regulation unit. The memory chip includes at least a storage array and the voltage regulation unit includes at least an operational amplifier. The voltage regulation unit is configured to convert an external input first voltage into a second voltage to be provided to a word line driver circuit associated with the memory chip. The first voltage is greater than the second voltage. According to the semiconductor memory provided, power consumption of the memory chip (or the semiconductor memory) is reduced and the second voltage provided to the word line driver circuit reaches a threshold voltage.

Abstract: Memory cell sensing by charge sharing between two sense nodes is disclosed. A first sense node and a second sense node are pre-charged and the second node is discharged initiating charge sharing between the first sense node and the second sense node that results in an improved sense margin. Sensing circuitry disclosed herein may include one or more pre-charge circuits, sense enable circuits, and charge-sharing circuits. The increased sense margin achieved by sensing circuitry disclosed herein provides better noise immunity and more accurate sensing results.

Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.

Abstract: Disclosed herein is an Artificial Intelligence (AI) processor. The AI processor includes multiple NVM AI cores for respectively performing basic unit operations required for a deep-learning operation based on data stored in NVM; SRAM for storing at least some of the results of the basic unit operations; and an AI core for performing an accumulation operation on the results of the basic unit operation.

Abstract: An integrated circuit can include latched comparator circuitry. The latched comparator circuitry may include first and second input transistors configured to receive an input signal, first and second cross-coupled inverting circuits, reset transistors, and a current pulse generator. The first and second inverting circuits may each include a pull-up transistor and a pull-down transistor. The first input transistor may be coupled between the pull-up and pull-down transistors in the first inverting circuit. The second input transistor may be coupled between the pull-up and pull-down transistors in the second inverting circuit. The reset transistors may be coupled in parallel with the pull-up transistors and may receive a clock signal. The current pulse generator may receive the clock signal and generate current pulse signals in response to detecting edges in the clock signal. Latched comparator circuitry configured and operated in this way can provide reduced clock kickback noise.

Abstract: A first bin boundary for a first voltage bin associated with a die of a memory device is identified. The first bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family is determined. The first bin boundary is updated based on the first bin boundary offset.

Abstract: A storage device is provided that performs constant biasing in priority blocks, such as OTP memory blocks (fuse ROM) and flash memory blocks having a threshold number of P/E cycles. The storage device includes an OTP memory, a flash memory, and a controller. The OTP memory includes a block having a word line and a plurality of cells coupled to the word line. The flash memory includes another block having a word line and a plurality of cells coupled to this word line. The controller is configured to apply a constant bias to the word line of the OTP memory block and, in some cases to the word line of the flash memory block, between execution of host commands. As a result, lower bit error rates due to wider Vt margins may occur while system power may be saved through selective application of constant biasing.

Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

Abstract: Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor.

Abstract: A method of peak power management (PPM) for a storage system with multiple memory dies is provided, where each of the multiple memory dies includes a PPM circuit having a PPM contact pad and PPM contact pads of the multiple memory dies are electrically connected. The PPM method includes the following steps: switching on a pull-down driver of the PPM circuit on a selected memory die of the storage system; verifying a PPM enablement signal regulated by a pull-down current flowing through the pull-down driver; and performing a peak power operation on the selected memory die when the PPM enablement signal indicates that a total current of the storage system is less than a maximum total current allowed for the storage system.

Abstract: A unit structure of non-volatile memory is provided. The unit structure includes a substrate, an n-type ferroelectric field effect transistor (FeFET) and a p-type FeFET disposed on the substrate, first circuitry by which sources of the n-type FeFET and the p-type FeFET are electrically coupled in parallel downstream from a common terminal and second circuitry by which top electrodes of the n-type FeFET and the p-type FeFET are electrically coupled in parallel upstream of a common terminal.

Abstract: A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said first transistors controls power delivery for at least one of said second transistor, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.

Abstract: An information handling system includes first and second memory modules, and a central processing unit. The first memory module includes one or more memory ranks of memory devices, and a first plurality of thermal sensors. The second memory module includes one or more memory ranks of memory devices, and a second plurality of thermal sensors. The central processing unit receives first thermal telemetry data for the first memory module from the first thermal sensors, and second thermal telemetry data for the second memory module from the second thermal sensors. In response to the reception of the first thermal telemetry data, the central processing unit determines a first localized temperature of a first memory rank. In response to the first localized temperature exceeding a threshold temperature, the central processing unit re-maps access of data from the first memory rank to a second memory rank.

Abstract: Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.

Abstract: According to an embodiment of the present disclosure, a memory device for a logic-in-memory may include a cell array including a plurality of ternary memory cells, a row decoder configured to select at least one ternary memory cell from among the plurality of ternary memory cells, and a page buffer configured to provide a first value to the at least one ternary memory cell and latch a third value obtained by performing a logic operation on the first value and a second value stored in the at least one ternary memory cell and/or the second value.

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a flash storage system. In an example, read commands or write commands can optionally include a file-type indicator. The file-type indicator can allow for exchange of data between the host and the flash storage system using a single record of a Flash Translation Layer (FTL) table or logical-to-physical (L2P) table, and where the amount of data can be much larger than the atomic unit associated with the flash storage system.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Abstract: A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.

Abstract: A power circuit is adapted for providing a programming voltage to an electronic fuse circuit, and includes a pass transistor of a P-type metal-oxide-semiconductor transistor, a buffer circuit, and a bulk voltage control circuit. The pass transistor includes a bulk electrode, a gate electrode, a first source/drain electrode receiving a system high voltage, and a second source/drain electrode connected to a bit line. The buffer circuit provides a control voltage to the gate electrode of the pass transistor. The pass transistor is turned on during a programming operation and turned off during a reading operation. The bulk voltage control circuit independently provides a bulk voltage to the bulk electrode. A last-stage buffer of the buffer circuit is also activated by the bulk voltage to control the pass transistor during the reading operation of the electronic fuse circuit. A method for providing power to an electronic fuse circuit is also provided.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.

Abstract: Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.

Abstract: A high-side driving circuit drives a high-side transistor configured as an N-channel or NPN transistor, according to an input signal. A level shift circuit level shifts the input signal. A latch stabilization circuit selects one node that corresponds to an output of the level shift circuit, from among a first node and a second node configured as complementary nodes provided to a latch circuit, and sinks a current from the node thus selected.

Abstract: A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.

Abstract: Methods, systems, and devices related to an improved driver for non-binary signaling are described. A driver for a signal line may include a set of drivers of a first type and a set of drivers of a second type. When the driver drives the signal line using multiple drivers of the first type, at least one additional driver of the first type may compensate for non-linearities associated with one or more other drivers of the first type, which may have been calibrated at other voltages. The at least one additional driver of the first type may be calibrated for use at a particular voltage, to compensate for non-linearities associated with the one or more other drivers of the first type as exhibited at that particular voltage.

Abstract: A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.

Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.

Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

Abstract: A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

Abstract: A memory device is provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.

Abstract: In some embodiments of the method, patterning the opening includes: projecting a radiation beam toward the second dielectric layer, the radiation beam having a pattern of the opening. In some embodiments of the method, the single-patterning photolithography process is an extreme ultraviolet (EUV) lithography process. In some embodiments of the method, filling the opening with the conductive material includes: plating the conductive material in the opening; and planarizing the conductive material and the second dielectric layer to form the first metal line from remaining portions of the conductive material, top surfaces of the first metal line and the second dielectric layer being planar after the planarizing.