Abstract: Various aspects relate to a method of manufacturing a memory cell, the method including: forming a memory cell, wherein the memory cell comprises a spontaneously-polarizable memory element, wherein the spontaneously-polarizable memory element is in an as formed condition; and carrying out a preconditioning operation of the spontaneously-polarizable memory element to bring the spontaneously-polarizable memory element from the as formed condition into an operable condition to allow for a writing of the memory cell after the preconditioning operation is carried out.

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract: A power supply device including a register circuit, an internal control circuit, and a storage circuit is disclosed. The register circuit includes a first sub-register circuit and a second sub-register circuit. The first sub-register circuit and the second sub-register circuit are configured to take turns to temporarily store a data transmitted form an external control circuit. The internal control circuit is coupled to the register circuit, and the internal control circuit is configured to obtain the data temporarily stored in the first sub-register circuit and the second sub-register circuit. The storage circuit is coupled to the internal control circuit, and the storage circuit is configured to obtain the data from the internal control circuit and to store the data.

Abstract: A flexible RAM loader including a shift register that includes a first data section coupled with a serial data input, and a second data section selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register comprising a selection bit to couple the second data section with the first parallel data input.

Abstract: A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.

Abstract: Embodiments of the present disclosure provide a system for testing multicore firmware (FW) in a memory system and a method thereof. A test system includes a test device and a storage device including a plurality of flash translation layer (FTL) cores, each FTL core associated with multiple memory blocks. The test device generates test preconditions for the plurality of FTL cores and provides the test preconditions to the plurality of FTL cores, the test preconditions being different from each other. Each of the plurality of FTL cores performs one or more test operations based on a corresponding test precondition of the test preconditions.

Abstract: There are provided a method for testing failure of a memory, an apparatus for testing failure of a memory, a computer-readable storage medium, and an electronic device. The method for testing failure of a memory includes: writing preset storage data into a storage array of the memory (S310); raising a bit line voltage, and controlling a part of word lines of the storage array to enter a test mode (S320); exiting the test mode after waiting for preset time (S330); turning off sense amplifiers corresponding to a preset part of bit lines, and reading data from a remaining part of the bit lines (S340); comparing the data read from the remaining part of the bit lines with the preset storage data to obtain a comparison result (S350); and determining a failure state of the memory according to the comparison result (S360).

Abstract: Devices, systems and methods for monitoring interconnect lines may include operations for transmitting, by a transmit block to a receive block, a first signal over a first interconnect line; executing, by the transmit block, a first transmit logic operation on the first signal with respect to a second signal, on at least one second interconnect line to generate a transmit signal; receiving, by the transmit block, a receive signal resulting from a receive logic operation executed by the receive block on a received first signal on the first interconnect line with respect to a received second signal received on at least one second interconnect line; executing, by the transmit block, a second transmit logic operation on the transmit signal with respect to the receive signal; and generating, by the transmit block and based on the executing of the second transmit logic operation, a result signal.

Abstract: A system on a chip includes a first subsystem comprising a first memory; a second subsystem comprising a second memory; and an always-on subsystem. The always-on subsystem can comprise processing circuitry configured to: in response to a first activation event, signal the first subsystem to initiate repair operations on the first memory, and in response to a second activation event occurring after the first event, signal the second subsystem to initiate repair operations on the second memory.

Abstract: A protection circuit can be applied in a chip, and include: a first protection unit and a first element to be protected, wherein the first protection unit is configured to receive a first input signal and a control signal, and is configured to output a first output signal, the first element to be protected includes a first P-type transistor, and a gate of the P-type transistor is configured to receive the first output signal. When the chip enters a burn-in test, the first output signal is a high-level signal.

Abstract: A test method for an alignment error includes: providing a substrate, wherein a first conductive layer and a second conductive layer are arranged on the substrate at intervals, and the first conductive layer and the second conductive layer are arranged in a first direction; acquiring a first distance; acquiring a first resistance of the first conductive layer and a second resistance of the second conductive layer; acquiring an actual distance between the first conductive layer and the second conductive layer according to the first distance, the first resistance, and the second resistance; and acquiring a value of the alignment error between the first conductive layer and the second conductive layer based on the actual distance and a standard distance between the first conductive layer and the second conductive layer.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes P groups of banks. P redundant banks are included in and shared by the P groups of banks. The I/O circuit is coupled to the P groups of banks and configured to direct P×N pieces of data to or from P×N working banks, respectively. The I/O control logic is configured to determine the P×N working banks from the P groups of banks based on bank fail information indicative of K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks. The I/O control logic is also configured to control the I/O circuit to direct P×N pieces of data to or from the P×N working banks, respectively.

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

Abstract: Methods, systems, and devices for non-destructive pattern identification at a memory device are described. A memory device may perform pattern identification within the memory device and output a flag indicating whether a first data pattern matches with a second data pattern. The memory device may access one or more memory cells, via a word line, and latch the second data pattern of the memory cells to a sense amplifier. The memory device may deactivate the word line, which may result in isolating the memory cells from potential destruction of data. The memory device may write a first data pattern to the sense amplifier and compare the first data pattern and second data pattern at the sense amplifier. The memory device may output a signal indicating whether the data patterns match.

Abstract: Embodiments provide a method for sense margin detection for a sense amplifier and an electronic device. The method includes: writing first data and second data respectively to a first memory cell and a second memory cell connected to a first bit line, the first memory cell and the second memory cell being respectively connected to a first word line and a second word line adjacent to each other, and the first bit line being connected to a first sense amplifier; performing a reverse write operation on the first memory cell and the second memory cell; performing write operations on memory cells connected to the second bit line; and reading the second memory cell, and determining the preset row precharge time to be a margin value of row precharge time of the first sense amplifier when the first data is not correctly read.

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

Abstract: The present disclosure provides a circuit for detecting leakage between word lines in a memory device. The circuit includes a first and a second coupling capacitor. A first terminals of the first and second coupling capacitors are connected to a first word line and a second word line, respectively. The first terminals of the first and second coupling capacitors are also connected to a first and a second voltage supply, respectively. The circuit further includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupling capacitor and a second input of the comparator is connected to a second terminal of the second coupling capacitor. The comparator is configured to send alarm signal when a differential voltage between the first input and the second input of the comparator is larger than a hysteresis level of the comparator.

Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

Abstract: A vehicle-to-X communication apparatus including: a reception device to receive a vehicle-to-X message; a first electronic computation device to calculate a hash value for a received vehicle-to-X message; and a second electronic computation device to generate a new vehicle-to-X message using data included in the received vehicle-to-X message and to calculate a hash value for the generated vehicle-to-X message. The first electronic computation device is designed in accordance with a higher safety integrity level than the second electronic computation device, and a comparison device to make a comparison between the hash value for the received vehicle-to-X message and the hash value for the generated vehicle-to-X message. The vehicle-to-X communication apparatus further processes the data from the received vehicle-to-X message depending on a result of the comparison. Also disclosed are a corresponding method and the use of the apparatus in a vehicle or an infrastructure device.

Abstract: An apparatus having a power bus supplying power to a component of a memory device. The apparatus includes a noise source circuit generating a plurality of noise source signals that simulate a real-world noise. The apparatus can include a pulse generator circuit that receives the noise source signal and outputs at least one noise profile signal based on the noise source signal. A bus shorting circuit can be connected to the pulse generator circuit to receive the at least one noise profile signal. The bus shorting circuit can have at least one transistor connected between a first rail and a second rail of the power bus. Based on the at least one noise profile signal, the bus shorting circuit intermittently connects the at least one transistor between the first rail to the second rail to induce noise on the power bus.

Abstract: A burn-in board for burn-in testing of semiconductor devices includes a strip socket mounted to a PCB. The strip socket includes a socket base configured to receive a device strip including an array of semiconductor devices, and a socket lid including at least one heating block. The socket lid is movable moved between (a) an open position allowing the device strip to be mounted on the socket base and (b) a closed position in which the socket lid including the heating block(s) is closed down on the mounted device strip. The strip socket includes conductive contacts configured to contact individual semiconductor devices on the device strip to allow selective monitoring of individual semiconductor devices during a burn-in test process. The burn-in board may also include heating control circuitry to control the heating block(s) during the burn-in test process.

Abstract: A semiconductor memory device includes a memory string, first wirings electrically connected to the memory string, second wirings electrically connected to the first wirings, transistors electrically connected between the first wirings and the second wirings, and a third wiring connected to gate electrodes of the transistors in common. The memory string includes memory transistors connected in series. Gate electrodes of the memory transistors are connected to the first wirings. The semiconductor memory device executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage that turns the transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation.

Abstract: A capacitor aging apparatus that includes continuity check pads configured to be electrically connected to positive electrodes of a plurality of capacitors in one-to-one correspondence to check electrical continuity with the plurality of capacitors a plurality of first terminals electrically connected to the plurality of continuity check pads; a plurality of second terminals electrically connected to the plurality of first terminals in one-to-one correspondence; and a plurality of connectors configured to be electrically connected to and disconnected from the plurality of first terminals and the plurality of second terminals, and configured to electrically connect the positive electrodes of the plurality of capacitors, the plurality of connectors each allowing a second terminal corresponding to one capacitor of corresponding two capacitors among the plurality of capacitors to be electrically connected to a first terminal corresponding to another capacitor.

Abstract: Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition.

Abstract: A non-volatile memory includes memory cells, word lines connected to the memory cells, and a set of regular control gate drivers connected to the word lines. The control gate drivers include different subsets of control gate drivers that receive different sources of voltage and provide different output voltages. A redundant control gate driver, that receives the different sources of voltage and provides the different output voltages, is included that can replace any of the regular control gate drivers.

Abstract: Preliminary program analysis of an executable may be performed. A security vulnerability level of a portion of the executable may be determined based on the preliminary program analysis. The security vulnerability level of the portion may be compared to a security vulnerability threshold. The precision of runtime monitoring of the portion may be tuned based on the comparison.

Abstract: A data writing method and a memory, in which the data writing method is used for writing data to a memory array of the memory. The data writing method includes that: old data is read from a target column of the memory array; the old data is updated according to data to be written which carries target data bits information to generate new data; and the new data is written into the target column, in which the memory includes a plurality of data columns, the data is required to be written into the target column, and the target column includes a part of the data columns.

Abstract: A dual reference voltage generator, an equalizer circuit, and a memory are provided. The dual reference voltage generator is configured to receive an original code, a first code and a second code, generate a first reference voltage according to the received original code and first code, and generate a second reference voltage according to the received original code and second code. The first reference voltage is different from the second reference voltage.

Abstract: A memory system includes non-volatile memory cells for storing multiple bit data and a controller configured to control to apply read voltages to the non-volatile memory cells at different threshold levels to read data written to the non-volatile memory cells. The non-volatile memory cells comprise different sub-groups. The controller stores first information indicating a first initial value for each of the different threshold level of the read voltages, second information that indicates whether data can be successfully read from each sub-group when the respective different threshold levels of the read voltages are set to the first initial values, and third information that indicates a second initial value for each different threshold level of the read voltages for at least one sub-group for which data reading was unsuccessful when a read voltage was set to the first initial value.

Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.

Abstract: One exemplary embodiment describes an integrated circuit, comprising a multiplicity of scan flip-flops, a multiplicity of ring oscillator circuits, wherein each ring oscillator circuit comprises a chain of logic gates comprising a plurality of logic gates connected in succession, an input multiplexer for the chain, and a feedback line from an output connection of the last logic gate of the chain to a data input connection of the input multiplexer. Each ring oscillator circuit is assigned a scan flip-flop group that contains at least one of the multiplicity of scan flip-flops.

Abstract: A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.

Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.

Abstract: Provided are a method for testing a memory, an apparatus for testing a memory, a computer-readable storage medium, and an electronic device, which relate to the field of integrated circuit technology. The method for testing a memory includes: writing first data into each of memory cells of a memory array; enabling a data mask mode, and writing second data into each of the memory cells of the memory array; enabling a leakage mode, and writing the first data into a memory cell corresponding to a column under test of the memory array; and after preset leakage time, disabling the leakage mode, and reading data from the memory cell corresponding to the column under test for testing, to determine whether there are at least two columns simultaneously turned on in the memory array. This method may test whether a row decoder fails.

Abstract: In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.

Abstract: Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

Abstract: The present disclosure provides a sense amplifier, a memory, and a data readout method, and relates to the field of semiconductor memory technologies. The sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first switch, a second switch, a third switch, and a fourth switch. During the offset compensation stage of the sense amplifier, the switching states of the first switch to the fourth switch are controlled so that the first NMOS transistor and the second NMOS transistor are configured to be in a cross-coupled amplification mode, and the first PMOS transistor and the second PMOS transistor are configured to be in a diode connection mode. The present disclosure enables to realize the offset compensation of the sense amplifier and improves the correctness of data readout by the memory.

Abstract: The present application relates to the technical field of integrated circuits, and in particular, to a memory test method and a memory test apparatus. The memory test method includes: providing a to-be-tested memory, where the to-be-tested memory includes a plurality of memory cells; alternately writing a first write value and a second write value into a memory cell of the memory cells at a preset frequency; writing a test write value into the memory cell; judging whether a data read from the memory cell is the test write value, and determining that a capacitance-frequency characteristic of the memory cell is abnormal if the data is not the test write value. According to the present application, the capacitance-frequency characteristic of the to-be-tested memory is accurately tested, to improve the field of memory products.

Abstract: A method comprises executing a testing operation on a plurality of redundant components of an edge device. In one example, based, at least in part, on the testing operation, at least one redundant component of the plurality of redundant components is identified as having an operational issue, and the at least one redundant component is deactivated in response to the identifying. One or more remaining redundant components of the plurality of redundant components are utilized in one or more operations following the testing operation.

Abstract: Embodiments of the present application provide a memory structure and a memory layout. The memory structure includes: memory arrays, each including a plurality of memory cells; read-write conversion circuits, each disposed between two adjacent ones of the memory arrays in a first direction, being arranged in a second direction, having a symmetry axis in the second direction, and configured to write external data into the memory cells, or read data from the memory cells, and the first direction being perpendicular to the second direction; sense amplification circuits, symmetrically disposed between two adjacent ones of the memory arrays based on the symmetry axis, coupled to the memory cells in the adjacent ones of the memory arrays; and bias contact point structures, disposed in gaps between the read-write conversion circuits, and configured to set a bias voltage of a well region where the bias contact point structures are located.

Abstract: Disclosed are devices, systems, apparatus, methods, products, and other implementations, including a method that includes determining whether an operation to access a memory location containing executable code comprises a general-purpose memory access operation, and changing content of the memory location in response to a determination that the operation to access the memory location containing the executable code comprises the general-purpose memory access operation to the memory location.

Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal receives at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage. The first data strobe signal is synchronized with the at least one first data signal, and is arranged to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

Abstract: A semiconductor device includes a test command generation circuit that generates a test write command and a test read command when entering a test mode, and an input/output control circuit that controls a memory block, the memory block including a plurality of banks such that write operations are simultaneously performed on the plurality of banks based on the test write command and read operations are simultaneously performed on the plurality of banks based on the test read command.

Abstract: A chip and a chip testing method are provided. The chip includes a sending terminal circuit and a test circuit. The sending terminal circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to a circuit node between the signal sending unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.

Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

Abstract: Techniques for usage metering by bias temperature instability with differential sensing on pairs of matching transistors are provided. In one aspect, a usage metering device includes: at least one metering circuit on a chip, the at least one metering circuit having a pair of matching transistors, and a differential current sense circuit connected to the pair of matching transistors, wherein the pair of matching transistors includes a reference transistor which is unused during regular operation of the chip, and a stressed transistor that is on continuously during the regular operation of the chip, and wherein the differential current sense circuit determines a Vt difference between the reference transistor and the stressed transistor. A method for usage metering and a method of forming a usage metering device are also provided.