Abstract: A refresh counter circuit, a refresh counting method and a semiconductor memory are provided. The refresh counter circuit includes: a first signal generator that is configured to generate a first carry signal according to each of refresh pulse signals generated by a received refresh command; a second signal generator that is configured to generate a second carry signal according to a last refresh pulse signal generated by the received refresh command; a first counter that is configured to perform signal inversion according to the first carry signal and generate a first output signal; and a second counter that is configured to count the refresh command according to the second carry signal and generate a second output signal; where the refresh command generates at least two refresh pulse signals.

Abstract: Various embodiments include a memory device that is capable of transferring both commands and data via a single clock signal input. In order to initialize the memory device to receive commands, a memory controller transmits a synchronization command to the memory device. The synchronization command establishes command start points that identify the beginning clock cycle of a command that is transferred to the memory device over multiple clock cycles. Thereafter, the memory controller transmits subsequent commands to the memory device according to a predetermined command length. The predetermined command length is based on the number of clock cycles needed to transfer each command to the memory device. Adjacent command start points are separated from one another by the predetermined command length. In this manner, the memory device avoids the need for a second lower speed clock signal for transferring commands to the memory device.

Abstract: A memory device includes: a memory cell array; a first latch; a second latch; a first circuit; and a second circuit. The memory cell array includes first, second, and third columns associated with first, second, and third addresses, respectively. The first latch stores the first address and is associated with a fourth address. The second latch stores the second address and is associated with a fifth address. The fourth address and the fifth address are in an ascending order. The first circuit selects the third column in place of the first column based on the first address. The second circuit determines whether or not the first address and the second address are in an ascending order.

Abstract: Methods, systems, and devices for operating memory cell(s) using an enhanced bit flipping scheme are described. An enhanced bit flipping scheme may include methods, systems, and devices for performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits. For instance, a flip bit that is even more reliable may be generated by determining whether a number of, a majority of, or all of the inversion bits indicate that the data bits are in an inverted state.

Abstract: Disclosed herein is an apparatus that includes a plurality of memory banks and a refresh controller configured to perform a refresh operation on one or more of the plurality of memory banks having a first state without performing the refresh operation on one or more of the plurality of memory banks having a second state responsive to a first refresh command, and perform the refresh operation on a selected one of the plurality of memory banks responsive to a second refresh command. The refresh controller is configured to bring the selected one of the plurality of memory banks into the second state when the refresh operation is performed responsive to the second refresh command.

Abstract: A semiconductor device includes a data input/output control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, the data input/output control block suitable for generating a control signal using the first and second voltages, a data input/output block including a third power gating circuit coupled to any one of the supply terminal of the first voltage and the supply terminal of the second voltage, the data input/output block suitable for inputting and outputting a data signal using the first and second voltages based on the control signal, and a memory block, coupled to the data input/output block, suitable for writing or reading the data signal.

Abstract: A method for testing a memory device includes the following steps of: generating a first refresh command to the memory device; storing a first refresh address information into a register of the memory device according to the first refresh command; reading out the first refresh address information according to a mode register read command; comparing the first refresh address information with an expectation address information to generate a comparison result; and generating a second refresh command to the memory device or screening out the memory device according to the comparison result.

Abstract: Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.

Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Abstract: A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Abstract: A storage controller is provided. The storage controller includes circuitry configured to utilize a format command to change a storage volume coupled to the storage controller from a first format to a second format and memory configured to store a data structure for first and second format indications for the storage volume. The storage controller determines if a selected band is initialized to the second format, and if the selected band is not initialized to the second format, the storage controller initializes the selected band to the second format and updates the data structure to indicate the selected band is initialized to the second format.

Abstract: Systems, apparatuses, and methods related to arithmetic operations in memory are described. The arithmetic operations may be performed using bit strings and within a memory array without transferring the bit strings to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings to be transferred from the memory array to the sensing circuitry. In addition to the arithmetic operations, the sensing circuitry can also perform a logical operation using the one or more bit strings.

Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.

Abstract: A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

Abstract: A semiconductor memory device includes a cell circuit including a plurality of cell dies arranged in a cell die stack. The semiconductor device also includes a control circuit configured to control the cell circuit, wherein the control circuit includes an address decoder and an address conversion circuit. The address decoder is configured to decode an address signal provided by a host and to output address information including a first address which identifies a first cell die, of the plurality of cell dies, requested by the host. The address conversion circuit is configured to convert the first address to a second address using the address information and to provide the second address to the cell circuit, wherein the second address is used to identify a second cell die of the plurality of cell dies different from the first cell die.

Abstract: An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z?X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for determining that an object implicated in an executing application is to be allocated to memory in an in-memory system, determining a type of the object, and allocating the object to one of a first size of virtual memory page and a second size of virtual memory page of an operating system based on the type of the object.

Abstract: User events are processed to estimate a unique user count. An identifier hash, having a bucket index portion denoting one of a plurality hash buckets, is generated for each of the user events. At a processing node, each of the user events is allocated to one of a plurality of processing threads based on the bucket index portion of its identifier hash. A unique user count is estimated as follows: for each user event satisfying at least one query parameter, 1) determine a run length of a second portion of its identifier hash, 2) compare it with a value of the hash bucket denoted by the bucket index portion of that identifier hash, and 3) if the determined run length is greater, change that hash bucket value at that node to match the determined run length. The hash bucket values are used to estimate the unique user count.

Abstract: Some embodiments provide a method for dynamically implementing quality of service (QoS) for machines of a network. The method identifies a QoS policy rule that defines a QoS policy to be implemented for machines that meet a set of criteria specified by the QoS policy rule. The method dynamically identifies a set of machines that meet the set of criteria. The method configures a set of managed forwarding elements of the network to implement the QoS policy rule for network traffic associated with the set of machines. In some embodiments, the method monitors network events (e.g., user logins, addition of new machines, etc.) and identifies a corresponding QoS policy rule to be enforced at corresponding locations in the network based on the detected event.

Abstract: A pipe latch circuit includes: a pipe latch control block suitable for controlling a plurality of pipe input signals and a plurality of pipe output signals to be activated sequentially or be divided into at least two groups and be activated sequentially by group, depending on a latency setting value, and outputting at least one pipe input signal and at least one pipe output signal; and a pipe latch block coupled between an input node and an output node, and suitable for storing data of the input node in response to the pipe input signal and outputting stored data to the output node in response to the pipe output signal.

Abstract: A microprocessor prepares a fused multiply-accumulate operation of a form ±A*B±C for execution by issuing first and second multiply-accumulate microinstructions to one or more instruction execution units to complete the fused multiply-accumulate operation. The first multiply-accumulate microinstruction causes an unrounded nonredundant result vector to be generated from a first accumulation of a selected one of (a) the partial products of A and B or (b) C with the partial products of A and B. The second multiply-accumulate microinstruction causes performance of a second accumulation of C with the unrounded nonredundant result vector, if the first accumulation did not include C. The second multiply-accumulate microinstruction also causes a final rounded result to be generated from the unrounded nonredundant result vector, wherein the final rounded result is a complete result of the fused multiply-accumulate operation.

Abstract: To produce output from a memory block, a first index is used to access a pointer, a mode select and a function select from a first memory. The pointer, the mode select and the function select are used to produce a second index. The pointer is used to produce the second index when the mode select is a first value. A function is used to produce the second index when the mode select is a second value. The function select identifies a function to be used to produce the second index. The second index is used to access output from a second memory.

Abstract: A memory controller includes a state shaping encoder that receives k-bit write data, selects a logical page with reference to state shape mapping information, and changes data of the logical page to decrease an occurrence probability of a high-order program state among program states used to program the k-bit data in multi-level memory cells.

Abstract: An NFA hardware engine includes a pipeline and a controller. The pipeline includes a plurality of stages, where one of the stages includes a transition table. Both a first automaton and a second automaton are encoded in the same transition table. The controller receives NFA engine commands onto the NFA engine and controls the pipeline in response to the NFA engine commands.

Abstract: A semiconductor memory device may include: a plurality of first to third memory cells, each memory cell being a DRAM memory cell; a plurality of fuses suitable for storing repair information for replacing failed first memory cells with corresponding second memory cells; a normal operation unit suitable for accessing and refreshing one or more of the first and second memory cells according to the repair information during a normal mode; and a repair operation unit suitable for providing the repair information from the fuses to the third memory cells during a boot-up mode, and for providing the repair information from the third memory cells to the normal operation unit and for refreshing the third memory cells during a normal mode.

Abstract: Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Abstract: A computational device maintains a first type of cache and a second type of cache. The computational device receives a command from the host to release space. The computational device synchronously discards tracks from the first type of cache, and asynchronously discards tracks from the second type of cache.

Abstract: A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.

Abstract: A memory device include a memory array, a transmitter suitable for outputting data to the outside of the memory device, and a data bus suitable for transmitting data of a selected memory cell in the memory array to the transmitter during a read operation. When successive read commands for the same memory cell are applied, data transmission from the memory array to the data bus is blocked, and data previously loaded in the data bus is outputted through the transmitter.

Abstract: A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit (which may include a programmable hash table) may multiply bit vectors representing key values by a bit matrix and add a constant bit vector to the results. Each hash value may be used to access a location in a lookup table in memory to obtain its contents (e.g., a key and associated data). The circuit may include a selection sub-circuit that selects the data of one of the identified locations as an output of the lookup circuit (e.g., one whose key matches the input key). The circuit may modify obtained data prior to its selection and may output a signal indicating the validity of input keys.

Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in a controller of the data storage device, a value of a particular write/erase (W/E) counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular W/E counter and that includes a storage element that is tracked by a particular cell erase counter of the set of counters. The method includes, in response to the value of the particular W/E counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory at least partially based on the value of the particular cell erase counter.

Abstract: A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The input of the analog-to-digital converter may be coupled to the bit-line, and the output of the analog-to-digital converter may be coupled to the digital filter.

Abstract: A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.

Abstract: A read voltage generation circuit includes a register unit configured to store an initial read voltage code, a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and a voltage generation circuit configured to generate a read voltage corresponding to a read voltage code produced by the counter circuit.

Abstract: A method of reading a nonvolatile memory device comprises applying a read voltage to a memory cell array to read selected memory cells, counting a number of the selected memory cells that have a threshold voltage higher or lower than the read voltage, and comparing the counted number with a reference value to determine a number of bits stored in the selected memory cells.

Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

Abstract: A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.

Abstract: Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.

Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized.

Abstract: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.

Abstract: A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.

Abstract: A semiconductor memory device includes a plurality of banks; a counting block suitable for counting the activation number of the respective banks, and selecting a bank of which the activation number is larger than or equal to a given number; and a refresh control block suitable for performing a normal refresh operation on the banks in response to a refresh command, and performing an additional refresh operation N times on the selected bank, N being a positive integer.

Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.

Abstract: A bit line power implementing circuit is provided, the bit line power implementing circuit has a bit line discharge oscillator to convert the supply voltage to a pulse; a decoder coupled to the bit line discharge oscillator to decode the pulse, and providing a first pulse with a first frequency and a second pulse with a second frequency; a first and a second counters, coupled to the decoder, and receiving the first and the second pulses respectively, and outputting a signal proportional to an average and a minimum read currents respectively; a divider outputting a read current ratio of the average read current to the minimum read current; and a multiplier for multiplying the supply voltage the read current ratio to output a bit line power consumption corresponding to the supply voltage.

Abstract: A method is provided for operating a nonvolatile memory comprising memory cells stacked on a substrate. The method comprises counting a number of program loops performed in a first program operation of selected memory cells connected to a selected wordline, and controlling an increment of a program voltage between successive program loops of a second program operation of the selected memory cells according to the counted number.

Abstract: A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

Abstract: A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program information from the memory area and determines whether to program pages according to the program information. The main memory controller determines whether the program information for a page is at a predetermined amount and if the corresponding page should be programmed again or not.

Abstract: A controlling method of a connector, the connector, and a memory storage device are provided. The controlling method includes following steps. A first clock signal generated by a first oscillator in the connector is obtained. A second clock signal generated by a second oscillator in the connector is obtained. A frequency shift of the first oscillator is smaller than a frequency shift of the second oscillator. A detection window information corresponding to the second clock signal is corrected according to the first clock signal and the second clock signal. The first oscillator is turned off. A signal stream including a first signal is received. A detection window is generated according to the corrected detection window information and the second clock signal, and whether the first signal is a burst signal is determined according to the detection window. Thereby, the power consumption of the connector is reduced.