Abstract: A signal transmission circuit and method for testing an integrated circuit (IC) are disclosed. The signal transmission circuit includes: an input circuit, configured to generate a first test signal in response to a first control signal and a clock signal; a transfer chain, including multiple stages of serially-connected transfer circuits, where adjacent transfer circuits in the transfer chain are connected via a through silicon via (TSV), the transfer circuit on one end of the transfer chain is connected to the input circuit, and the multiple stages of transfer circuits transfer the first test signal in stage by stage in response to the clock signal; and multiple signal output ends, where a first test signal input end of each stage of transfer circuit is correspondingly connected to one signal output end. The signal transmission circuit improves the effective utilization rate of a chip in an IC having a TSV test circuit.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes an operative memory device coupled to a bit-line. The operative memory device is configured to store a data state. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus includes one or more regulating MTJ devices that are configured to control a current provided to the operative memory device. The one or more regulating MTJ devices respectively include a free layer, a dielectric barrier layer on the free layer, and a pinned layer separated from the free layer by the dielectric barrier layer. The pinned layer covers a center of a surface of the dielectric barrier layer that faces the pinned layer.

Abstract: Examples described herein generally relate to forming and/or configuring a die stack in a multi-chip device. An example is a method of forming a multi-chip device. Dies are formed. At least two or more of the dies are interchangeable. Characteristics of the at least two or more of the dies that are interchangeable are determined. A die stack comprising the at least two or more of the dies that are interchangeable is formed. Respective placements within the die stack of the at least two or more of the dies that are interchangeable are based on the characteristics.

Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

Abstract: A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.

Abstract: A DIMM slot test system without series connection of test board through JTAG and a method thereof are disclosed. A DIMM connector interface of a test board is inserted to a DIMM slot of a circuit board under test, a CPU generates test data or a test signal based on a test signal with JTAG signal format, the CPU transmits test data to a specified CPLD chip through differential pins or IO pins, the specified CPLD chip records the received data as a test result; the CPU transmits the generated test signal to the specified CPLD chip, which then tests power pins or ground pins, reads and records values of the power pins or the ground pins as the test result; the CPU generates and transmits a test result read signal to the specified CPLD chip through the control pins, obtains the test result through data transmission pins.

Abstract: Methods, systems, and devices for debug capabilities of a memory system with a pin are described. An apparatus may include a memory system that includes a plurality of pins of a first type that are configured to communicate information as part of operating the memory system and a pin of a second type. The apparatus may also include a circuit coupled with the memory system, the circuit including a resistor that is coupled with the pin of the second type. The memory system may include a controller that selects a value for the resistor and generates a code as part of a memory management operation to determine one or more operating conditions of the memory system based on selecting the value. The memory system controller may also determine an error associated with the code based on generating the code and the selected value of the resistor.

Abstract: Combinations of resistive change elements and resistive change element arrays thereof are described. Combinational resistive change elements and combinational resistive change element arrays thereof are described. Devices and methods for programming and accessing combinations of resistive change elements are described. Devices and methods for programming and accessing combinational resistive change elements are described.

Abstract: A clock distribution system includes a clock mesh structure which has a plurality of first metal patterns extending along a first axis, a plurality of second metal patterns extending along a second axis, a plurality of third metal patterns extending along a third axis. The plurality of first metal patterns, the plurality of second metal patterns, and the plurality of third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis.

Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.

Abstract: A memory includes: a plurality of row lines; a plurality of column lines; and a plurality of memory cells each of which is coupled to one row line among the row lines and one column line among the column lines, wherein memory cells corresponding to a row line which is selected based on a row address among the row lines are simultaneously activated, and data are read from memory cells corresponding to column lines which are selected based on a column address among the activated memory cells, and the selected column lines are not adjacent to each other.

Abstract: A method of operating a memory circuit includes enabling a first row of select transistors, disabling a second row of select transistors, enabling a first row of memory cells in response to a first word line signal, and disabling a second row of memory cells in response to a second word line signal. Enabling the first row of select transistors includes turning on a first select transistor in the first row of select transistors in response to a first select line signal thereby electrically coupling a first local bit line and a global bit line to each other. Disabling the second row of select transistors includes turning off a second select transistor in the second row of select transistors in response to a second select line signal thereby electrically decoupling a second local bit line and the global bit line from each other.

Abstract: A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.

Abstract: A stack package includes a core die disposed over a package substrate, and a controller die disposed between the core die and the package substrate to control the core die. The core die includes banks each including memory cell arrays, an interbank region in which row decoders and column decoders are arranged, and a pad region in which first connection pads electrically connected to the row decoders and column decoders through first wirings are disposed. The controller die includes a through via region in which controller die through vias penetrating the controller die to be connected to the first connection pads are disposed, and a circuit region in which controlling circuitry electrically connected to the controller die through vias through second wirings is disposed.

Abstract: A restocking hub with interchangeable buttons mapped to item identifiers is described herein. In some instances, a local hub may receive an actuation signal from a particular interchangeable button communicatively coupled with the local hub. The actuation signal may include a button ID that identifies the particular interchangeable button and may indicating an actuation of the particular interchangeable button. The local hub may generate an order signal identifying the button ID based on the actuation signal, and may transmit the order signal instructing a remote server to perform a defined operation using the button ID. In some instances, the local hub may output a confirmation notification based on data received from the remote server based on the defined operation.

Abstract: A semiconductor memory device includes a substrate including a logic circuit, a memory cell array disposed over the substrate, a first conductive group including a plurality of bit lines and a first upper source line that are coupled to the memory cell array and spaced apart from each other and a first upper wire that is coupled to the logic circuit, an insulating structure covering the first conductive group.

Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

Abstract: An apparatus includes a controller adapted to be coupled to memory components in parallel and configured to provide memory address signals and a controller clock signal to the memory components, a memory enable logic circuit coupled to the controller and adapted to be coupled to the memory components in parallel and configured to provide test-enable signals to the memory components. The test-enable signals enable, with the controller clock signal, the memory components to read locally stored memory values. The apparatus includes a multiplexer adapted to be coupled to the memory components in parallel and configured to receive from the memory components memory signals that include the memory values in respective sequences of the memory clock signals, and a pipeline coupled to the multiplexer and the controller and configured to receive the memory values from the multiplexer and send the memory values to a multiple input signature register of the controller.

Abstract: Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to provide a unique instruction model based on triggers defined in metadata of the memory objects. This model represents a dynamic dataflow method of execution in which processes are performed based on actual dependencies of the memory objects. This provides a high degree of memory and execution parallelism which in turn provides tolerance of variations in access delays between memory objects. In this model, sequences of instructions are executed and managed based on data access. These sequences can be of arbitrary length but short sequences are more efficient and provide greater parallelism.

Abstract: A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces.

Abstract: Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and isolation material. Contact structures are formed to extend through the isolation material. Some of the contact structures are coupled to some of the digit lines, and some other of the contact structures are coupled to some of the word lines. Air gaps are formed to be interposed between the contact structures and the isolation material. An additional microelectronic device structure comprising control logic devices and additional isolation material is formed. After forming the air gaps, the additional microelectronic device structure is attached to the microelectronic device structure. Additional contact structures are formed to extend through the additional isolation material and to the contact structures. The additional contact structures are in electrical communication with the control logic devices.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array; a first insulating layer; and a passivation film. The memory cell array includes first interconnect layers and a first memory pillar. The first interconnect layers extend in a first direction substantially parallel to a semiconductor substrate. The first memory pillar passes through the first interconnect layers and extends in a second direction substantially perpendicular to the semiconductor substrate. The first insulating layer is provided above the memory cell array. The passivation film is provided on the first insulating layer, and includes a protrusion at least above the memory cell array and between the passivation film and the first insulating layer.

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

Abstract: Systems and methods are disclosed for side-channel attack mitigation for secure devices including cryptographic circuits using block ciphers that are not based upon feedback. For disclosed embodiments, an integrated circuit includes a cryptographic circuit and a controller. The cryptographic circuit performs cryptographic operations in a block cipher AES mode without feedback. The controller outputs control signals to the cryptographic circuit that cause the cryptographic circuit to perform the cryptographic operations on sequential data blocks with an internally permuted order to mitigate block cipher side-channel attacks. The internally permuted order can be generated using one or more random number generators, one or more pre-configured permutated orders, or other techniques.

Abstract: In a computer comprising multiple processing units, a method of exchanging read only elements between the processing units is described. The read only elements may be code or data, such as vector or matrix data for an AI graph. A master processing unit is identified. At compile time, at least one shareable read only element is allocated to the master processing unit. The at least one shareable read only element is stored in the local memory of the master processing unit. At compile time a transmitting exchange code sequence designated to be executed at the execution stage of the master processing unit is also allocated to the master processing unit. At a time point determined at compile time, the transmitting exchange code sequence causes the processing unit to identify the shareable read only element and to generate a message to be transmitted for reception by another processing unit, the message comprising the shareable read only data element.

Abstract: Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. Example memory devices, systems and methods include a multiplexer circuit to further facilitate use of slower, and wider bandwidth memory devices. Devices and methods described may be configured to substantially match the capacity of a narrower, higher speed host interface.

Abstract: A data storage system includes a plurality of memory dies and interface circuitry, including a receiver configured to receive pulses of a read clock signal; an I/O contact pad coupled to the receiver via a signal path of an interface channel; and on-die-termination (ODT) circuitry coupled to the I/O contact pad and the receiver. The ODT circuitry includes a plurality of resistor pairs, each including a pull-up resistor selectively coupled to the signal path via a first switch, and a pull-down resistor selectively coupled to the signal path via a second switch; and ODT control circuitry configured to enable ODT at the interface circuitry by causing each of the switches to be closed during a first stage of the read operation, and disable ODT at the interface circuitry by causing each of the switches to be open during a final stage of the read operation.

Abstract: A memory module is provided including a plurality of semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the plurality of semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group of the semiconductor memory devices and the second group of the semiconductor memory devices through a first transmission line and a second transmission line, respectively.

Abstract: An image sensor comprising a BJT pixel circuit, a biasing circuit and a comparator. The BJT pixel circuit comprises a BJT; a charging selection circuit, configured to control a first storage capacitor to be charged in a first reset time and to control a second storage capacitor to be charged to a second reset time; a discharging selection circuit, configured to control the first storage capacitor to be discharged by the BJT in a first exposure time to generate a first output voltage, and to control the second storage capacitor to be discharged by the BJT in a second exposure time to generate a second output voltage; a biasing circuit, configured to provide voltage decreasing and voltage increasing to the second output voltage to generated adjusted images; and a comparator, configured to compare the first output voltage and the adjusted voltages.

Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.

Abstract: A semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact plug CP1 which extends in the second area in the first direction and is connected to the logic circuit.

Abstract: A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.

Abstract: Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed at intersection regions of the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first and second directions; and a heat sink positioned between two memory cells adjacent to each other in a diagonal direction with respect to the first and second directions.

Abstract: An edge memory array mat with access lines that are split, and a bank of sense amplifiers formed under the edge memory array may in a region that separates the access line segment halves. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes access line connectors configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0?t1<t2.

Abstract: A system for clock management in an m columns×n rows array-based accelerators. Each row of the array may include a clock domain that clocks runtime clock cycles for the m processing elements. The clock domain includes a data detection and timing control circuit which is coupled to a common clock phase bus which provides a local clock source in multiple selectable phases, wherein the data detection and timing control circuit is configured to select a clock phase to clock a next clock cycle for a next concurrent data processing by the m processing elements. Each of m processing elements is coupled to access data from a first memory and a second memory and to generate respective outputs from each of the m processing elements to a corresponding m processing element of a same column in a subsequent neighboring row for the next processing in the next clock cycle.

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Abstract: A semiconductor device including a substrate having isolation films and active regions that are defined by the isolation films. The active regions extend in a first direction. A first trench is disposed on the substrate. Second trenches are disposed in the active regions. A filling film is disposed in the first trench. First gate patterns are disposed on the filling film in the first trench. Second gate patterns are disposed in the second trenches. The second gate patterns extend in a second direction that is different from the first direction. The filling film includes at least one material selected from a semiconductor material film and a metal.

Abstract: Detection accuracy of a collector sense in detecting a voltage is improved. A power module 300 has a first conductor 410 and a second conductor 411 to which a plurality of active elements 317 and 315 configuring upper and lower arm circuits are connected. In addition, the power module 300 has an AC side terminal 320B protruding from one side 301a, a positive electrode side terminal 315B and a negative electrode side terminal 319B which protrude from the other side 301b, an intermediate electrode portion 414 that connects the first conductor 410 and the second conductor 411 to each other, and a collector sense wiring 452a in which a collector electrode of an active element 157 and the first conductor 410 are connected to each other via a sense connection portion 415.

Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

Abstract: A representative system, apparatus, method and protocol are disclosed for data communication between chiplets or SOCs on a common interposer. A representative system comprises: an interposer; a first integrated circuit arranged on the interposer, the first integrated circuit comprising a first common protocol interface circuit; a communication link coupled to the first common protocol interface circuit; and a second integrated circuit arranged on the interposer, the second integrated circuit comprising a second common protocol interface circuit coupled to the communication link to form a serial protocol interface between the first common protocol interface circuit and the second common protocol interface circuit. Serial data and control packets and parallel data and control packets having specified, ordered fields are also disclosed.

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating an analog crossbar array. Embodiment include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a bit-length to represent the number. Embodiments also include selecting pulse positions in a pulse sequence having the bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described.