Abstract: A semiconductor device including a memory cell is provided. The memory cell comprises a transistor and a capacitor, and one of a resistor and a diode. A gate of the transistor is electrically connected to a word line, and one of a source and a drain of the transistor is electrically connected to a bit line. One terminal of the capacitor is electrically connected to the other of the source and the drain of the transistor, and the other terminal of the capacitor is electrically connected to a wiring. One terminal of one of the resistor and the diode is electrically connected to the other of the source and the drain of the transistor, and the other terminal of one of the resistor and the diode is electrically connected to the wiring.

Abstract: Apparatus, devices, systems, and methods are described that include filamentary memory cells. Mechanisms to substantially remove the filaments in the devices are described, so that the logical state of a memory cell that includes the that includes the removable filament can be detected. Additional apparatus, systems, and methods are described.

Abstract: A memelectronic device may have a first and a second electrode spaced apart by a plurality of materials. A first material may have a memory characteristic exhibited by the first material maintaining a magnitude of an electrically controlled physical property after discontinuing an electrical stimulus on the first material. A second material may have an auxiliary characteristic.

Abstract: Provide are a three-dimensional semiconductor device and a method of operating the same. the device may include a substrate, left, center, and right blocks provided on the substrate, and at least one decoding block provided between the left and center blocks and/or between the right and center blocks. The center block comprises first lines arranged to form a plurality of columns and a plurality of layers, and the at least one decoding block comprises a plurality of decoding groups, each of which is configured to selectively connect a corresponding one of the columns of the first lines to one of the left and right blocks.

Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Abstract: A multi-bit memory cell stores information corresponding to a high resistive state and multiple other resistive states lower than the high resistive state. A resistance of a memory element within the multi-bit memory cell switches from the high resistive state to one of the other multiple resistive states by applying a corresponding current to the memory element.

Abstract: In a semiconductor integrated circuit device, from a first power source strap supplying a potential to a first standard cell receiving a supply of the potential, the potential is supplied via a first cell power source line having a constant width. The width of the first cell power source line is determined in accordance with power consumed by the first standard cell and with the number of standard cells that can be placed between the first power source strap and a third power source strap.

Abstract: Negative differential resistance devices are implemented to facilitate current flow under different operating conditions. According to an example embodiment of the present invention, an NDR device is arranged for selective passage of current through relatively high tunneling efficiency regions and relatively low tunneling efficiency regions. In some applications, a gate is used to accumulate carriers to facilitate the passage of current that is predominantly one of tunneling current and generation current, respectively, by controlling the passage of current through a relatively high tunneling efficiency region and a relatively low tunneling efficiency region. In some implementations, the NDR device is arranged to mitigate leakage in a storage device using a two-terminal connection.

Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Abstract: A method of controlling a negative differential resistance (NDR) element is disclosed, which includes altering various NDR characteristics during operation to effectuate different NDR modes. By changing biasing conditions applied to the NDR element (such as a silicon based NDR FET) a peak-to-valley ratio (PVR) (or some other characteristic) can be modified dynamically to accommodate a desired operational change in a circuit that uses the NDR element. In a memory or logic application, for example, a valley current can be reduced during quiescent periods to reduce operating power. Thus an adaptive NDR element can be utilized advantageously within a conventional semiconductor circuit.

Abstract: A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Abstract: A multiple-level memory cell including a storage element formed of several polysilicon resistors connected in series between two input/output terminals; and a load in series with said resistive element, the midpoint of this series connection forming a read terminal of the memory cell, and the respective junction points of said resistors of the storage element being accessible.

Abstract: A method of operating a ferroelectric-type nonvolatile semiconductor memory comprising a memory unit having a bit line, a transistor for selection, a sub-memory unit composed of memory cells that are M in number, plate lines that are M in number, and a sense amplifier connected to the bit line; wherein each memory cell comprises a first electrode, a ferroelectric layer and a second electrode; the first electrodes of the memory cells constituting the sub-memory unit are in common with the sub-memory unit; said common first electrode is connected to the bit line through the transistor for selection; and each second electrode is connected to each plate line; said method comprising reading out data stored in the memory cell at a designated address externally designated, latching said data in the sense amplifier, and then outputting said data latched in the sense amplifier.

Abstract: A dynamically-operating restoration circuit (106) is used to apply a voltage or current restore pulse signal to thyristor-based memory cells (108) and therein restore data in the cell using the internal positive feedback loop of the thyristor (110). In one example implementation, the internal positive feedback loop in the thyristor (110) is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Abstract: A method for in-line testing of a chip to include multiple independent bit Flash memory devices, includes the steps of: grounding every other polysilicon line on the chip to emulate the multiple independent bit Flash memory devices, where an oxide line reside between every two polysilicon lines; scanning the polysilicon lines with an electron beam; examining voltage contrasts between the polysilicon lines; and determining if there are consecutively grounded polysilicon lines based on the voltage contrasts. If consecutive polysilicon lines appear to be grounded, then this indicates that a bridge defect exists between two of the consecutively grounded polysilicon lines. With this method, bridge defects in multiple independent bit Flash memory devices are better detected, leading to improved yield and reliability of the devices.

Abstract: A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an “on” state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and the bit line, and a second resistive element coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of the a TCCT based memory cell.

Abstract: A method of controlling a negative differential resistance (NDR) element is disclosed, which includes altering various NDR characteristics during operation to effectuate different NDR modes. By changing biasing conditions applied to the NDR element (such as a silicon based NDR FET) a peak-to-valley ratio (PVR) (or some other characteristic) can be modified dynamically to accommodate a desired operational change in a circuit that uses the NDR element. In a memory or logic application, for example, a valley current can be reduced during quiescent periods to reduce operating power. Thus an adaptive NDR element can be utilized advantageously within a conventional semiconductor circuit.

Abstract: A semiconductor memory device having a driver transistor for the supply of electric power is provided, which can diminish leakage current during inactivation while ensuring sufficient power supply capability for a sense amplifier during activation. Gate width is provided at every two bit line pair pitches perpendicularly to a bit line direction, and a supply voltage VDD and a reference voltage VSS are fed to PMOS transistors SP0, SP0_ to SP3, sP3_ and NMOS transistors SN0, SN0_ to SN3, SN3_. In driver-dedicated PMOS transistors P1, P2, and NMOS transistors N1, N2, gate width is adjusted using the length of two bit line pair pitches as a maximum value, while gate length is adjusted using an adjusting region &Dgr;L, whereby there can be obtained driver-dedicated MOS transistors P1, P2, N1, and N2 in an appropriately adjusted state with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and diminishing a tailing current.

Abstract: A semiconductor device including integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements, combined and formed on a common substrate. Thus, a variety of circuits, including logic and memory are implemented with a combination of conventional and NDR capable FETs. Because both types of elements share a number of common features, they can be fabricated with common processing operations to achieve better integration in a manufacturing facility.

Abstract: An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed. Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

Abstract: A negative resistance device (NRD) has a MOSFET-like structure, and is biased by shorting the gate and source together at a fixed applied potential and applying a different fixed potential to the drain, and sweeping the bulk potential towards the drain potential, causing the bulk current to exhibit a negative resistance characteristic. The NRD may be used in a memory circuit (10) in which a resistor (R) is connected between the bulk (2) and a fixed potential. Two States of the circuit at which the current through the resistor matches that through the bulk of the NRD are stable, providing for bistable memory operation.

Abstract: A two-dimensional memory comprises a matrix of multi-valued resonant tunneling diodes (RTD). Each memory cell has two series RTDs with hysteretic folding V-I characteristics. The memory state is determined by the node voltage between the two RTDs and the series current. Each memory cell has two terminals connected to two bit lines through word line switches. The two bit lines are fed with two sets of multi-valued data and are written into the cell by two consecutive pulses to set the operating point. The two sets of multi-valued data are converted by two D/A converters from two sub-words of the binary digital word. The memory state is read by the sensing the voltages at the two terminals, or voltage at one terminal and the current through the other terminal.

Abstract: A data storage device consisting of at least two series connected resonant tunneling diodes (RTD1, RTD2) with capacitors (C1 ,C2) coupled thereacross. By coupling a time varying voltage V(t) across the series connected diodes, one the diodes can be selectively switched from a state below its peak current to a stable point above its peak current. The diode which switches state is controlled by the slope of the time varying voltage V(t). Cells consisting of at least two or more resonant tunneling diodes may be connected in series and can store up to 2.sup.N binary states where N is the number of resonant tunneling diodes in the cell.

Abstract: A number of resonant tunneling diodes are connected in series with a resistor, a current source or a load device. A bit line is connected to every joint between any two devices through a switch. When properly biased, there can be (N+1).sup.m number of stable quantized operating points which are represented by a combination of m variables (of either voltage or current, where N is the number of peaks of the folding I-V characteristic and m is the number of bit lines. The m bit lines can write in (N+1).sup.m different combinations of inputs. During reading, the quantized voltage (or current) at each bit line is sensed. The number of stable states can be doubled by changing the polarity of the power supply.

Abstract: A memory cell for multi-valued logic utilizing bidirectional folding V-I characteristics. Two devices with bidirectional multiple folding characteristics, such as the V-I characteristics of resonant tunneling diodes, are connected in series across a power supply. Multiple stable operating points are established where the positive resistance portions the folding characteristics interesect and can be used to store multiple levels of signal. With bidirectional folding characteristics, the number of operating points can be doubled by using both a positive power supply and a negative power supply. The signal can be written in and read out at the connecting point of the two devices.

Abstract: A memory cell for multi-value logic. Two devices with multiple peak folding characteristics, such as the V-I characteristics of resonant tunneling diodes, are connected in series across a power supply. Multiple stable operating points are established where the positive resistance portions of the respective folding voltage-current characteristics intersect and correspond to multiple quantized levels for storing information, creating a multi-valued memory cell.