Magnetic Shift Registers Patents (Class 365/80)
  • Patent number: 11302373
    Abstract: A race track magnetic memory device includes a magnetic fine wire having a plurality of magnetic domains, a magnetic tunnel junction element comprising a pinned layer and an insulating layer, and a spin-orbit torque (SOT) generator. An easy axis of the magnetic fine wire is substantially perpendicular to a contact surface of the magnetic fine wire and the SOT generator. The magnetic tunnel junction element and the SOT generator are disposed on a magnetic domain write region of the magnetic fine wire. Data is written by generating spin-transfer torque at magnetization of the magnetic domain write region by flowing a first current in the magnetic tunnel junction element and by generating spin-orbit torque at the magnetization of the magnetic domain write region by flowing a second current in the SOT generator.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: April 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoshiaki Sonobe, Syuta Honda, Teruo Ono
  • Patent number: 11232822
    Abstract: According to one embodiment, a magnetic memory includes a magnetic body with two portions of a first dimension in a first direction which are spaced from each other a second direction and another portion that has a second dimension less than the first dimension in the first direction, which is between the two other portions. A circuit supplies a shift pulse to the magnetic body. The shift pulse includes a first pulse and a second pulse and moves a domain wall in the magnetic body along the second direction. The first pulse has a first pulse width. The second pulse has a second pulse width less than the first pulse width. The second pulse is supplied to the magnetic body after the first pulse.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: January 25, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Michael Arnaud Quinsat, Tsuyoshi Kondo, Masahiro Koike, Shiho Nakamura, Susumu Hashimoto, Masaki Kado, Nobuyuki Umetsu, Yasuaki Ootera, Megumi Yakabe, Agung Setiadi, Shigeyuki Hirayama, Yoshihiro Ueda, Tsutomu Nakanishi
  • Patent number: 10885961
    Abstract: A memory system includes a memory track including a plurality of magnetic domains having alternating magnetic polarities and positioned along a path, and a plurality of domain walls separating adjacent ones of the plurality of magnetic domains, each one of the domain walls being configured to store data.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dmytro Apalkov, Sebastian Schafer
  • Patent number: 10748589
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes first blocks each including magnetic memory lines and performs writing and reading of data for each block by a last-in first-out (LIFO) method by shifting, in a unit of a layer, data portions stored in a plurality of layers, respectively, in a first direction from a top layer to a last layer or in a second direction opposite to the first direction, the magnetic memory lines including the plurality of layers. The controller controls the nonvolatile memory. The controller selects a source block of a compaction process from the first blocks based on a ratio of layers of a second attribute to the plurality of layers in each of the first blocks.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hideki Yamada, Marie Takada, Masanobu Shirakawa, Naomi Takeda
  • Patent number: 10446249
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a first memory portion, and a controller. The first memory portion is provided between the first and second interconnects. The controller is electrically connected with the first and second interconnects. The first memory portion includes a first magnetic member, a first magnetic element, and a first non-linear element. The first magnetic element is provided between the first magnetic member and the second interconnect in a first current path between the first and second interconnects. The first non-linear element is provided between the first magnetic element and the second interconnect in the first current path. The controller is configured to supply a first shift current in the first current path in a first shift operation. The controller is configured to supply a first reading current in the first current path in a first reading operation.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Michael Arnaud Quinsat, Yasuaki Ootera, Tsuyoshi Kondo, Nobuyuki Umetsu, Takuya Shimada, Masaki Kado, Susumu Hashimoto, Shiho Nakamura, Hideaki Aochi, Tomoya Sanuki, Shinji Miyano, Yoshihiro Ueda, Yuichi Ito, Yasuhito Yoshimizu
  • Patent number: 10425078
    Abstract: A circuit for controlling a high-side power switch includes a level shifting circuit configured to receive an input signal for selectively configuring a logic command circuit to be in a set state, for providing a first output signal to the high-side power switch, and in a reset state, for providing a second output signal, different from the first output signal, to the high-side power switch. The circuit also includes a regulation circuit configured to detect an indicative signal indicative of the output signal provided to the high-side power switch and to change sensitivity of the level shifting circuit to the input signal, based on the indicative signal that is detected.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 24, 2019
    Assignee: Mosway Technologies Limited
    Inventor: On Bon Peter Chan
  • Patent number: 10276224
    Abstract: According to an embodiment, a magnetic memory includes a first magnetic portion, a second magnetic portion, a first nonmagnetic portion, and a controller. The first magnetic portion includes a first portion and a second portion. The controller in a first operation supplies a first current from the first portion toward the second portion. The controller in a second operation supplies a second current to from the second portion toward the first portion. A first electrical resistance value can be different from a second electrical resistance value. The first electrical resistance value is between the second magnetic portion and the portion of the first magnetic portion before the first operation and the second operation are performed. The second electrical resistance value is between the second magnetic portion and the portion of the first magnetic portion after the first operation and the second operation are performed.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Hirofumi Morise, Tsuyoshi Kondo, Nobuyuki Umetsu, Yasuaki Ootera, Susumu Hashimoto, Masaki Kado, Takuya Shimada, Michael Arnaud Quinsat, Shiho Nakamura
  • Patent number: 9659996
    Abstract: According to one embodiment, a magnetic memory element comprises a first magnetic unit, a second magnetic unit, a first insulating unit, a first electrode, a second electrode, and a third electrode. The first magnetic unit includes a plurality of magnetic domains. The second magnetic unit includes a first region and a second region. The first region includes a conductive material. The second region includes an insulating material. At least one of the first region or the second region is magnetic. The first insulating unit is provided between the first magnetic unit and the second magnetic unit. The first electrode and the second electrode are connected to the first magnetic unit. A part of the second magnetic unit and a part of the first insulating unit are provided between the third electrode and a part of the first magnetic unit.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: May 23, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Shimada, Hirofumi Morise, Shiho Nakamura, Tsuyoshi Kondo, Yasuaki Ootera, Michael Arnaud Quinsat
  • Patent number: 9653099
    Abstract: An information storage apparatus includes a magnetic track, a writer, and a reader, where the magnetic track includes a number of magnetic domains. Each magnetic domain is divided into at least two magnetic regions, and the writer is disposed on the magnetic track, and configured to write information to the at least two magnetic regions of each magnetic domain. The reader, disposed on the magnetic track, is configured to read the written information from the at least two magnetic regions. Therefore, multiple pieces of valid information are written to one magnetic domain of the magnetic track, thereby increasing storage density of the magnetic track, and expanding a storage capacity of the storage apparatus.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: May 16, 2017
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yinyin Lin, Yarong Fu, Kai Yang, Wei Yang, Yuangang Wang, Junfeng Zhao
  • Patent number: 9583212
    Abstract: A domain wall injector device uses electrical current passed across an interface between two magnetic regions whose magnetizations are aligned non-collinearly to create a domain wall or a series of domain walls in one of the magnetic regions. The method relies on a combination of innate fringing fields from the magnetic regions and the spin-transfer torque derived from the charge current. The device may be used to store data that are subsequently read out.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stuart P. Parkin, Timothy Phung, Aakash Pushp
  • Patent number: 9502090
    Abstract: A memory device comprising a ferromagnetic data nanowire, a ferromagnetic driver nanowire, read element and/or a spaced write element positioned about the data nanowire, wherein driving a domain wall in the driver nanowire remotely drives a domain wall in the data nanowire past the read element and/or the write element.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 22, 2016
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Wen Siang Lew, Indra Purnama, Chandra Sekhar Murapaka
  • Patent number: 9190168
    Abstract: A magnetic memory includes a first magnetic line, an electrode, a write-in portion, a second magnetic line, and a spin-wave generator. The first magnetic line has a plurality of magnetic domains and domain walls, the domain wall separating the magnetic domain. The electrode is provided to both ends of the first magnetic line. The write-in portion is provided adjacent to the first magnetic line. The second magnetic line is provided so that the second magnetic line intersects with the first magnetic line. The spin-wave generator provided to one end of the second magnetic line. The spin-wave detector provided to the other end of the second magnetic line.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shiho Nakamura, Tsuyoshi Kondo, Hirofumi Morise, Junichi Akiyama
  • Patent number: 9190167
    Abstract: A shift register according to an embodiment includes: a magnetic nanowire; a first control electrode group and a second control electrode group arranged with the magnetic nanowire being sandwiched therebetween, the first control electrode group including a plurality of first control electrodes arranged to be spaced apart from each other along a direction in which the magnetic nanowire extends, the second control electrode group including a plurality of second control electrodes arranged to be spaced apart from each other to correspond to the plurality of first control electrodes along the direction in which the magnetic nanowire extends, and the second control electrodes corresponding to the first control electrodes being shifted in the direction in which the magnetic nanowire extends; a first driving unit for driving the first control electrode group; and a second driving unit for driving the second control electrode group.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: November 17, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Hirofumi Morise
  • Patent number: 9184212
    Abstract: A magnetic storage element according to an embodiment includes: a magnetic nanowire having a cross-sectional area varying in a first direction, the magnetic nanowire having at least two positions where the cross-sectional area is minimal; first and second electrode groups having the magnetic nanowire interposed in between, the magnetic nanowire including at least one of a first region where the first electrodes overlap the second electrodes with the magnetic nanowire interposed in between and a second region where neither the first electrodes nor the second electrodes exist with the magnetic nanowire interposed in between, the magnetic nanowire including at least one of a third region where the first electrodes exist and the second electrodes do not exist with the magnetic nanowire interposed in between and a fourth region where the first electrodes do not exist and the second electrodes exist with the magnetic nanowire interposed in between.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: November 10, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirofumi Morise, Yoshiaki Fukuzumi, Shiho Nakamura, Tsuyoshi Kondo, Hideaki Aochi, Takuya Shimada
  • Patent number: 9171888
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic unit, a switching part, and a reading part. The magnetic unit includes a magnetic wire, and first and second magnetic parts. The magnetic wire includes magnetic domains and has one end and one other end. The first magnetic part is connected with the one end and has a first magnetization. The second magnetic part is connected with the one end, and has a second magnetization. The switching part includes first and second switches. The first switch is connected with the first magnetic part and flows a first current between the first magnetic part and the magnetic wire. The second switch is connected with the second magnetic part and flows a second current between the second magnetic part and the magnetic wire. The reading part is configured to read a magnetization of the magnetic domains.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michael Arnaud Quinsat, Tetsufumi Tanamoto, Shiho Nakamura
  • Patent number: 9042151
    Abstract: Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Marcin J. Gajek
  • Patent number: 8995163
    Abstract: A magnetic memory according to an embodiment includes: a magnetic layer including a plurality of magnetic domains and a plurality of domain walls, and extending in a direction; a pinning layer formed with nonmagnetic phases and magnetic phases, extending in an extending direction of the magnetic layer and being located adjacent to the magnetic layer; an electrode layer located on the opposite side of the pinning layer from the magnetic layer; an insulating layer located between the pinning layer and the electrode layer; a current introducing unit flowing a shift current to the magnetic layer, the shift current causing the domain walls to shift; a write unit writing information into the magnetic layer; a read unit reading information from the magnetic layer; and a voltage generating unit generating a voltage to be applied between the pinning layer and the electrode layer.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shiho Nakamura, Hirofumi Morise, Tsuyoshi Kondo
  • Patent number: 8902626
    Abstract: A method of pinning magnetic domain walls in magnetic domain shift registers includes pinning the magnetic domain walls at a plurality of pinning sites in a nanowire, reducing an energy of the pinning of the magnetic domain walls and shifting the magnetic domain walls in the nanowire by applying a shift current in a control wire adjacent the nanowire.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Publication number: 20140268982
    Abstract: Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire.
    Type: Application
    Filed: August 13, 2013
    Publication date: September 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Marcin J. Gajek
  • Publication number: 20140268981
    Abstract: Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Marcin J. Gajek
  • Patent number: 8830718
    Abstract: A magnetic memory includes a magnetic wire, a first insulating layer, first electrodes a second electrode, a current supplying module, and a voltage applying module. The magnetic wire includes a first portion and a second portion, has a first electric resistance value, and is configured to form magnetic domains. The first electrodes are formed on the first insulating layer, arranged along the magnetic wire, and spaced from each other. The second electrode includes a third portion and a fourth portion. The second electrode is electrically connected to the first electrodes between the third portion and the fourth portion and has a second electric resistance value being larger than the first electric resistance value. The current supplying module is configured to supply the magnetic wire with a pulse current. The voltage applying module is configured to apply a voltage that decreases with time.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Kondo, Hirofumi Morise, Shiho Nakamura
  • Publication number: 20140241030
    Abstract: A shift register according to an embodiment includes: a magnetic nanowire; a first control electrode group and a second control electrode group arranged with the magnetic nanowire being sandwiched therebetween, the first control electrode group including a plurality of first control electrodes arranged to be spaced apart from each other along a direction in which the magnetic nanowire extends, the second control electrode group including a plurality of second control electrodes arranged to be spaced apart from each other to correspond to the plurality of first control electrodes along the direction in which the magnetic nanowire extends, and the second control electrodes corresponding to the first control electrodes being shifted in the direction in which the magnetic nanowire extends; a first driving unit for driving the first control electrode group; and a second driving unit for driving the second control electrode group.
    Type: Application
    Filed: July 5, 2013
    Publication date: August 28, 2014
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Hirofumi Morise
  • Publication number: 20140204647
    Abstract: A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.
    Type: Application
    Filed: January 21, 2013
    Publication date: July 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Anthony J. Annunziata
  • Publication number: 20140204648
    Abstract: A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.
    Type: Application
    Filed: August 20, 2013
    Publication date: July 24, 2014
    Applicant: International Business Machines Corporation
    Inventor: Anthony J. Annunziata
  • Patent number: 8787062
    Abstract: A magnetic domain wall shift register memory device includes a nanowire, a plurality of pinning sites disposed along the nanowire and a control line arranged substantially parallel to the nanowire and configured to support a current.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Patent number: 8750013
    Abstract: Methods for writing include applying a current pulse to a racetrack memory medium to position a domain in proximity to a thermally triggered magnon source in contact with the racetrack memory medium; activating a heat source/sink in contact with the magnon source to create a thermal gradient in the magnon source, generating a magnon flow in the magnon source; and changing a magnetization in the racetrack memory medium by spin torque transfer from the magnon flow.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Anthony J. Annunziata
  • Patent number: 8750012
    Abstract: Racetrack memory units and methods for writing include a racetrack memory medium; a heat source/sink configured to change temperature according to an applied current; and a magnon source material in contact with the racetrack memory medium and the heat source/sink, such that a temperature of the heat source/sink causes a magnon flow in the magnon source material that injects a domain wall in the racetrack memory medium.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Anthony J. Annunziata
  • Patent number: 8743584
    Abstract: A shift register memory according to the present embodiment includes a magnetic pillar including a plurality of magnetic layers and a plurality of nonmagnetic layers provided between the magnetic layers adjacent to each other. A stress application part applies a stress to the magnetic pillar. A magnetic-field application part applies a static magnetic field to the magnetic pillar. The stress application part applies the stress to the magnetic pillar in order to transfer magnetization states of the magnetic layers in a stacking direction of the magnetic layers.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 8687414
    Abstract: A magnetic memory cell includes: a magnetization recording layer; and a magnetic tunneling junction section. The magnetization recording layer includes a ferromagnetic layer with perpendicular magnetic anisotropy. The magnetic tunneling junction section is used for reading information in the magnetization recording layer. The magnetization recording layer includes two domain wall moving areas.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: April 1, 2014
    Assignee: NEC Corporation
    Inventors: Kiyokazu Nagahara, Shunsuke Fukami, Nobuyuki Ishiwata, Tetsuhiro Suzuki, Norikazu Ohshima
  • Patent number: 8649214
    Abstract: A magnetic memory includes magnetic memory elements corresponding to magnetic memory cells and at least one shift register. Each magnetic memory element includes a pinned layer, a free layer, and a nonmagnetic spacer layer between the pinned and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic memory element. The shift register(s) correspond to the magnetic memory elements. Each shift register includes domains separated by domain walls. A domain is antiparallel to an adjoining domain. The shift register(s) are configured such that an equilibrium state aligns a portion of the domains with the magnetic memory elements. The shift register(s) are also configured such that each domain wall shifts to a location of an adjoining domain wall when a shift current is passed through the shift register(s) in a direction along adjoining domains.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dmytro Apalkov, Vladimir Nikitin, Alexey Vasilyevitch Khvalkovskiy
  • Patent number: 8638601
    Abstract: Magnetic wires that include cobalt, nickel, and platinum layers show improved domain wall motion properties, when the domain walls are driven by pulses of electrical current. These wires exhibit perpendicular magnetic anisotropy, thereby supporting the propagation of narrow domain walls. The direction of motion of the domain walls can be influenced by the order in which the platinum and cobalt layers are arranged.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stuart Stephen Papworth Parkin, Luc Thomas, See-Hun Yang
  • Publication number: 20140009994
    Abstract: Magnetic wires that include two antiferromagnetically coupled magnetic regions show improved domain wall motion properties, when the domain walls are driven by pulses of electrical current. The magnetic regions preferably include Co, Ni, and Pt and exhibit perpendicular magnetic anisotropy, thereby supporting the propagation of narrow domain walls. The direction of motion of the domain walls can be influenced by the order in which the wire's layers are arranged.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: STUART STEPHEN PAPWORTH PARKIN, LUC THOMAS, SEE-HUN YANG
  • Publication number: 20140009993
    Abstract: Magnetic wires that include cobalt, nickel, and platinum layers show improved domain wall motion properties, when the domain walls are driven by pulses of electrical current. These wires exhibit perpendicular magnetic anisotropy, thereby supporting the propagation of narrow domain walls. The direction of motion of the domain walls can be influenced by the order in which the platinum and cobalt layers are arranged.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: STUART STEPHEN PAPWORTH PARKIN, LUC THOMAS, SEE-HUN YANG
  • Publication number: 20140003117
    Abstract: A magnetic domain wall shift register memory device includes a nanowire, a plurality of pinning sites disposed along the nanowire and a control line arranged substantially parallel to the nanowire and configured to support a current.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Publication number: 20140003118
    Abstract: A magnetic domain wall shift register memory device includes a nanowire and a magnetic reference layer island disposed on the nanowire, wherein an interface between the nanowire and the magnetic tunnel junction island is a magnetic tunnel junction aligned with a width of the nanowire.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Publication number: 20140003119
    Abstract: A method of pinning magnetic domain walls in magnetic domain shift registers includes pinning the magnetic domain walls at a plurality of pinning sites in a nanowire, reducing an energy of the pinning of the magnetic domain walls and shifting the magnetic domain walls in the nanowire by applying a shift current in a control wire adjacent the nanowire.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 2, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Michael C. Gaidis
  • Patent number: 8580408
    Abstract: An apparatus for moving a magnetic domain wall and a memory device using a magnetic field application unit are provided. The apparatus for moving a magnetic domain wall includes a magnetic layer having a plurality of magnetic domains; current supply units that are disposed on both sides of the magnetic layer and supply current to the magnetic layer; and a magnetic field application unit that is disposed on at least one surface of the magnetic layer and applies a magnetic field to the magnetic layer.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-su Kim, Sung-chul Lee
  • Publication number: 20130294138
    Abstract: A shift register memory device includes a shift register, program/read element, and rotating force application unit. The shift register includes plural rotors arranged along a direction with uniaxial anisotropy. Each rotor has a characteristic direction rotatable around a rotational axis extending in the direction. The program/read element can program data to the shift register by matching the characteristic direction of one of the rotors to one selected from two directions conforming to the uniaxial anisotropy and to read data by detecting the characteristic direction. The rotating force application unit can apply a rotating force to the shift register to urge the characteristic direction to rotate. The rotors are organized into plural pairs of every two adjacent rotors. Respective first and second forces urge the characteristic directions to be opposingly parallel for two rotors of the same pair and for two mutually adjacent rotors of mutually adjacent pairs.
    Type: Application
    Filed: April 5, 2013
    Publication date: November 7, 2013
    Inventor: KABUSHIKI KAISHA TOSHIBA
  • Publication number: 20130242634
    Abstract: A shift register memory according to the present embodiment includes a magnetic pillar including a plurality of magnetic layers and a plurality of nonmagnetic layers provided between the magnetic layers adjacent to each other. A stress application part applies a stress to the magnetic pillar. A magnetic-field application part applies a static magnetic field to the magnetic pillar. The stress application part applies the stress to the magnetic pillar in order to transfer magnetization states of the magnetic layers in a stacking direction of the magnetic layers.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 19, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki FUKUZUMI, Hideaki Aochi
  • Publication number: 20130155754
    Abstract: A magnetic memory is described. The magnetic memory includes magnetic memory elements corresponding to magnetic memory cells and at least one shift register. Each magnetic memory element includes a pinned layer, a free layer, and a nonmagnetic spacer layer between the pinned and free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic memory element. The shift register(s) correspond to the magnetic memory elements. Each shift register includes domains separated by domain walls. A domain is antiparallel to an adjoining domain. The shift register(s) are configured such that an equilibrium state aligns a portion of the domains with the magnetic memory elements. The shift register(s) are also configured such that each domain walls shifts to a location of an adjoining domain wall when a shift current is passed through the shift register(s) in a direction along adjoining domains.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 20, 2013
    Applicant: Samsung Electronics Co., LTD.
    Inventors: Dmytro Apalkov, Vladimir Nikitin, Alexey Vasilyevitch Khvalkovskiy
  • Patent number: 8467221
    Abstract: A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Joseph, Stuart S. P. Parkin, Mary B. Rothwell
  • Patent number: 8467222
    Abstract: A reader for magnetic shift register is provided. The reader includes a magnetic reference layer, a tunneling layer, a magnetic canceling layer and an isolated layer. The magnetic reference layer and the magnetic canceling layer are respectively configured at different sides of a magnetic track for providing anti-parallel magnetic fields. The magnetic reference layer overlaps the magnetic canceling layer in a perpendicular direction of the magnetic track. The magnetic reference layer electrically connects to a readout circuit. The magnetic canceling layer is floating. The tunneling layer is configured between the magnetic reference layer and the magnetic track for providing a magnetic tunnel junction (MTJ). The isolated layer is configured between the magnetic canceling layer and the magnetic track for avoiding a current in the magnetic track from tunneling to the magnetic canceling layer.
    Type: Grant
    Filed: October 30, 2011
    Date of Patent: June 18, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Kuei-Hung Shen, Ching-Hsiang Tsai
  • Patent number: 8437160
    Abstract: Provided is a multi-stack memory device that includes a storage unit group including a plurality of storage units that are vertically stacked and form a plurality of storage unit rows, and a plurality of transistors connected to the storage unit group, wherein the transistors that are connected to the storage units which are included in at least two rows of the plurality of the storage unit rows and are connected by a common wire. The common wire may be a gate line or a bit line.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: May 7, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Sung-hoon Choa, Young-jin Cho, Kee-won Kim
  • Patent number: 8437167
    Abstract: According to one embodiment, a shift register memory device includes a shift register, a program/read element, and a rotating force application unit. The shift register includes a plurality of rotors arranged along one direction and provided with a uniaxial anisotropy. Each of the plurality of rotors has a characteristic direction rotatable around a rotational axis extending in the one direction. The program/read element is configured to program data to the shift register by causing the characteristic direction of one of the rotors to match one selected from two directions conforming to the uniaxial anisotropy and configured to read the data by detecting the characteristic direction. The rotating force application unit is configured to apply a rotating force to the shift register to urge the characteristic direction to rotate. The plurality of rotors are organized into a plurality of pairs of every two mutually adjacent rotors.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 8406029
    Abstract: In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: March 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-jung Kim, Chul-woo Park, Sang-beom Kang, Jong-wan Kim, Hyun-ho Choi, Young-pil Kim, Sung-chul Lee
  • Patent number: 8379429
    Abstract: A domain wall motion element has a magnetic recording layer 10 that is formed of a ferromagnetic film and has a domain wall DW. The magnetic recording layer 10 has: a pair of end regions 11-1 and 11-2 whose magnetization directions are fixed; and a center region 12 sandwiched between the pair of end regions 11-1 and 11-2, in which the domain wall. DW moves. A first trapping site TS1 by which the domain wall DW is trapped is formed at a boundary between the end region 11-1, 11-2 and the center region 12. Furthermore, at least one second trapping site TS2 by which the domain wall DW is trapped is formed within the center region 12.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: February 19, 2013
    Assignee: NEC Corporation
    Inventors: Nobuyuki Ishiwata, Tetsuhiro Suzuki, Norikazu Ohshima, Kiyokazu Nagahara, Shunsuke Fukami
  • Publication number: 20130033917
    Abstract: A reader for magnetic shift register is provided. The reader includes a magnetic reference layer, a tunneling layer, a magnetic canceling layer and an isolated layer. The magnetic reference layer and the magnetic canceling layer are respectively configured at different sides of a magnetic track for providing anti-parallel magnetic fields. The magnetic reference layer overlaps the magnetic canceling layer in a perpendicular direction of the magnetic track. The magnetic reference layer electrically connects to a readout circuit. The magnetic canceling layer is floating. The tunneling layer is configured between the magnetic reference layer and the magnetic track for providing a magnetic tunnel junction (MTJ). The isolated layer is configured between the magnetic canceling layer and the magnetic track for avoiding a current in the magnetic track from tunneling to the magnetic canceling layer.
    Type: Application
    Filed: October 30, 2011
    Publication date: February 7, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuei-Hung Shen, Ching-Hsiang Tsai
  • Patent number: 8351235
    Abstract: A feedback circuit by which an output of a memory device for storing level-shifted data can be fed back to the input side includes inverters, resistors, and transistors. The resistance value of combined resistance for pulling up or down first and second switching devices is varied in accordance with the output of the memory device by the feedback circuit, so that malfunction caused by dv/dt noise can be dealt with out generating any through current. In this manner, it is possible to provide a level shift circuit which can deal with malfunction causing dv/dt noise regardless of an on or off state of a high-potential-side switching device, while generation of a through current can be suppressed.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: January 8, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Masashi Akahane
  • Patent number: 8331125
    Abstract: A high density memory architecture comprising magnetic racetrack memory and a method of operation. The memory architecture comprises a plurality of magnetic memory structures, each the structure formed of magnetic material; a sensing device associated with each magnetic memory structure; first decoder device initiating a track select signal for activating a single magnetic memory structure from among the plurality to perform a bit read or bit storage operation; a bit drive device for applying a first signal to form a new magnetic memory domain associated with a bit value to be stored in the activated magnetic memory structure at a first position thereof during a bit storage operation; and, a second decoder applying a second signal for advancing each the formed magnetic memory domain toward a second position of the activated memory structure. The sensing device reads a memory bit value stored at a magnetic domain at the second position of the activated memory structure.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: December 11, 2012
    Assignee: International Business Machines Corporation
    Inventor: John K. DeBrosse
  • Patent number: 8320152
    Abstract: An information storage device includes a storage node, a write unit configured to write information to a first magnetic domain region of the storage node, and a read unit configured to read information from a second magnetic domain region of the storage node. The information storage device further includes a temporary storage unit configured to temporarily store information read by the read unit, and a write control unit electrically connected to the temporary storage unit and configured to control current supplied to the write unit. The information read from the second magnetic domain region is stored in the temporary storage unit and written to the first magnetic domain region.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: November 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jin Cho, Hyung-soon Shin, Seung-jun Lee, Sun-ae Seo, Sung-chul Lee, Ji-young Bae