Abstract: A pulse generator comprising: a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; and a controller arranged to activate the plurality of switching elements in a predetermined sequence so as to generate a predetermined pulse waveform at a pulse generator output. The switching elements of the signal generating arm and the inductor together form a pulse synthesizer that takes the signal from the controller and uses it to synthesize an output pulse. Compared with conventional transmitter architectures, the functions of the upconversion mixer, the DAC, and the power amplifier are all performed by a single simplified circuit. This is both area efficient and power efficient.

Abstract: Method and Apparatuses for of transmitting data between semiconductor chips are described. An example apparatus includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes first and second inductors. The first semiconductor chip transmits a first combination of a plurality of data bits in logical value by flowing a first current through the first inductor and by flowing substantially no current through the second inductor. The second semiconductor chip includes third and fourth inductors that correspond respectively to the first and second inductors of the first semiconductor chip. The second semiconductor chip receives the first combination of the plurality of data bits in logical value by detecting an electromotive force at the third inductor responsive to the first current and by detecting substantially no electromotive force at the fourth inductor responsive to no current.

Abstract: A differential receiver for receiving differential signals including a positive signal and a negative signal and generating an output signal is provided. The differential receiver includes a first comparator configured to compare the positive signal and the negative signal and generate a first signal that is asserted when a difference between the positive signal and the negative signal is larger than a positive offset voltage; a second comparator configured to compare the positive signal and the negative signal and generate a second signal that is asserted when the difference between the positive signal and the negative signal is smaller than a negative offset voltage; a logic gate configured to generate a third signal that is asserted when the first signal and the second signal are negated; and an output circuit configured to generate the output signal based on the first to third signals.

Abstract: Digital information is communicated between stacked integrated circuit devices by inductive coupling between arrays of inductors formed from integrated circuit wiring layers. This can be done using a combination of push-pull drivers, common inductor return legs, and balanced sparse ternary encoding. Embodiments result in low power utilization and high pin efficiency.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: A signal processor, which includes: a signal receiving section for receiving signals encoded under a predetermined code rule; a rule violation detecting section for detecting code rule violation included in the signals received by the signal receiving section; an error range specifying section for specifying a range in which an error bit is included out of a bit string which constitutes the signals on the basis of a position of the code rule violation detected by the rule violation detecting section; and an error correcting section for correcting one error bit in the range specified by the error range specifying section so that the code rule violation detected by the rule violation detecting section is eliminated.

Abstract: A method of processing data is provided that includes receiving a plurality of binary electronic signals and generating an optical signal by a number of lasers that is equal to or greater than the number of binary electronic signals. The optical signal is generated at one of a plurality of intensity levels, and each intensity level represents a particular combination of bit values for the plurality of binary electronic signals. The optical signal is converted into an electronic signal having the plurality of intensity levels. An apparatus for processing data is provided that includes a plurality of lasers configured to emit light at a plurality of frequencies, and a plurality of modulators configured to receive a plurality of binary electronic signals and to modulate the light emitted by the lasers. An apparatus for transmitting data is provided that includes a photo receiver and an electronic signal generator.

Abstract: A method, apparatus, and electronic device for using digital predistortion are disclosed. A transmitter 212 may transmits a transmission signal. A receiver 214 may monitor the transmission signal to execute digital predistortion of the transmission signal to compensate for distortion. A field programmable gate array or application specific integrated circuit 226 may adjust a power amplifier bias to improve the digital predistortion.

Abstract: In a provided information processing device, a first information processing module, within its transmission time segment, transmits an encoded signal in which mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the same amplitude value not occurring consecutively and the amplitude value polarity being inverted with each cycle. Within a transmission time segment for a second information processing module, the first information processing module transmits a clock signal that corresponds to the cycle at which the polarity is inverted.

Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: An encoding apparatus that converts input digital data and an input clock into three-bit six-state transition encode outputs and outputs them is disclosed. The encoding apparatus has a first state transition control section, second state transition control section, and an output selection section. The first state transition control section changes a state of first data at a positive edge of the input clock. The second state transition control section changes a state of second data at a negative edge of the input clock. The output selection section alternately selects the state of the first state transition control section and the second state transition control section.

Abstract: Wired/wireless optical signal modulation and demodulation apparatuses and methods using an intensity modulation/direct detection method and an orthogonal frequency division multiplexing (OFDM) method are provided. A unipolar OFDM symbol frame is generated by determining the polarity of each of a plurality of sub-frames of a bipolar OFDM symbol frame which comprises both a plurality of positive pulses and a plurality of negative pulses, inverting the polarity of the sub-frames which are determined to be negative, delaying one of the positive sub-frame and a positive sub-frame obtained through the inversion by the duration of the sub-frames, and multiplexing the result of the delaying and whichever of the positive sub-frame and the positive sub-frame obtained through the inversion is not the result of the delaying. The unipolar OFDM symbol frame can guarantee high power amplification efficiency and high transmission power efficiency, and is robust against a multi-path channel environment.

Abstract: When a receiver (200) receives a signal transmitted from a transmitter, an A/D converter (204) converts the signal into a digital signal having two or more levels by A/D conversion. A zero-level detector (207) converts the signal into a two-level digital signal of positive and negative levels. The converted signals are subjected to spectrum despreading by correlators (206, 208), respectively. Whichever signal has a higher intensity is selected by absolute value detectors (209, 210), a comparator (211), and a switch (212). A decoder (213) decodes the selected signal. In a receiving state where the zero-level detector (207) is selected, the transmitter transmits the transmission signal after the signal is converted into a two-level signal. In a receiving state where the A/D converter (204) is selected, the transmitter transmits the transmission signal after the signal is converted into a signal having two or more levels.

Abstract: There is provided a transmission system in which a data sequence is transmitted. The transmission system includes a transmitter that generates a transmission signal by converting pieces of data included in the data sequence into data waveforms each of which has (i) a level signal whose signal level is determined by a value of a corresponding one of the pieces of data and (ii) a timing edge indicating a timing to obtain the level signal, and transmits the generated transmission signal, and a receiver that detects the signal level of each of the data waveforms of the received transmission signal at the timing designated by the timing edge of the each data waveform, and outputs a data value corresponding to the detected signal level.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In a method of data transmission according to another embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. In a method of data transmission according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space.

Abstract: A high power electric pulse generator includes a charge storage device, a high voltage source for charging the charge storage device, a first photoconductor element connected to the reference potential and to the storage device, a second photoconductor element connected to the storage device and to a useful load, a first light source for delivering a pulse of light to the first photoconductor, a second light source for delivering a pulse of light to the second photoconductor and a synchronization device for synchronizing the emission delay between the first light source and the second light source. The first photoconductor and the second photoconductor are passive semiconductor elements with a linear regime forming photosensitive switches, with the first and second photoconductors being doped silicon photoconductors.

Abstract: According to an embodiment of the invention, a method and apparatus for signal modulation are described. According to an embodiment of the invention, a method comprises producing and transferring a modulated signal. The modulation of the signal is over a plurality of amplitude levels, including at least a first amplitude level, a second amplitude level and a third amplitude level, and over a plurality of time slots, including at least a first time slot, a second time slot, and a third time slot. The modulated signal transitions from the first amplitude level to the second amplitude level in the first phase slot, remains at the second amplitude level in the second time slot, and transitions from the second amplitude level to the third amplitude level in a third time slot.

Abstract: The present invention discloses an apparatus and a method of modulating a carrier with digital information having a series of datums represented in a plurality of symbols, the method comprising selecting a first number of half-periods of a first phase distinguished carrier signal for representing a corresponding symbol of a first one of the datums, selecting a second number of half-periods of a second phase distinguished carrier signal for representing a corresponding symbol of the datum following the first datum, determining at least one matching carrier signal having a third number of half-periods of a format to conform to a transition of the first phase distinguished carrier signal to the second phase distinguished carrier signal, and sequentially arranging the first number of half-periods of the first phase distinguished carrier signal, the third number of half-periods of the matching carrier signal and the second number of half-periods of the second phase distinguished carrier signal.

Abstract: A method for ultra wideband (UWB) communication in which UWB pulses encode binary data as either normal or inverted (anti-podal) pulses. In the case of pulses of a carrier signal, each pulse has the carrier signal either inverted or in phase, that is, shifted by 180°, or not. For example, a binary “1” may be encoded as a normal or non-inverted pulse and a binary “0” as an inverted pulse. After each carrier pulse is rectified and filtered, detection is effected using a threshold value of zero, resulting in increased immunity to noise, compared with detection of unidirectional pulses. In one aspect of the invention, data pertaining to multiple communication channels are encoded in time-divided portions of each UWB pulse.

Abstract: A communication system having an echo canceller is disclosed. One embodiment of the echo canceller includes an adaptive filter used to provide an estimate of reflected echo which is removed from the send signal. The echo canceller may also include a near-end talker signal detector which may be used to prevent the adaptive filter from adapting when a near-end talker signal is present. The echo canceller may also include a nonlinear processor used to further reduce any residual echo and to preserve background noise. The echo canceller may also include a monitor and control unit which may be used to monitor the filter coefficients and gain of the adaptive filter to maintain stability of the echo canceller, estimate pure delay, detect a tone, and inject a training signal. The echo canceller may also include a nonadaptive filter used to reduce the length of the adaptive filter.

Abstract: An ultra-wide band (UWB) waveform generator and encoder for use in a UWB digital communication system. The UWB waveform is made up of a sequence of shaped wavelets. The waveform generator produces multi-amplitude, multi-phase wavelets that are time-constrained, zero mean, and can be orthogonal in phase, yet still have a ?10 dB power spectral bandwidth that is larger than the frequency of the peak of the power spectrum In one embodiment, the wavelets are bi-phase wavelets. The encoder multiplies each data bit by an n-bit identifying code, (e.g., a user code), resulting in a group of wavelets corresponding to each data bit. The identifying codeword is passed onto the UWB waveform generator for generation of a UWB waveform that can be transmitted via an antenna.

Abstract: A system and a method for encoding and decoding ultra-wideband information are provided. An ultra-wideband transmission is encoded by positioning bipolar pulse pairs. The bipolar pulse pairs assist in detecting errors in the ultra-wideband transmission, before the entire transmission has been received. The transmission is analyzed for errors and an error rate is calculated. The calculated error rate is compared to one or more predefined acceptable error rate levels to determine whether the calculated error rate of the transmission is within at least one of the predefined acceptable error rate levels.

Abstract: A signal processing circuit generating a digital signal based on an input pulse signal is provided, which circuit includes a clock pulse output circuit which outputs clock pulses having one of positive and negative polarities for a period which includes a pulse of the input pulse signal, a counter circuit which counts the clock pulses, and an output circuit which outputs the digital signal based on a counted value of the counter circuit.

Abstract: Systems and methods are provided for controlling gain compensation over temperature and frequency variations. A variable amplifier may be used to receive a control signal and an input signal. The variable amplifier may be operable to apply a gain to the input signal to generate an output signal, wherein the gain is a function of the control signal. A summation module may be used to combine a gain reference signal and a gain variation signal to generate the control signal. The gain reference signal may be calibrated at a reference temperature and a reference frequency. A gain calibration module may be used to output the gain variation signal as a function of both a current operating temperature and a current operating frequency.

Abstract: In the prior art, it has been difficult to provide a data generator and a data generating method which serve to implement an efficient transmitter, as well as a transmitter utilizing this data generator. The present invention provides a raw data generator that generates, from an inputted signal, an I signal and a Q signal which are orthogonal to each other and an amplitude component of a quadrature signal composed of the I and Q signals, a delta sigma modulator that delta-sigma-modulates the amplitude component, a first multiplier that outputs first data obtained by multiplexing normalized I data obtained by dividing the I signal by the amplitude component, by the delta-sigma-modulated signal, and a second multiplier that outputs second data obtained by multiplexing normalized Q data obtained by dividing the Q signal by the amplitude component, by the delta-sigma-modulated signal.

Abstract: A system and a method for encoding and decoding ultra-wideband information are provided. An ultra-wideband transmission is encoded by positioning bipolar pulse pairs. The bipolar pulse pairs assist in detecting errors in the ultra-wideband transmission, before the entire transmission has been received. The transmission is analyzed for errors and an error rate is calculated. The calculated error rate is compared to one or more predefined acceptable error rate levels to determine whether the calculated error rate of the transmission is within at least one of the predefined acceptable error rate levels.

Abstract: An optical transmission system is provided, which permits high-precision optical transmission of a signal even if the signal has a high accurate timing, an indefinite period, and a DC component. The transmitting side is provided with a rise edge detecting circuit 1 for detecting the rise edge of a transmitting signal waveform, a transmitting pulse generating circuit 2 for generating a transmitting pulse signal (b) constituted by a pair of opposite-polarity pulses inverting their polarities at the detected timing, and a light intensity modulation circuit 3 for generating a light intensity modulated signal (c) based on the pulse signal (b). The receiving side is provided with an AC-coupled receiving circuit 4 for receiving the light intensity modulated signal (c) and extracting therefrom only an AC component, and a discrimination circuit 5 for discriminating the rise timing from the received signal.

Abstract: A method of modulating a phase reversing pulse train including a plurality of signal pulses each having an associated period of a given temporal duration to encode a multiplicity of input data bits each having a data state, and prevent losses of clock timing. The method includes the steps of: identifying select ones of the input data bits which repeat the data state of a respectively preceding one of the input data bits; identifying select ones of the pulses which correspond to the select bits; and, alternately shortening and lengthening the periods associated with the select ones of the pulses.

Abstract: A write/read device (1) for the contactless communication with at least one transponder has first coding means (4) for coding a data block (DB) in accordance with a first coding method, which first coding means (4) can generate at the most a given number of N coding signals (KI) per data block (DB) in accordance with this first coding method, and has second coding means (9) for coding a data block (DB) in accordance with a second coding method, which second coding means (9) can generate at the most a given number of M coding signals (KI) per data block (DB) in accordance with this second coding method, and has selection means (10) for the selection between the coding signals (KI) supplied by the first coding means (4) and the coding signals (KI) supplied by the second coding means (9).

Abstract: Disturbances in bipolar signals transmitted on a transmission line are suppressed by adjusting the amplitude of the signals with coarse adjustment steps and with fine adjustment steps. The amplitude adjusted signals are compared to at least a lower reference level and an upper reference level for determining a first percentage of the amplitude adjusted signals violating the lower reference level and a second percentage of the amplitude adjusted signals violating the upper reference level. The coarse adjustment steps and the fine adjustment steps are selected in accordance with an adjustment characteristic which evaluates at least the first percentage and the second percentage. The adjustment characteristic is changed if a tendency of reference level violation of the amplitude adjusted signals is detected and a check is performed if the step of changing the adjustment characteristic improves the disturbance suppression. A device for suppressing disturbances is also provided.

Abstract: A pulse signal transmitting circuit generates a pulse signal having an enhanced high-frequency component with a reduced power loss. A pulse signal is transmitted to a load circuit through a transmission cable connected to a secondary winding of a transformer. First and second transistors are connected to a primary winding of the transformer. A voltage output from an external power source is input to the primary winding of the transformer when at least one of the first and second transistors is conductive so that a pulse voltage signal is input to the transformer. A booster power supply circuit is located between the external power source and a middle point of the primary winding of the transformer. The booster power supply circuit superimposes a boost voltage onto the voltage input to the primary winding of the transformer so that a high-frequency component of the pulse voltage signal input to the primary winding of the transformer is enhanced.

Abstract: Methods and apparatus to transmit and receive information bits encoded in duobinary, multilevel pulse-amplitude-modulated (PAM) optical signals are described. The transmitted optical signal has a narrow optical spectrum and a low symbol rate. Information bits are encoded in a M-ary PAM symbol sequence, where M≧3. The subsequence-based encoder decomposes the PAM symbol sequence into M1 subsequences, precodes each subsequence, performs duobinary filtering on each precoded subsequence, and forms a weighted sum of the duobinary precoded subsequences. The weighted sum of duobinary precoded subsequences is lowpass filtered and modulated onto an optical electric field. The receiver processes a received optical electric field to obtain an electrical signal proportional to the received optical intensity, and performs M-ary symbol-by-symbol decisions to recover the transmitted information bits, without potential error propagation.

Abstract: Apparatus, and an accompanying method, for transmitting a frame synchronization signal and a data signal simultaneously through a serial transmission medium (170). Specifically within a data transmitter (105), a frame synchronization signal, a clock signal and a data signal, are encoded to form a single bi-phase mark signal having the frame synchronization signal incorporated into the bi-phase mark signal as a phase-shift. The bi-phase mark signal is then transmitted through a suitable serial transmission medium. A receiver (175), connected to the transmission medium, receives and amplifies an incoming bi-phase mark signal appearing on the medium, and, in turn, synthesizes the clock, frame synchronization, and data signals from this bi-phase mark signal.

Abstract: A signal processing circuit generating a digital signal based on an input pulse signal is provided, which circuit includes a clock pulse output circuit which outputs clock pulses having one of positive and negative polarities for a period which includes a pulse of the input pulse signal, a counter circuit which counts the clock pulses, and an output circuit which outputs the digital signal based on a counted value of the counter circuit.

Abstract: The present invention provides a method of generating a signal that may be used to determine the characteristic response of a communication channel that utilizes the public Digital Telephone Network (DTN). The channel includes the DTN, which may have Network Digital Attenuators (NDA) and/or Robbed Bit Signalling (RBS), and a Digital-to-Analog Converter (DAC), (also known as a codec), as well as the analog characteristics of the local loop, typically a twisted pair of copper wires. The present invention provides a method and apparatus to determine the optimal sampling instant of the received data stream. The present invention provides a probing signal that is well-suited for use in determining the channel's response to a known sequence of PCM codes used as data symbols. This is especially useful in so-called PCM modulation schemes that utilize the DTN, where knowledge of network and DAC distortion predicates the selection of available PCM codes used to represent data.

Abstract: A transmitter within a line driver circuit is configured to supply data signals in compliance with the Multilevel Transmission-3 (MLT-3) protocol for high speed data communication. The transmitter comprises a pre-driver system and a final driver. The pre-driver system comprises a plurality of individual pre-drivers that are in parallel. A zero drive logic designates any number of individual pre-drivers as zero drive types, such that these designated zero drive pre-drivers are turned ON during a zero signaling state. The partially turned ON pre-driver system, during the zero state, permits the final driver to rapidly output positive and negative signals in accord with the MLT-3 protocol.

Abstract: Disturbances in a bipolar signal in the case of large line lengths are suppressed. The signal is led to a coarse setting and a fine setting in an equalizer and to a downstream level detector. From there it is fed back to the equalizer via a control device. Sampling is performed in this case with the aid of a measuring clock pulse. The sampling clock pulse is dimensioned such that undersampling is carried out. Three reference levels are used, from which one digital sampled signal is derived in each case. A coarse setting or fine setting is initiated as a function of a percentage-prescribed number of upper and lower threshold violations.

Abstract: At least two level detectors compare a multilevel signal to respective prescribed voltage levels to produce corresponding streams of bits. These bit streams are repeatedly delayed in respective digital delay lines, and bits from the digital delay lines are output in parallel to multilevel decoder logic. The multilevel decoder logic converts the parallel bits into a plurality of corresponding two-level decoded bits and performs error detections for an invalid transition in the multilevel signal. The decoded bits may be descrambled and block decoded.

Abstract: An encoding circuit with a function of zero continuous-suppression in a data transmission system according to the present invention includes an EXZ detecting unit, a NRZ pulse generating unit and an output control unit. The EXZ detecting unit receives serial data indicating a NRZ signal and binary information indicating a code rule, and outputs EXZ pulses and delay data. The NRZ pulse generating unit receives the EXZ pulses from the EXZ detecting unit, and outputs an EXZ detecting signal, bipolar rule pulses and violation pulses. The output control unit receives the EXZ detecting signal, the bipolar rule pulses and the violation pulses, these are output from the NRZ pulse generating unit, and the delay data from the EXZ detecting unit, and outputs P-pole pulses and N-pole pulses to an external stage, and an odd signal to the NRZ pulse generating unit.

Abstract: A method and apparatus 200 for converting dual 4-wire digital data services (DDS-1 and DDS-2) for transmission over a single twisted pair telephone line 205. The present method includes use of a digital data service remote terminal 219 and a digital data service central office terminal 201. Each terminal converts more than one 4-wire digital data services into a 2B1Q signal for transmission over the single twisted pair telephone line 205. The present method provides an efficient and cost effective technique for increasing 4-wire digital data services to a customer premises without a corresponding increase in the number of telephone lines.

Abstract: An improved decoder for recovering Non-Return-to-Zero Interface (NRZI) digital data from a multiple layer transition (MLT-3) encoded signal in a 100BASE-TX Ethernet (IEEE Standard 802.3u) uses multiple comparators to minimize jitter in the decoded signal. A CMOS-based biasing circuit receives the differential MLT-3 encoded input signals and control signals from a signal amplitude detection circuit. The biasing circuit adjusts for any DC offset, and also generates offset signals based on respective mid-peak voltage values of the respective differential input signals. Four comparators are then used to detect a prescribed edge transition (e.g., a positive edge) coinciding with the respective mid-peak voltage value in the respective signals. The detected edge transitions are then used by edge decoding logic to generate the NRZI bilevel signal.

Abstract: An improved serial-digital data receiver that receives a scrambled NRZI voltage signal representing a transmitted serial-digital data signal converts the scrambled NRZI voltage signal in the analog domain to a bi-polar or pseudo-ternary voltage signal. The bi-polar voltage signal is then input to a slicer and clock recovery circuit to provide a recovered clock signal and a scrambled NRZ data signal in the digital domain. The scrambled NRZ data signal is then descrambled to recover the transmitted serial-digital data signal. Single bit error identification and limited correction may be included by using a sequential state machine decoder to generate an error flag and by using a "soft-decision" circuit to identify the probable bit error location.

Abstract: An optical transmission method and device consisting of coding a binary data pattern (SI) to be transmitted in the form of a second binary signal (SM), by differential coding; filtering the second binary signal (SM) to obtain a duobinary signal (SMF having three meaningful values (-1, 0.+-..epsilon., +a) and a narrower bandwidth; and modulating an optical carrier according to the values assumed by the filtered signal (SMF), the modulated carrier having a maximal amplitude to represent the maximal value (+a) and the minimal value (+a) of the duobinary signal (SMF), the phase of the modulated carrier being shifted by .theta..sub.1 and .theta..sub.2 =.theta..sub.1 +180.degree., respectively, and a minimal amplitude to represent values (0.+-..epsilon.) near 0 if the duobinary signal. The method of this invention is suitable for long distance fiber-optic transmissions.

Abstract: A burst-mode digital receiver which minimizes any reduction in the minimum input level as compared with a continuous-signal digital receiver includes a unipolar code-to-bipolar code converter for converging unipolar code pulses of an inputted burst signal into bipolar code pulses, an identifying circuit for identifying logic levels of "1" and "0" with an identifying level at a center of a pulse duration of bipolar code pulses outputted from the unipolar code-to-bipolar code converter, and a burst on/off detecting circuit for continuously outputting a signal until the inputted burst signal is finished when a pulse amplitude of the inputted burst signal exceeds a constant value. The burst-mode digital receiver produces an output signal when an AND gate connected to the output terminal of the identifying circuit is turned on at the time the output signal from the burst on/off detecting circuit is turned on.

Abstract: A bipolar-clock monitor circuit includes a first shift register shifting positive-polarity pulse signal according to the negative-polarity pulse signal to produce a i-bit-shift signal and a j-bit-shift signal. The integers i and j are determined based on the period ratio of a main clock and a subclock included in the bipolar clock signal so that the i-bit-shift signal is identical with the j-bit-shift signal when the bipolar clock signal is normal. The non-coincidence determination circuit checks whether the i-bit-shift signal coincides with the j-bit-shift signal and produces a disturbance detection signal when the i-bit-shift signal does not coincide with the j-bit-shift signal.

Abstract: A build-out Network (BON) built-in type balanced line driver circuit is provided. The (BON) built-in type balanced line driver circuit comprises a pair of transistors, the emitters of which are connected in common, and an impedance circuit connected between a power supply and respective collectors of the pair of the transistors. The impedance circuit has a reverse characteristic of the line characteristic of a balanced line connected between the collectors of the pair of transistors. The respective bases of the pair of transistors are supplied with unipolar data pulses (+DATA, -DATA).

Abstract: An optical communication system of a construction wherein the average wavelength dispersion value of the transmission optical fiber used, the optical output intensity of each optical amplifier repeater inserted in the transmission optical fiber and the widths of return-to-zero optical pulses transmitted over the transmission line are determined so as to compensate for the pulse compression effect by the nonlinear optical effect produced on the optical pulses by the pulse spreading effect by the wavelength dispersion effect. An optical multiplexer in the optical transmitting device time-division multiplexes the return-to-zero optical pulses, and the optical multiplexed signal is provided as an alternating-amplitude optical signal with the amplitudes of the return-to-zero optical pulses alternated.

Abstract: In a data bus with m data bits, electromagnetic interference is produced by polarity switching the data on that data bus. When two consecutive data items result in a change of over half of the data bits, the polarity of the second data item is switched, and a polarity signal is correspondingly switched on the data bus. When the data is received, it is restored to its original polarity by adjusting the polarity of the received data according to the signal on the polarity line. In this way, the total number of bit transitions between any two data items is reduced to a maximum of m/2.

Abstract: An apparatus and method for receiving line encoded bursts of information removes unwanted background light and has a maximum inter-packet idle time of only one bit between bursts. The invention permits the use of AC coupling in a receiver and results in outputting data with constant pulse widths irrespective of optical signal power levels, etc. . . In one embodiment, a receiver has a wide dynamic range, is highly stable, may be used over all frequencies of interest without developing high speed electronics or optical components, and has no sensitivity penalty as compared to existing burst mode/packet mode receivers. Because the receiver completely removes common signals, base line wander problems are also removed. The inventive apparatus and method is superior to existing burst mode/packet mode receivers in the presence of unwanted background light and long runs of "1"s and "0"s.