Abstract: Protection of a kernel from a sniff and code reuse attack. A kernel mode page table in initialized in a kernel. The kernel page entries in the kernel mode page table are set from s-pages to u-pages. Supervisor mode access prevention is enabled in the u-pages. Code contained in the kernel page entries in the u-pages is executed, the kernel page entries in the u-pages are capable of execution but are not capable of being accessed and read directly.

Abstract: A method, system, and apparatus are disclosed herein for bridging a deterministic phase of instructions with a non-deterministic phase of instructions when those instructions are executed by a machine learning accelerator while executing a machine learning network. Specifically, data is transferred from off-chip memory to on-chip memory (non-deterministic phase of instructions). The data transfer involves determining whether certain on-chip memory is already storing data that has not been consumed yet (e.g., certain memory locations on-chip may be storing data for future consumption and should not be overwritten). Based on determining that the certain on-chip memory is not storing data that has not been consumed yet, the data may be transferred from the off-chip memory to the on-chip memory and the target memory locations may be marked as storing data that has not been consumed yet. The deterministic phase of instructions may be started subsequently.

Abstract: An information handling system may include a host processor module comprising a host processor field programmable gate array, a management controller communicatively coupled to the host processor field programmable gate array and configured to provide out-of-band management facilities for management of the information handling system, and an interposer configured to interface between the host processor field programmable gate array and one or more peripheral devices in order to perform power management and control of the one or more peripheral device. The interposer may include a general purpose input/output extender configured to enable and control power delivery to the one or more peripheral devices and a microcontroller unit communicatively coupled to the host processor field programmable gate array and configured to perform monitoring and discovery of the one or more peripheral devices.

Abstract: An apparatus comprising a CPU core configured to execute instructions and consume data. The apparatus includes a memory configured to store the instructions and the data. A memory protection shim is coupled to the CPU core and the memory. The memory protection shim is configured to perform transformations over digital blocks to perform at least one of authentication or decryption of the digital blocks received from the memory. The memory protection shim is coupled to the CPU core in a fashion that prevents egress of the digital blocks or ingress of other external digital blocks between the memory protection shim and the CPU core.

Abstract: A computerized system operating in conjunction with computerized apparatus and with a fabric target service in data communication with the computerized apparatus, the system comprising functionality residing on the computerized apparatus, and functionality residing on the fabric target service, which, when operating in combination, enable the computerized apparatus to coordinate access to data.

Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.

Abstract: An example computing device includes a plurality of interfaces to connect to a plurality of audio peripheral devices, a communications interface to establish a network connection, and a processor interconnected with the plurality of interfaces and the communications interface. The processor is to determine a location of the computing device based on the network connection. The processor sets an audio peripheral device from the plurality of the audio peripheral devices as a default audio peripheral device based on the location. The processor communicates an audio signal through the default audio peripheral device.

Abstract: An apparatus comprising a CPU core configured to execute instructions and consume data. The apparatus includes a memory configured to store the instructions and the data. A memory protection shim is coupled to the CPU core and the memory. The memory protection shim is configured to perform transformations over digital blocks to perform at least one of authentication or decryption of the digital blocks received from the memory. The memory protection shim is coupled to the CPU core in a fashion that prevents egress of the digital blocks or ingress of other external digital blocks between the memory protection shim and the CPU core.

Abstract: A system is disclosed. The system may include a processor and a memory coupled to the processor. A storage device may also be coupled to the processor. The storage device may include a first interface and a second interface. The storage device may be configured to extend the memory. A mode switch may select a selected interface of the first interface and the second interface for a command issued by the processor.

Abstract: A surgical instrument is disclosed. The surgical instrument includes a first control circuit configured to communicate with an energy module using at least a first protocol over a first communication line and a second control circuit configured to communicate with another surgical instrument coupled to the surgical instrument using at least a second protocol over a second communication line.

Abstract: An adaptor includes non-volatile memory that stores a scan engine. A removable storage device is connected to the adaptor, which in turn is connected to a host computer. Files being copied between the removable storage device and the host computer through the adaptor are scanned for malware using the scan engine.

Abstract: The present application discloses a pre-reading method and system of a kernel client, and a computer-readable storage medium. The method includes: receiving a reading request for a file and determining whether the reading of the file is continuous; if the reading of the file is discontinuous, generating a head node of a file inode, and constructing a linked list embedded in the head node; determining whether the file includes a reading rule for the file, and if the file includes the reading rule for the file, acquiring, based on the reading rule, the number of reading requests for the file and a reading offset corresponding to each request, generating a map route based on the number of reading requests and corresponding reading offsets, and storing the map route in the linked list; and executing pre-reading based on the linked list.

Abstract: A display device is disclosed that includes a display panel, a data driver, a timing controller, a memory device, and a power voltage generator. The display panel includes pixels. The data driver is configured to apply data voltages to the pixels. The timing controller is configured to control the data driver, to generate a test strobe signal by shifting a phase of a strobe signal, to perform a test write operation and a test read operation with the memory device based on the test strobe signal, and to increase a power voltage when an error bit occurs in the test write operation and the test read operation. The memory device is configured to sample memory data received from the timing controller using the strobe signal and to store sampled memory data. The power voltage generator is configured to apply the power voltage to the memory device.

Abstract: Embodiments of a system and method to track the locality of a file being restored at the time of prefetching; and a mechanism to dynamically adjust the prefetching parallelism, per read batch, optimally based on the locality and other heuristics, such as system load. A process tracks locality of data elements in a batched data stream, as corresponds to a number of different container IDs accessed by the data elements. The prefetch nominally works serially on the data elements, however, if the locality exceeds a threshold separating acceptable versus non-acceptable distribution of data accesses, each batch is divided into a number of smaller sub-batches that are then pre-fetched in parallel with one another.

Abstract: An apparatus includes a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.

Abstract: Methods of memory allocation in which registers referenced by different groups of instances of the same task are mapped to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a privilege area and a normal area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a privilege mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: Method and apparatus for matched buffer decompression. In some examples, a circuit comprising a first data element, a second data element, a first buffer coupled to the first data element, a second buffer coupled to the second data element, compression override logic circuits coupled to the first data element and the second data element, and a parallel register coupled to the compression override logic circuits.

Abstract: Techniques that facilitate machine learning optimization are provided. In one example, a system includes a computational resource component, a batch interval component, and a machine learning component. The computational resource component collects computational resource data associated with a group of computing devices that performs a machine learning process. The batch interval component determines, based on the computational resource data, batch interval data indicative of a time interval to collect data for the machine learning process. The machine learning component provides the batch interval data to the group of computing devices to facilitate execution of the machine learning process based on the batch interval data.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a secure area and a non-secure area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a secure mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: A system and method rate limits database access to, for example, prevent or reduce damage from unauthorized or errant access of a database by enforcing a network-level limit to the amount of data that may be accessed from the database. In at least one embodiment, a data transfer rate limiter monitors data transfer and determines whether the data transfer exceeds one or more predetermined thresholds. Based on the determination, the data transfer rate limiter generates a control signal that controls one or more processes that appropriately address any the data rate transfer of concern.

Abstract: Systems and methods of writing data acquired from measurement instrumentation. Embodiments include establishing a direct data connection between the test equipment and a network storage drive, generating test data from a sample under test, and writing the test data to the network storage drive without assistance of a computerized controlling device configured to control the testing device.

Abstract: An integrated circuit (IC) includes an Input/Output (I/O) interface, first-domain circuitry and second-domain circuitry. The I/O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I/O interface with the bit value.

Abstract: A data intake and query system provides interfaces that enable users to configure source type definitions used by the system. A data intake and query system generally refers to a system for collecting and analyzing data including machine-generated data. Such a system may be configured to consume many different types of machine data generated by any number of different data sources including various servers, network devices, applications, etc. At a high level, a source type definition comprises one or more properties that define how various components of a data intake and query system collect, index, store, search and otherwise interact with particular types of data consumed by the system. The interfaces provided by the system generally comprise one or more interface components for configuring various attributes of a source type definition.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may fetch a first command from the host into a command queue, suspend execution of the first command when receiving a lock request for the first command from the host, and resume the execution of the first command when receiving an unlock request for the first command or after the first command is suspended for an amount of time corresponding to a suspend time value transmitted together with the lock request.

Abstract: Examples provide a method and apparatus for a multi-domain computing device providing physical separation of computing domains and network isolation. The multi-domain computing device includes a user facing panel with a shared display device and a keyboard, video mouse (KVM) switch. A set of domain-specific devices which are not shared between domains may include one or more processors, card readers, network devices, headset jacks, and power switches. The devices shared by the different domains include a display screen, power supply, the KVM switch and/or touchscreen. Each domain is configured to power up, boot and operate independently within a single physical unit.

Abstract: In response to a detected presence of an intended target appliance within a logical topography of controllable appliances identity information associated with the intended target appliance is used to automatically add to a graphical user interface of a controlling device an icon representative of the intended target appliance and to create at a Universal Control Engine a listing of communication methods for use in controlling corresponding functional operations of the intended target appliance. When the icon is later activated, the controlling device is placed into an operating state appropriate for controlling functional operations of the intended target appliance while the Universal Control Engine uses at least one of the communication methods to transmit at least one command to place the intended target appliance into a predetermined operating state.

Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for precisely tracking memory usage in a multi-process computing environment. One of the methods includes implementing an instance of a memory usage tracker (MUT) in each process running in a node of a computer system. A MUT can maintain an account of memory usage for each of multiple logical owners running on a process on which the MUT is running. The MUT can determine an actual memory quota for each owner, and enforce the actual memory quota of the owner. Enforcing the actual memory quota of the owner can include receiving each memory allocation request, checking each allocation request and a current state of the account against the actual quota, approving or rejecting each allocation request, communicating the approval or rejection to an underlying memory manager, and updating the owner account for each approved allocation request.

Abstract: An apparatus may be communicatively coupled to other nodes in a network. The apparatus may include a control circuit configured to repeatedly issue transmission cycles to the other nodes. A given transmission cycle may include a least one send slot for each of the other nodes to send data. The control circuit may be configured to initiate transmission cycles by issuing beacon signals to the other nodes. The control circuit may be configured to determine when to issue a beacon signal in a given transmission cycle by determining that all of the other nodes have completed all associated send slots in an immediately previous transmission cycle and based upon a determination of the completion of the other nodes' transmission, delaying transmission of the beacon signal for the given transmission cycle.

Abstract: Examples of lighting equipment provide services to and on behalf of a biomechatronically enhanced organism and/or a biomechatronic component of the organism. Such services include charging, communications, location-related services, control, optimization, client-server functions and distributed processing functionality. The biomechatronically enhanced organism anchor biomechatronic component utilize such services provided by and/or via the lighting equipment to enable, enhance or otherwise influence operation of the organism.

Abstract: Various methods, apparatuses/systems, and media for automating a process of receiving documentation are provided. A first computing device initiates an electronic communication process to request documentation from a second computing device utilized by a user. A processor receives identification information of the user for generating a unique barcode to be provided with the requested documentation in response to the initiation of the electronic communication. One or more processors generate the unique barcode based on the received identification information of the user; create an application programming interface (API) link for the generated barcode; transmit the electronic communication with the API link attached therein to the second computing device; and automatically obtain the unique barcode upon receiving an input to open the API link from the second computing device, the unique barcode to be attached as a cover sheet with the requested documentation for scanning by a multi-functional device.

Abstract: An intelligent method of scheduling garbage collection (GC) in a storage system. A GC scheduler obtains capacity utilization and ingest rate of the storage system and calculate therefrom a predicted capacity utilization. When the predicted capacity utilization reaches a threshold, the GC scheduler invokes GC, but otherwise skips GC until such time as predicted capacity utilization reaches the threshold. The ingest rage may be calculated by performing linear fit on past data ingest. The GC scheduler may calculate predicted capacity utilization periodically according to preset period. The GC scheduler may calculate the predicted capacity utilization to a future date beyond the next period. The future date may be at least as far as the next period plus total ingest time.

Abstract: A standalone Storage Controller with PCIe Multi-Mode capability that can be configured as PCIe Root-Complex (RC), an End-Point (EP) or a bridge (BR). In EP mode, the Storage Controller acts like a regular PCIe slaved controller which is connected to a PCIe Root-Complex provided by a Host via a PCIe port. While in RC mode, the Storage Controller acts as a PCIe configuration and management entity, a Host acting as a PCIe Root-Complex, which an add-in card or chip can attach to via a PCIe port that is provided by the Storage Controller, supporting any type of Network Device Interface, without an external Root-Complex. While in bridge mode, the Storage Controller can act as a transparent or non-transparent bridge with either a Root-Complex or End-Point port for the internal connection to the bridge.

Abstract: A network device may receive packets and may calculate, during a time interval, an arrival rate and a departure rate, of the packets, at one of multiple virtual output queues. The network device may calculate a current oversubscription factor based on the arrival rate and the departure rate, and may calculate a target oversubscription factor based on an average of previous oversubscription factors associated with the multiple virtual output queues. The network device may determine whether a difference exists between the target oversubscription factor and the current oversubscription factor and may calculate, when the difference exists, a scale factor based on the current oversubscription factor and the target oversubscription factor. The network device may calculate new scheduling weights based on prior scheduling weights and the scale factor, and may process packets received by the multiple virtual output queues based on the new scheduling weights.

Abstract: Examples of lighting equipment provide services to and on behalf of a biomechatronically enhanced organism and/or a biomechatronic component of the organism. Such services include charging, communications, location-related services, control, optimization, client-server functions and distributed processing functionality. The biomechatronically enhanced organism and/or biomechatronic component utilize such services provided by and/or via the lighting equipment to enable, enhance or otherwise influence operation of the organism.

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

Abstract: An object of the present disclosure is to suppress an increase in the time required for setting a peripheral device including driver installation. An embodiment of the present invention is a method including: a step for causing a display unit to display information of each of detected peripheral devices as a search result from a searching step; a step for causing a storage unit to store information of a peripheral device selected by a user from among the detected peripheral devices; an installation step for installing a driver that is compatible with the selected peripheral device; and a determination step for determining a port that is capable of communicating with the selected peripheral device, based on the information stored in the storage unit, wherein an installation process by the installation step and a communication-capable port determination process by the determination step are executed concurrently.

Abstract: Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security (such as intrusion and/or virus/malware prevention), performance, cost, and efficiency. For example, the processing chip includes at least one CPU and circuitry enabling the at least one CPU to securely boot from an external, non-volatile memory chip containing encrypted, executable code, and does not expose un-encrypted data, including the executable code, on an external memory interface, including a DRAM interface. Further, only the specific processing chip that was used to initially write the encrypted executable code to the external non-volatile memory chip is able to decrypt the encrypted executable code. The decryption uses a key unique to the processing chip and created at manufacturing time that is never CPU-accessible, forming a secure hardware association between the two chips.

Abstract: A set command is issued to transfer a diagnostic parameter record to a communication component of the computing environment. The diagnostic parameter record specifies a diagnostic action to be taken by the communication component to obtain diagnostic information and specifies a version of the diagnostic information to be obtained. Based, in part, on issuing the set command, the diagnostic information is obtained. The version of the diagnostic information obtained is the version specified, based on the version specified being supported by the communication component.

Abstract: A method, computer program product, and computer system for extending, by a computing device, transaction log page-buffers for Non-Volatile Random Access Memory (NVRAM) onto a solid state drive (SSD). It may be determined whether a bandwidth limit of the NVRAM has reached a threshold bandwidth. An IO may be processed on one of the NVRAM and the SSD based upon, at least in part, whether the bandwidth limit of the NVRAM has reached the threshold bandwidth.

Abstract: Some embodiments provide a method for a global manager that manages a logical network configuration for multiple datacenters that each have a local manager for managing the logical network configuration within the datacenter. Based on detecting that a connection to a particular local manager of a particular datacenter has been restored after a period of unavailability, the method identifies a portion of the logical network configuration that is relevant to the particular datacenter. In a series of transactions, the method transfers the identified portion of the logical network configuration to the particular local manager. During the series of transactions, the method identifies modifications to the identified portion of the logical network configuration to be included in the series of transactions. Upon completion of the series of transactions, the method transfers a notification to the particular local manager indicating completion of the series of transactions.

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

Abstract: Embodiments of the present disclosure relate to load balancing application processing between storage platforms. Input/output (I/O) workloads can be anticipated during one or more time-windows. Each I/O workload can comprise one or more I/O operations corresponding to one or more applications. Processing I/O operations of each application can be dynamically migrated to one or more storage platforms of a plurality of storage platforms based on the anticipated workload.

Abstract: A method and a system for transparently overlaying a logical transport network over an existing physical transport network is disclosed. The system designates a virtual channel located in a first transaction layer of a network conforming to a first network protocol. The system assembles a transaction layer packet in a second logical transaction layer of a second network protocol that is also recognizable by the first transaction layer. The system transfers the transaction layer packet from the second transaction layer to the virtual channel. The system transmits the transaction layer packet over the first transaction layer using the designated virtual channel over the network.

Abstract: Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the memory bus from memory. The memory controller associates a unique identifier with the given point in time. The memory controller identifies a given command associated with the arriving read data based on the given point in time.

Abstract: A method and system for protecting an aircraft against an incoherent command instruction. The system has a generation unit generating a command instruction transmitted to an evaluation unit that evaluates whether or not the command instruction is incoherent and generates and transmits a validation order if the command instruction is coherent or an arbitration request if not, the arbitration request being transmitted by an arbitration unit, where applicable, to an operator who sends a confirmation response or a cancellation response. The arbitration unit generates and transmits a validation order to an execution unit in the event of receiving a confirmation response and a cancellation order in the event of receiving a cancellation response, the system allowing the execution unit to execute only the command instructions evaluated and confirmed as not being incoherent.

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.

Abstract: Techniques are disclosed for using a forwarding microchip to implement a network functions virtualization (NFV) backplane within a network device. In one example, processing circuitry of a forwarding microchip establishes a respective logical connection between each of a plurality of virtual ports of the forwarding microchip and each of a plurality of virtual ports configured for respective software-implemented virtual network functions (VNFs) executing on the network device. The processing circuitry receives packets via one or more physical ports of the forwarding microchip and forwards, using the logical connections between each of the plurality of virtual ports of the forwarding microchip and each of the plurality of virtual ports configured for the respective software-implemented VNFs, the packets to a Network Interface Controller (NIC) for forwarding to the plurality of virtual ports configured for the respective software-implemented VNFs.